diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
@@ -33,37 +33,6 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
 declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, i32)
 declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
 
@@ -95,2940 +64,2932 @@
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i32:
+define void @test_vsuxseg2_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
 ; CHECK-NEXT:    vmv4r.v v12, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i32:
+define void @test_vsuxseg2_mask_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
 ; CHECK-NEXT:    vmv4r.v v12, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i16:
+define void @test_vsuxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i16:
+define void @test_vsuxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv32i16:
+define void @test_vsuxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv32i16:
+define void @test_vsuxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i32:
+define void @test_vsuxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i32:
+define void @test_vsuxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i16:
+define void @test_vsuxseg3_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i16:
+define void @test_vsuxseg3_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i8:
+define void @test_vsuxseg3_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i8:
+define void @test_vsuxseg3_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv8i32:
+define void @test_vsuxseg3_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv8i32:
+define void @test_vsuxseg3_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv64i8:
+define void @test_vsuxseg4_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv64i8:
+define void @test_vsuxseg4_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i8:
+define void @test_vsuxseg4_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i8:
+define void @test_vsuxseg4_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv1i16:
+define void @test_vsuxseg4_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv1i16:
+define void @test_vsuxseg4_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv32i8:
+define void @test_vsuxseg5_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv32i8:
+define void @test_vsuxseg5_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i8:
+define void @test_vsuxseg5_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i8:
+define void @test_vsuxseg5_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i32:
+define void @test_vsuxseg5_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i32:
+define void @test_vsuxseg5_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv2i16:
+define void @test_vsuxseg6_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv2i16:
+define void @test_vsuxseg6_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv4i32:
+define void @test_vsuxseg6_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv4i32:
+define void @test_vsuxseg6_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i16:
+define void @test_vsuxseg6_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i16:
+define void @test_vsuxseg6_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i8:
+define void @test_vsuxseg7_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i8:
+define void @test_vsuxseg7_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i8:
+define void @test_vsuxseg7_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i8:
+define void @test_vsuxseg7_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i32:
+define void @test_vsuxseg7_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i32:
+define void @test_vsuxseg7_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i16:
+define void @test_vsuxseg8_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i16:
+define void @test_vsuxseg8_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv32i16:
+define void @test_vsuxseg8_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv32i16:
+define void @test_vsuxseg8_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i32:
+define void @test_vsuxseg8_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i32:
+define void @test_vsuxseg8_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i16:
+define void @test_vsuxseg2_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i16:
+define void @test_vsuxseg2_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i8:
+define void @test_vsuxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i8:
+define void @test_vsuxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv8i32:
+define void @test_vsuxseg2_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv8i32:
+define void @test_vsuxseg2_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv64i8:
+define void @test_vsuxseg3_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv64i8:
+define void @test_vsuxseg3_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i8:
+define void @test_vsuxseg3_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i8:
+define void @test_vsuxseg3_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv1i16:
+define void @test_vsuxseg3_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv1i16:
+define void @test_vsuxseg3_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv32i8:
+define void @test_vsuxseg4_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv32i8:
+define void @test_vsuxseg4_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i8:
+define void @test_vsuxseg4_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i8:
+define void @test_vsuxseg4_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv16i32:
+define void @test_vsuxseg4_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv16i32:
+define void @test_vsuxseg4_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vmv2r.v v14, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv2i16:
+define void @test_vsuxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv2i16:
+define void @test_vsuxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg2_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i8_nxv4i32:
+define void @test_vsuxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_nxv4i32:
+define void @test_vsuxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i16:
+define void @test_vsuxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i16:
+define void @test_vsuxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i8:
+define void @test_vsuxseg3_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
+define void @test_vsuxseg3_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i8:
+define void @test_vsuxseg3_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i8:
+define void @test_vsuxseg3_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i32:
+define void @test_vsuxseg3_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i32:
+define void @test_vsuxseg3_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i16:
+define void @test_vsuxseg4_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i16:
+define void @test_vsuxseg4_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i32:
+define void @test_vsuxseg4_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i32:
+define void @test_vsuxseg4_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i16:
+define void @test_vsuxseg4_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i16:
+define void @test_vsuxseg4_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i8:
+define void @test_vsuxseg5_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i8:
+define void @test_vsuxseg5_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i8:
+define void @test_vsuxseg5_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i8:
+define void @test_vsuxseg5_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv1i16:
+define void @test_vsuxseg5_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv1i16:
+define void @test_vsuxseg5_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i8:
+define void @test_vsuxseg6_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i8:
+define void @test_vsuxseg6_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv16i32:
+define void @test_vsuxseg6_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv16i32:
+define void @test_vsuxseg6_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv2i16:
+define void @test_vsuxseg6_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv2i16:
+define void @test_vsuxseg6_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i8_nxv4i32:
+define void @test_vsuxseg7_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_nxv4i32:
+define void @test_vsuxseg7_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i16:
+define void @test_vsuxseg7_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i16:
+define void @test_vsuxseg7_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i8:
+define void @test_vsuxseg7_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i8:
+define void @test_vsuxseg7_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i8:
+define void @test_vsuxseg8_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i8:
+define void @test_vsuxseg8_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i32:
+define void @test_vsuxseg8_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i32:
+define void @test_vsuxseg8_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i16:
+define void @test_vsuxseg8_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i16:
+define void @test_vsuxseg8_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv32i16:
+define void @test_vsuxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv32i16:
+define void @test_vsuxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i32:
+define void @test_vsuxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i32:
+define void @test_vsuxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i16:
+define void @test_vsuxseg2_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i16:
+define void @test_vsuxseg2_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i8:
+define void @test_vsuxseg3_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i8:
+define void @test_vsuxseg3_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv64i8:
+define void @test_vsuxseg3_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv64i8:
+define void @test_vsuxseg3_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i8:
+define void @test_vsuxseg3_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i8:
+define void @test_vsuxseg3_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv1i16:
+define void @test_vsuxseg4_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv1i16:
+define void @test_vsuxseg4_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i8:
+define void @test_vsuxseg4_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i8:
+define void @test_vsuxseg4_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv16i32:
+define void @test_vsuxseg4_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv16i32:
+define void @test_vsuxseg4_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv2i16:
+define void @test_vsuxseg5_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv2i16:
+define void @test_vsuxseg5_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i8_nxv4i32:
+define void @test_vsuxseg5_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_nxv4i32:
+define void @test_vsuxseg5_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i16:
+define void @test_vsuxseg5_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i16:
+define void @test_vsuxseg5_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i8:
+define void @test_vsuxseg6_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i8:
+define void @test_vsuxseg6_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i8:
+define void @test_vsuxseg6_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i8:
+define void @test_vsuxseg6_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i32:
+define void @test_vsuxseg6_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i32:
+define void @test_vsuxseg6_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i16:
+define void @test_vsuxseg7_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i16:
+define void @test_vsuxseg7_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv32i16:
+define void @test_vsuxseg7_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv32i16:
+define void @test_vsuxseg7_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i32:
+define void @test_vsuxseg7_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i32:
+define void @test_vsuxseg7_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i16:
+define void @test_vsuxseg8_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i16:
+define void @test_vsuxseg8_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i8:
+define void @test_vsuxseg8_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i8:
+define void @test_vsuxseg8_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv8i32:
+define void @test_vsuxseg8_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv8i32:
+define void @test_vsuxseg8_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+define void @test_vsuxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv64i8:
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i8:
+define void @test_vsuxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i8:
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv1i16:
+define void @test_vsuxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv1i16:
+define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv32i8:
+define void @test_vsuxseg3_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv32i8:
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i8:
+define void @test_vsuxseg3_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i8:
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv16i32:
+define void @test_vsuxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv16i32:
+define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv2i16:
+define void @test_vsuxseg4_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv2i16:
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i8_nxv4i32:
+define void @test_vsuxseg4_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_nxv4i32:
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i16:
+define void @test_vsuxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i16:
+define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i8:
+define void @test_vsuxseg5_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i8:
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i8:
+define void @test_vsuxseg5_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i8:
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i32:
+define void @test_vsuxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i32:
+define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i16:
+define void @test_vsuxseg6_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3036,16 +2997,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i16:
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3053,56 +3014,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i32:
+define void @test_vsuxseg6_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3110,16 +3034,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i32:
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3127,19 +3051,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i16:
+define void @test_vsuxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3147,16 +3071,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i16:
+define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3164,19 +3088,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i8:
+define void @test_vsuxseg7_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3184,16 +3108,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i8:
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3201,19 +3126,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv8i32:
+define void @test_vsuxseg7_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3221,16 +3147,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv8i32:
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3238,56 +3165,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i8:
+define void @test_vsuxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3295,16 +3186,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i8:
+define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3312,19 +3204,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv1i16:
+define void @test_vsuxseg8_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3332,16 +3225,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv1i16:
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3349,19 +3244,21 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv32i8:
+define void @test_vsuxseg8_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3369,16 +3266,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv32i8:
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3386,19 +3285,21 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i8:
+define void @test_vsuxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -3406,16 +3307,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i8:
+define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -3423,832 +3326,690 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv16i32:
+define void @test_vsuxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv16i32:
+define void @test_vsuxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv2i16:
+declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
+
+define void @test_vsuxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv2i16:
+define void @test_vsuxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg6_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i8_nxv4i32:
+define void @test_vsuxseg2_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_nxv4i32:
+define void @test_vsuxseg2_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i16:
+define void @test_vsuxseg3_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i16:
+define void @test_vsuxseg3_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i8:
+define void @test_vsuxseg3_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i8:
+define void @test_vsuxseg3_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i8:
+define void @test_vsuxseg3_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i8:
+define void @test_vsuxseg3_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i32:
+define void @test_vsuxseg4_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i32:
+define void @test_vsuxseg4_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i16:
+define void @test_vsuxseg4_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i16:
+define void @test_vsuxseg4_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
+
+define void @test_vsuxseg4_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
+  ret void
+}
+
+define void @test_vsuxseg4_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv32i16:
+define void @test_vsuxseg2_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv32i16:
+define void @test_vsuxseg2_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i32:
+define void @test_vsuxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i32:
+define void @test_vsuxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i16:
+define void @test_vsuxseg2_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i16:
+define void @test_vsuxseg2_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i8:
+define void @test_vsuxseg3_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i8:
+define void @test_vsuxseg3_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv8i32:
+define void @test_vsuxseg3_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv8i32:
+define void @test_vsuxseg3_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv64i8:
+define void @test_vsuxseg3_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv64i8:
+define void @test_vsuxseg3_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
 ; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i8:
+define void @test_vsuxseg4_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i8:
+define void @test_vsuxseg4_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv1i16:
+define void @test_vsuxseg4_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv1i16:
+define void @test_vsuxseg4_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv32i8:
+define void @test_vsuxseg4_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv32i8:
+define void @test_vsuxseg4_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v10, v8
+; CHECK-NEXT:    vmv1r.v v11, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i8:
+define void @test_vsuxseg5_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i8:
+define void @test_vsuxseg5_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv2i16:
+define void @test_vsuxseg5_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv2i16:
+define void @test_vsuxseg5_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg7_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i8_nxv4i32:
+define void @test_vsuxseg5_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_nxv4i32:
+define void @test_vsuxseg5_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i16:
+define void @test_vsuxseg6_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4256,18 +4017,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i16:
+define void @test_vsuxseg6_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4275,21 +4034,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i8:
+define void @test_vsuxseg6_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4297,18 +4054,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i8:
+define void @test_vsuxseg6_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4316,21 +4071,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i8:
+define void @test_vsuxseg6_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4338,18 +4091,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i8:
+define void @test_vsuxseg6_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4357,21 +4108,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i32:
+define void @test_vsuxseg7_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4380,17 +4129,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i32:
+define void @test_vsuxseg7_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4399,20 +4147,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i16:
+define void @test_vsuxseg7_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4421,17 +4168,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i16:
+define void @test_vsuxseg7_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4440,61 +4186,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i32:
+define void @test_vsuxseg7_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4503,17 +4207,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i32:
+define void @test_vsuxseg7_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4522,20 +4225,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i16:
+define void @test_vsuxseg8_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4545,16 +4247,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i16:
+define void @test_vsuxseg8_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4564,19 +4266,19 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i8:
+define void @test_vsuxseg8_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4586,16 +4288,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i8:
+define void @test_vsuxseg8_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4605,19 +4307,19 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv8i32:
+define void @test_vsuxseg8_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -4627,16 +4329,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv8i32:
+define void @test_vsuxseg8_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -4646,67129 +4348,1315 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv64i8:
+define void @test_vsuxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv64i8:
+define void @test_vsuxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i8:
+define void @test_vsuxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i8:
+define void @test_vsuxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv1i16:
+define void @test_vsuxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv1i16:
+define void @test_vsuxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv32i8:
+define void @test_vsuxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv32i8:
+define void @test_vsuxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i8:
+define void @test_vsuxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i8:
+define void @test_vsuxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv16i32:
+define void @test_vsuxseg2_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv16i32:
+define void @test_vsuxseg2_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv2i16:
+define void @test_vsuxseg3_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv2i16:
+define void @test_vsuxseg3_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg8_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i8_nxv4i32:
+define void @test_vsuxseg3_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_nxv4i32:
+define void @test_vsuxseg3_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i16:
+define void @test_vsuxseg3_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i16:
+define void @test_vsuxseg3_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i8:
+define void @test_vsuxseg4_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i8:
+define void @test_vsuxseg4_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i8:
+define void @test_vsuxseg4_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i8:
+define void @test_vsuxseg4_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i32:
+define void @test_vsuxseg4_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i32:
+define void @test_vsuxseg4_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i16:
+define void @test_vsuxseg5_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i16:
+define void @test_vsuxseg5_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv32i16:
+define void @test_vsuxseg5_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv32i16:
+define void @test_vsuxseg5_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i32:
+define void @test_vsuxseg5_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i32:
+define void @test_vsuxseg5_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i16:
+define void @test_vsuxseg6_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i16:
+define void @test_vsuxseg6_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i8:
+define void @test_vsuxseg6_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i8:
+define void @test_vsuxseg6_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv8i32:
+define void @test_vsuxseg6_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv8i32:
+define void @test_vsuxseg6_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv64i8:
+define void @test_vsuxseg7_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv64i8:
+define void @test_vsuxseg7_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i8:
+define void @test_vsuxseg7_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i8:
+define void @test_vsuxseg7_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv1i16:
+define void @test_vsuxseg7_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv1i16:
+define void @test_vsuxseg7_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv32i8:
+define void @test_vsuxseg8_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv32i8:
+define void @test_vsuxseg8_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i8:
+define void @test_vsuxseg8_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i8:
+define void @test_vsuxseg8_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv16i32:
+define void @test_vsuxseg8_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv16i32:
+define void @test_vsuxseg8_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv2i16:
+define void @test_vsuxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv2i16:
+define void @test_vsuxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg2_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16i8_nxv4i32:
+define void @test_vsuxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_nxv4i32:
+define void @test_vsuxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i16:
+define void @test_vsuxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i16:
+define void @test_vsuxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i8:
+define void @test_vsuxseg3_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i8:
+define void @test_vsuxseg3_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i8:
+define void @test_vsuxseg3_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i8:
+define void @test_vsuxseg3_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i32:
+define void @test_vsuxseg3_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i32:
+define void @test_vsuxseg3_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i16:
+define void @test_vsuxseg4_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i16:
+define void @test_vsuxseg4_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv32i16:
+define void @test_vsuxseg4_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv32i16:
+define void @test_vsuxseg4_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i32:
+define void @test_vsuxseg4_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i32:
+define void @test_vsuxseg4_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i16:
+define void @test_vsuxseg5_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i16:
+define void @test_vsuxseg5_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i8:
+define void @test_vsuxseg5_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i8:
+define void @test_vsuxseg5_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv8i32:
+define void @test_vsuxseg5_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv8i32:
+define void @test_vsuxseg5_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv64i8:
+define void @test_vsuxseg6_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv64i8:
+define void @test_vsuxseg6_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i8:
+define void @test_vsuxseg6_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i8:
+define void @test_vsuxseg6_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg3_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg4_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg5_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg6_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg7_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg8_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv32i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv32i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv64i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv64i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv64i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv1i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv1i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv1i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv32i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv32i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv32i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv16i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv16i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv16i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv2i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv2i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv2i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8i32_nxv4i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8i32.nxv4i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8i32_nxv4i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv8i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv8i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv8i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv64i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv64i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv64i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv1i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv1i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv1i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv16i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv16i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv16i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv2i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv2i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv2i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, <vscale x 32 x i1>, i32)
-
-define void @test_vsuxseg2_nxv32i8_nxv4i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv4i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv32i8_nxv4i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i8(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i8(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i32(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i32(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i16(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i16(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv32i16(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv32i16(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i32(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i32(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i16(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i16(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i8(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i8(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv8i32(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv8i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv8i32(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv64i8(<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv64i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv64i8(<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i8(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i8(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv1i16(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv1i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv1i16(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv32i8(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv32i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv32i8(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i8(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i8(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv2i16(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv2i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv2i16(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, <vscale x 16 x i1>, i32)
-
-define void @test_vsuxseg2_nxv16f16_nxv4i32(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv4i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv16f16_nxv4i32(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i16(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i16(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i8(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i8(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i8(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i8(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i32(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i32(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv32i16(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv32i16(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i32(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i32(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i16(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i16(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i8(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i8(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv8i32(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv8i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv8i32(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv64i8(<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv64i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv64i8(<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv1i16(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv1i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv1i16(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv32i8(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv32i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv32i8(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i8(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i8(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv16i32(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv16i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv16i32(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv2i16(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv2i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv2i16(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg5_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg8_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg2_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg3_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg4_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg5_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg6_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg7_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i32)
-
-define void @test_vsuxseg8_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg3_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg4_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i16(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i16(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i8(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i8(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i8(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i8(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i32(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i32(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i16(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i16(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv32i16(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv32i16(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i32(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i32(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv64i8(<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv64i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv64i8(<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i8(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i8(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv1i16(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv1i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv1i16(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv32i8(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv32i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv32i8(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v28, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i8(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i8(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv16i32(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv16i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv16i32(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv2i16(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv2i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv2i16(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv1r.v v25, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, <vscale x 8 x i1>, i32)
-
-define void @test_vsuxseg2_nxv8f32_nxv4i32(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv4i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv8f32_nxv4i32(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
-; CHECK-NEXT:    vmv2r.v v26, v12
-; CHECK-NEXT:    vmv4r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg3_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg4_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg2_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg3_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg3_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv1i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv32i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv2i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg5_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg5_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i8:
+define void @test_vsuxseg6_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -71776,16 +5664,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i8:
+define void @test_vsuxseg6_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -71793,19 +5681,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i32:
+define void @test_vsuxseg7_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -71813,16 +5701,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i32:
+define void @test_vsuxseg7_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -71830,19 +5719,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i16:
+define void @test_vsuxseg7_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -71850,73 +5740,38 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg6_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv32i16:
+define void @test_vsuxseg7_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i32:
+define void @test_vsuxseg7_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -71924,16 +5779,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i32:
+define void @test_vsuxseg7_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -71941,19 +5797,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i16:
+define void @test_vsuxseg8_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -71961,16 +5818,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i16:
+define void @test_vsuxseg8_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -71978,19 +5837,21 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i8:
+define void @test_vsuxseg8_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -71998,16 +5859,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i8:
+define void @test_vsuxseg8_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72015,19 +5878,21 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv8i32:
+define void @test_vsuxseg8_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72035,16 +5900,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv8i32:
+define void @test_vsuxseg8_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72052,471 +5919,471 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, <vscale x 32 x i1>, i32)
+
+define void @test_vsuxseg2_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i32 %vl)
+  ret void
+}
+
+define void @test_vsuxseg2_mask_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, <vscale x 32 x i1>, i32)
+
+define void @test_vsuxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i32 %vl)
+  ret void
+}
+
+define void @test_vsuxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv64i8:
+define void @test_vsuxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv64i8:
+define void @test_vsuxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i8:
+define void @test_vsuxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i8:
+define void @test_vsuxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv1i16:
+define void @test_vsuxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv1i16:
+define void @test_vsuxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv32i8:
+define void @test_vsuxseg3_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv32i8:
+define void @test_vsuxseg3_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i8:
+define void @test_vsuxseg3_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i8:
+define void @test_vsuxseg3_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv16i32:
+define void @test_vsuxseg3_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv16i32:
+define void @test_vsuxseg3_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv2i16:
+define void @test_vsuxseg4_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv2i16:
+define void @test_vsuxseg4_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg6_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i32:
+define void @test_vsuxseg4_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i32:
+define void @test_vsuxseg4_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i16:
+define void @test_vsuxseg4_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i16:
+define void @test_vsuxseg4_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i8:
+define void @test_vsuxseg5_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i8:
+define void @test_vsuxseg5_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i8:
+define void @test_vsuxseg5_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i8:
+define void @test_vsuxseg5_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i32:
+define void @test_vsuxseg5_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i32:
+define void @test_vsuxseg5_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i16:
+define void @test_vsuxseg6_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72524,17 +6391,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i16:
+define void @test_vsuxseg6_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72542,59 +6408,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i32:
+define void @test_vsuxseg6_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72602,17 +6428,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i32:
+define void @test_vsuxseg6_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72620,20 +6445,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i16:
+define void @test_vsuxseg6_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72641,17 +6465,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i16:
+define void @test_vsuxseg6_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72659,20 +6482,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i8:
+define void @test_vsuxseg7_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72681,16 +6503,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i8:
+define void @test_vsuxseg7_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72699,19 +6521,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv8i32:
+define void @test_vsuxseg7_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72720,16 +6542,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv8i32:
+define void @test_vsuxseg7_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72738,58 +6560,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg7_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i8:
+define void @test_vsuxseg7_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72798,16 +6581,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i8:
+define void @test_vsuxseg7_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72816,19 +6599,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv1i16:
+define void @test_vsuxseg8_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72837,16 +6620,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv1i16:
+define void @test_vsuxseg8_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72855,19 +6639,20 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv32i8:
+define void @test_vsuxseg8_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72876,16 +6661,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv32i8:
+define void @test_vsuxseg8_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72894,19 +6680,20 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i8:
+define void @test_vsuxseg8_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -72915,16 +6702,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i8:
+define void @test_vsuxseg8_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -72933,505 +6721,410 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv16i32:
+define void @test_vsuxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv16i32:
+define void @test_vsuxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv2i16:
+define void @test_vsuxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv2i16:
+define void @test_vsuxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg7_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i32:
+define void @test_vsuxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i32:
+define void @test_vsuxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i16:
+define void @test_vsuxseg3_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i16:
+define void @test_vsuxseg3_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i8:
+define void @test_vsuxseg3_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i8:
+define void @test_vsuxseg3_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i8:
+define void @test_vsuxseg3_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i8:
+define void @test_vsuxseg3_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i32:
+define void @test_vsuxseg4_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i32:
+define void @test_vsuxseg4_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i16:
+define void @test_vsuxseg4_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i16:
+define void @test_vsuxseg4_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv32i16:
+define void @test_vsuxseg4_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv32i16:
+define void @test_vsuxseg4_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i32:
+define void @test_vsuxseg5_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i32:
+define void @test_vsuxseg5_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i16:
+define void @test_vsuxseg5_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i16:
+define void @test_vsuxseg5_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i8:
+define void @test_vsuxseg5_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i8:
+define void @test_vsuxseg5_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv8i32:
+define void @test_vsuxseg6_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -73439,18 +7132,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv8i32:
+define void @test_vsuxseg6_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -73458,62 +7149,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i8:
+define void @test_vsuxseg6_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -73521,18 +7169,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i8:
+define void @test_vsuxseg6_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -73540,21 +7186,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv1i16:
+define void @test_vsuxseg6_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -73562,18 +7206,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv1i16:
+define void @test_vsuxseg6_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -73581,21 +7223,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv32i8:
+define void @test_vsuxseg7_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -73604,17 +7244,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv32i8:
+define void @test_vsuxseg7_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -73623,20 +7262,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i8:
+define void @test_vsuxseg7_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -73645,17 +7283,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i8:
+define void @test_vsuxseg7_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -73664,61 +7301,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg8_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg8_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv2i16:
+define void @test_vsuxseg7_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -73727,17 +7322,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv2i16:
+define void @test_vsuxseg7_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -73746,20 +7340,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i32:
+define void @test_vsuxseg8_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -73769,16 +7362,16 @@
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
 ; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i32:
+define void @test_vsuxseg8_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -73788,2415 +7381,2442 @@
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
 ; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i8:
+define void @test_vsuxseg8_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i8:
+define void @test_vsuxseg8_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i32:
+define void @test_vsuxseg8_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i32:
+define void @test_vsuxseg8_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
 ; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i16:
+define void @test_vsuxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i16:
+define void @test_vsuxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i8:
+define void @test_vsuxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i8:
+define void @test_vsuxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
 ; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg2_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg2_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv8i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv64i8:
+define void @test_vsuxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv64i8:
+define void @test_vsuxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i8:
+define void @test_vsuxseg3_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i8:
+define void @test_vsuxseg3_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv1i16:
+define void @test_vsuxseg3_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv1i16:
+define void @test_vsuxseg3_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv32i8:
+define void @test_vsuxseg3_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv32i8:
+define void @test_vsuxseg3_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i8:
+define void @test_vsuxseg4_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i8:
+define void @test_vsuxseg4_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv16i32:
+define void @test_vsuxseg4_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv16i32:
+define void @test_vsuxseg4_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i16:
+define void @test_vsuxseg4_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i16:
+define void @test_vsuxseg4_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v25, v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg2_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv4i32:
+define void @test_vsuxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv4i32:
+define void @test_vsuxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i16:
+define void @test_vsuxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i16:
+define void @test_vsuxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i8:
+define void @test_vsuxseg2_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv16f16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i8:
+define void @test_vsuxseg2_mask_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i8:
+define void @test_vsuxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i8:
+define void @test_vsuxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i32:
+define void @test_vsuxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i32:
+define void @test_vsuxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i16:
+define void @test_vsuxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i16:
+define void @test_vsuxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv32i16:
+define void @test_vsuxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv32i16:
+define void @test_vsuxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i32:
+define void @test_vsuxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i32:
+define void @test_vsuxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i16:
+define void @test_vsuxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i16:
+define void @test_vsuxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i8:
+define void @test_vsuxseg3_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i8:
+define void @test_vsuxseg3_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv8i32:
+define void @test_vsuxseg3_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv8i32:
+define void @test_vsuxseg3_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv64i8:
+define void @test_vsuxseg3_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv64i8:
+define void @test_vsuxseg3_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i8:
+define void @test_vsuxseg4_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i8:
+define void @test_vsuxseg4_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv1i16:
+define void @test_vsuxseg4_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv1i16:
+define void @test_vsuxseg4_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv32i8:
+define void @test_vsuxseg4_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv32i8:
+define void @test_vsuxseg4_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i8:
+define void @test_vsuxseg5_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i8:
+define void @test_vsuxseg5_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv16i32:
+define void @test_vsuxseg5_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv16i32:
+define void @test_vsuxseg5_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i16:
+define void @test_vsuxseg5_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i16:
+define void @test_vsuxseg5_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg3_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv4i32:
+define void @test_vsuxseg6_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv4i32:
+define void @test_vsuxseg6_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i16:
+define void @test_vsuxseg6_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i16:
+define void @test_vsuxseg6_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i8:
+define void @test_vsuxseg6_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i8:
+define void @test_vsuxseg6_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i8:
+define void @test_vsuxseg7_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i8:
+define void @test_vsuxseg7_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i32:
+define void @test_vsuxseg7_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i32:
+define void @test_vsuxseg7_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i16:
+define void @test_vsuxseg7_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i16:
+define void @test_vsuxseg7_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv32i16:
+define void @test_vsuxseg8_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv32i16:
+define void @test_vsuxseg8_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i32:
+define void @test_vsuxseg8_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i32:
+define void @test_vsuxseg8_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i16:
+define void @test_vsuxseg8_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i16:
+define void @test_vsuxseg8_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i8:
+define void @test_vsuxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i8:
+define void @test_vsuxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv8i32:
+define void @test_vsuxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv8i32:
+define void @test_vsuxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv64i8:
+define void @test_vsuxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv64i8:
+define void @test_vsuxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i8:
+define void @test_vsuxseg3_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i8:
+define void @test_vsuxseg3_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv1i16:
+define void @test_vsuxseg3_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv1i16:
+define void @test_vsuxseg3_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv32i8:
+define void @test_vsuxseg3_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv32i8:
+define void @test_vsuxseg3_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i8:
+define void @test_vsuxseg4_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
+  ret void
+}
+
+define void @test_vsuxseg4_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
+
+define void @test_vsuxseg4_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i8:
+define void @test_vsuxseg4_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
 ; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv16i32:
+define void @test_vsuxseg4_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv16i32:
+define void @test_vsuxseg4_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i16:
+define void @test_vsuxseg5_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i16:
+define void @test_vsuxseg5_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv4i32:
+define void @test_vsuxseg5_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv4i32:
+define void @test_vsuxseg5_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i16:
+define void @test_vsuxseg5_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i16:
+define void @test_vsuxseg5_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i8:
+define void @test_vsuxseg6_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i8:
+define void @test_vsuxseg6_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i8:
+define void @test_vsuxseg6_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i8:
+define void @test_vsuxseg6_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i32:
+define void @test_vsuxseg6_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i32:
+define void @test_vsuxseg6_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i16:
+define void @test_vsuxseg7_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i16:
+define void @test_vsuxseg7_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv32i16:
+define void @test_vsuxseg7_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv32i16:
+define void @test_vsuxseg7_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i32:
+define void @test_vsuxseg7_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i32:
+define void @test_vsuxseg7_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i16:
+define void @test_vsuxseg8_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i16:
+define void @test_vsuxseg8_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i8:
+define void @test_vsuxseg8_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i8:
+define void @test_vsuxseg8_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv8i32:
+define void @test_vsuxseg8_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv8i32:
+define void @test_vsuxseg8_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
+
+define void @test_vsuxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  ret void
+}
+
+define void @test_vsuxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv64i8:
+define void @test_vsuxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv64i8:
+define void @test_vsuxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
+
+define void @test_vsuxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  ret void
+}
+
+define void @test_vsuxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i8:
+define void @test_vsuxseg3_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i8:
+define void @test_vsuxseg3_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv1i16:
+define void @test_vsuxseg3_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv1i16:
+define void @test_vsuxseg3_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv32i8:
+define void @test_vsuxseg3_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv32i8:
+define void @test_vsuxseg3_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i8:
+define void @test_vsuxseg4_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i8:
+define void @test_vsuxseg4_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv16i32:
+define void @test_vsuxseg4_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv16i32:
+define void @test_vsuxseg4_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i16:
+define void @test_vsuxseg4_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i16:
+define void @test_vsuxseg4_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg5_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv4i32:
+define void @test_vsuxseg5_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg5_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv4i32:
+define void @test_vsuxseg5_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i16:
+define void @test_vsuxseg5_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i16:
+define void @test_vsuxseg5_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i8:
+define void @test_vsuxseg5_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i8:
+define void @test_vsuxseg5_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i8:
+define void @test_vsuxseg6_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76204,16 +9824,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i8:
+define void @test_vsuxseg6_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76221,19 +9841,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i32:
+define void @test_vsuxseg6_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76241,16 +9861,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i32:
+define void @test_vsuxseg6_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76258,19 +9878,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i16:
+define void @test_vsuxseg6_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76278,16 +9898,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i16:
+define void @test_vsuxseg6_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76295,56 +9915,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv32i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v8, (a0), v16, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i32:
+define void @test_vsuxseg7_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76352,16 +9935,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i32:
+define void @test_vsuxseg7_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76369,19 +9953,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i16:
+define void @test_vsuxseg7_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76389,16 +9974,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i16:
+define void @test_vsuxseg7_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76406,19 +9992,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i8:
+define void @test_vsuxseg7_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76426,16 +10013,17 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i8:
+define void @test_vsuxseg7_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76443,19 +10031,20 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv8i32:
+define void @test_vsuxseg8_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76463,16 +10052,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv8i32:
+define void @test_vsuxseg8_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76480,56 +10071,21 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg6_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg6_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i8:
+define void @test_vsuxseg8_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76537,16 +10093,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i8:
+define void @test_vsuxseg8_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76554,19 +10112,21 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv1i16:
+define void @test_vsuxseg8_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -76574,16 +10134,18 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv1i16:
+define void @test_vsuxseg8_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -76591,477 +10153,411 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv32i8:
+define void @test_vsuxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv32i8:
+define void @test_vsuxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i8:
+define void @test_vsuxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i8:
+define void @test_vsuxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv16i32:
+define void @test_vsuxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv16i32:
+define void @test_vsuxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
 ; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i16:
+define void @test_vsuxseg3_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i16:
+define void @test_vsuxseg3_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg6_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv4i32:
+define void @test_vsuxseg3_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg6_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv4i32:
+define void @test_vsuxseg3_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i16:
+define void @test_vsuxseg3_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i16:
+define void @test_vsuxseg3_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i8:
+define void @test_vsuxseg4_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i8:
+define void @test_vsuxseg4_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i8:
+define void @test_vsuxseg4_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i8:
+define void @test_vsuxseg4_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i32:
+define void @test_vsuxseg4_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i32:
+define void @test_vsuxseg4_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i16:
+define void @test_vsuxseg5_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i16:
+define void @test_vsuxseg5_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv32i16:
+define void @test_vsuxseg5_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv32i16:
+define void @test_vsuxseg5_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i32:
+define void @test_vsuxseg5_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
 ; CHECK-NEXT:    vmv1r.v v2, v0
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i32:
+define void @test_vsuxseg5_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
 ; CHECK-NEXT:    vmv1r.v v3, v1
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i16:
+define void @test_vsuxseg6_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77069,17 +10565,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i16:
+define void @test_vsuxseg6_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77087,20 +10582,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i8:
+define void @test_vsuxseg6_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77108,17 +10602,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i8:
+define void @test_vsuxseg6_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77126,20 +10619,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv8i32:
+define void @test_vsuxseg6_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77147,17 +10639,16 @@
 ; CHECK-NEXT:    vmv1r.v v3, v0
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv8i32:
+define void @test_vsuxseg6_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77165,59 +10656,19 @@
 ; CHECK-NEXT:    vmv1r.v v4, v1
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v12, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv64i8:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i8:
+define void @test_vsuxseg7_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77226,16 +10677,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i8:
+define void @test_vsuxseg7_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77244,19 +10695,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv1i16:
+define void @test_vsuxseg7_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77265,16 +10716,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv1i16:
+define void @test_vsuxseg7_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77283,19 +10734,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv32i8:
+define void @test_vsuxseg7_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77304,16 +10755,16 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv32i8:
+define void @test_vsuxseg7_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77322,19 +10773,19 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i8:
+define void @test_vsuxseg8_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77343,16 +10794,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i8:
+define void @test_vsuxseg8_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77361,58 +10813,20 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
-
-define void @test_vsuxseg7_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg7_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i16:
+define void @test_vsuxseg8_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77421,16 +10835,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i16:
+define void @test_vsuxseg8_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77439,19 +10854,20 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
 
-define void @test_vsuxseg7_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv4i32:
+define void @test_vsuxseg8_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vmv1r.v v1, v0
@@ -77460,16 +10876,17 @@
 ; CHECK-NEXT:    vmv1r.v v4, v0
 ; CHECK-NEXT:    vmv1r.v v5, v0
 ; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg7_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv4i32:
+define void @test_vsuxseg8_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv1r.v v1, v8
 ; CHECK-NEXT:    vmv1r.v v2, v1
@@ -77478,2414 +10895,2405 @@
 ; CHECK-NEXT:    vmv1r.v v5, v1
 ; CHECK-NEXT:    vmv1r.v v6, v1
 ; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i16:
+define void @test_vsuxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i16:
+define void @test_vsuxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i8:
+define void @test_vsuxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i8:
+define void @test_vsuxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i8:
+define void @test_vsuxseg2_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i8:
+define void @test_vsuxseg2_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i32:
+define void @test_vsuxseg3_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i32:
+define void @test_vsuxseg3_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i16:
+define void @test_vsuxseg3_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i16:
+define void @test_vsuxseg3_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv32i16:
+define void @test_vsuxseg3_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv32i16:
+define void @test_vsuxseg3_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i32:
+define void @test_vsuxseg4_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i32:
+define void @test_vsuxseg4_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
+
+define void @test_vsuxseg4_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  ret void
+}
+
+define void @test_vsuxseg4_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i16:
+define void @test_vsuxseg4_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i16:
+define void @test_vsuxseg4_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i8:
+define void @test_vsuxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i8:
+define void @test_vsuxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv2r.v v26, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv8i32:
+define void @test_vsuxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv8i32:
+define void @test_vsuxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv1r.v v25, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv64i8:
+define void @test_vsuxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv8f32_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv64i8:
+define void @test_vsuxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
+; CHECK-NEXT:    vmv4r.v v28, v12
+; CHECK-NEXT:    vmv4r.v v12, v8
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v28, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i8:
+define void @test_vsuxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i8:
+define void @test_vsuxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv1i16:
+define void @test_vsuxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv1i16:
+define void @test_vsuxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv32i8:
+define void @test_vsuxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v12
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv32i8:
+define void @test_vsuxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v12, v0.t
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i8:
+define void @test_vsuxseg3_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i8:
+define void @test_vsuxseg3_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv16i32:
+define void @test_vsuxseg3_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv16i32:
+define void @test_vsuxseg3_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15
-; CHECK-NEXT:    vmv1r.v v9, v8
-; CHECK-NEXT:    vmv1r.v v10, v8
-; CHECK-NEXT:    vmv1r.v v11, v8
-; CHECK-NEXT:    vmv1r.v v12, v8
-; CHECK-NEXT:    vmv1r.v v13, v8
-; CHECK-NEXT:    vmv1r.v v14, v8
-; CHECK-NEXT:    vmv1r.v v15, v8
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i16:
+define void @test_vsuxseg3_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i16:
+define void @test_vsuxseg3_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg8_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv4i32:
+define void @test_vsuxseg4_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmv1r.v v1, v0
-; CHECK-NEXT:    vmv1r.v v2, v0
-; CHECK-NEXT:    vmv1r.v v3, v0
-; CHECK-NEXT:    vmv1r.v v4, v0
-; CHECK-NEXT:    vmv1r.v v5, v0
-; CHECK-NEXT:    vmv1r.v v6, v0
-; CHECK-NEXT:    vmv1r.v v7, v0
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg8_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv4i32:
+define void @test_vsuxseg4_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v1, v8
-; CHECK-NEXT:    vmv1r.v v2, v1
-; CHECK-NEXT:    vmv1r.v v3, v1
-; CHECK-NEXT:    vmv1r.v v4, v1
-; CHECK-NEXT:    vmv1r.v v5, v1
-; CHECK-NEXT:    vmv1r.v v6, v1
-; CHECK-NEXT:    vmv1r.v v7, v1
-; CHECK-NEXT:    vmv1r.v v8, v1
-; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
-; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i16:
+define void @test_vsuxseg4_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i16:
+define void @test_vsuxseg4_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i8:
+define void @test_vsuxseg4_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv2r.v v0, v8
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i8:
+define void @test_vsuxseg4_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv2r.v v2, v8
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i8:
+define void @test_vsuxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i8:
+define void @test_vsuxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i32:
+define void @test_vsuxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i32:
+define void @test_vsuxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i16:
+define void @test_vsuxseg2_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i16:
+define void @test_vsuxseg2_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv32i16:
+define void @test_vsuxseg3_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv32i16:
+define void @test_vsuxseg3_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i32:
+define void @test_vsuxseg3_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i32:
+define void @test_vsuxseg3_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i16:
+define void @test_vsuxseg3_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i16:
+define void @test_vsuxseg3_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i8:
+define void @test_vsuxseg4_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i8:
+define void @test_vsuxseg4_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv8i32:
+define void @test_vsuxseg4_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv8i32:
+define void @test_vsuxseg4_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv64i8:
+define void @test_vsuxseg4_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv64i8:
+define void @test_vsuxseg4_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i8:
+define void @test_vsuxseg5_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i8:
+define void @test_vsuxseg5_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv1i16:
+define void @test_vsuxseg5_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv1i16:
+define void @test_vsuxseg5_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv32i8:
+define void @test_vsuxseg5_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv32i8:
+define void @test_vsuxseg5_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i8:
+define void @test_vsuxseg6_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i8:
+define void @test_vsuxseg6_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv16i32:
+define void @test_vsuxseg6_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv16i32:
+define void @test_vsuxseg6_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv2i16:
+define void @test_vsuxseg6_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv2i16:
+define void @test_vsuxseg6_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv1r.v v25, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i32:
+define void @test_vsuxseg7_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i32:
+define void @test_vsuxseg7_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
-; CHECK-NEXT:    vmv2r.v v26, v10
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i16:
+define void @test_vsuxseg7_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i16:
+define void @test_vsuxseg7_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i8:
+define void @test_vsuxseg7_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i8:
+define void @test_vsuxseg7_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i8:
+define void @test_vsuxseg8_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i8:
+define void @test_vsuxseg8_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i32:
+define void @test_vsuxseg8_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i32:
+define void @test_vsuxseg8_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i16:
+define void @test_vsuxseg8_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i16:
+define void @test_vsuxseg8_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv32i16:
+define void @test_vsuxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv32i16:
+define void @test_vsuxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i32:
+define void @test_vsuxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i32:
+define void @test_vsuxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i16:
+define void @test_vsuxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i16:
+define void @test_vsuxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8_v9 def $v8_v9
+; CHECK-NEXT:    vmv1r.v v25, v9
+; CHECK-NEXT:    vmv1r.v v9, v8
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i8:
+define void @test_vsuxseg3_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i8:
+define void @test_vsuxseg3_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv8i32:
+define void @test_vsuxseg3_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv8i32:
+define void @test_vsuxseg3_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv64i8:
+define void @test_vsuxseg3_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv64i8:
+define void @test_vsuxseg3_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg3ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i8:
+define void @test_vsuxseg4_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i8:
+define void @test_vsuxseg4_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv1i16:
+define void @test_vsuxseg4_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv1i16:
+define void @test_vsuxseg4_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv32i8:
+define void @test_vsuxseg4_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv32i8:
+define void @test_vsuxseg4_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg4ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i8:
+define void @test_vsuxseg5_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i8:
+define void @test_vsuxseg5_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv16i32:
+define void @test_vsuxseg5_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv16i32:
+define void @test_vsuxseg5_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv2i16:
+define void @test_vsuxseg5_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv2i16:
+define void @test_vsuxseg5_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg5ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i32)
-declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg3_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
+define void @test_vsuxseg6_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg3_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i32:
+define void @test_vsuxseg6_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i16:
+define void @test_vsuxseg6_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v12
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i16:
+define void @test_vsuxseg6_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i8:
+define void @test_vsuxseg6_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i8:
+define void @test_vsuxseg6_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg6ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i8:
+define void @test_vsuxseg7_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i8:
+define void @test_vsuxseg7_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i32:
+define void @test_vsuxseg7_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i32:
+define void @test_vsuxseg7_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i16:
+define void @test_vsuxseg7_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i16:
+define void @test_vsuxseg7_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg7ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv32i16:
+define void @test_vsuxseg8_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv32i16:
+define void @test_vsuxseg8_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei32.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i32:
+define void @test_vsuxseg8_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i32:
+define void @test_vsuxseg8_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei8.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i32)
+declare void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i16:
+define void @test_vsuxseg8_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v0, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i16:
+define void @test_vsuxseg8_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vmv1r.v v1, v8
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsuxseg8ei16.v v1, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i8:
+define void @test_vsuxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i8:
+define void @test_vsuxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg2ei16.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv8i32:
+define void @test_vsuxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v0, v8
-; CHECK-NEXT:    vmv2r.v v2, v0
-; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv8i32:
+define void @test_vsuxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv2r.v v2, v8
-; CHECK-NEXT:    vmv2r.v v4, v2
-; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv1r.v v25, v10
+; CHECK-NEXT:    vmv2r.v v10, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg2ei8.v v8, (a0), v25, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv64i8:
+define void @test_vsuxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv64i8:
+define void @test_vsuxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
+; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m2_v10m2 def $v8m2_v10m2
+; CHECK-NEXT:    vmv2r.v v26, v10
 ; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg2ei32.v v8, (a0), v26, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i8:
+define void @test_vsuxseg3_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg3ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i8:
+define void @test_vsuxseg3_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg3ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv1i16:
+define void @test_vsuxseg3_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg3ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv1i16:
+define void @test_vsuxseg3_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg3ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i32)
+declare void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv32i8:
+define void @test_vsuxseg3_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
-; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v12
+; CHECK-NEXT:    vsuxseg3ei32.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv32i8:
+define void @test_vsuxseg3_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
-; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v12, v0.t
+; CHECK-NEXT:    vsuxseg3ei32.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i8:
+define void @test_vsuxseg4_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i8:
+define void @test_vsuxseg4_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
-  ret void
-}
-
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i32)
-
-define void @test_vsuxseg4_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16
-; CHECK-NEXT:    ret
-entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i32 %vl)
-  ret void
-}
-
-define void @test_vsuxseg4_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv16i32:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2
-; CHECK-NEXT:    vmv2r.v v10, v8
-; CHECK-NEXT:    vmv2r.v v12, v8
-; CHECK-NEXT:    vmv2r.v v14, v8
-; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei32.v v8, (a0), v16, v0.t
+; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }
 
-declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i32)
-declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i32)
+declare void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i32)
+declare void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
 
-define void @test_vsuxseg4_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv2i16:
+define void @test_vsuxseg4_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v0, v8
 ; CHECK-NEXT:    vmv2r.v v2, v0
 ; CHECK-NEXT:    vmv2r.v v4, v0
 ; CHECK-NEXT:    vmv2r.v v6, v0
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v0, (a0), v10
+; CHECK-NEXT:    vsuxseg4ei8.v v0, (a0), v10
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i32 %vl)
   ret void
 }
 
-define void @test_vsuxseg4_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl) {
-; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv2i16:
+define void @test_vsuxseg4_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl) {
+; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmv2r.v v2, v8
 ; CHECK-NEXT:    vmv2r.v v4, v2
 ; CHECK-NEXT:    vmv2r.v v6, v2
 ; CHECK-NEXT:    vmv2r.v v8, v2
 ; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
-; CHECK-NEXT:    vsuxseg4ei16.v v2, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxseg4ei8.v v2, (a0), v10, v0.t
 ; CHECK-NEXT:    ret
 entry:
-  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl)
+  tail call void @llvm.riscv.vsuxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl)
   ret void
 }