Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -204,6 +204,9 @@ bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); + bool expandUlhu(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + void createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions); @@ -1607,6 +1610,7 @@ case Mips::SWM_MM: case Mips::JalOneReg: case Mips::JalTwoReg: + case Mips::Ulhu: return true; default: return false; @@ -1633,6 +1637,8 @@ case Mips::JalOneReg: case Mips::JalTwoReg: return expandJalWithRegs(Inst, IDLoc, Instructions); + case Mips::Ulhu: + return expandUlhu(Inst, IDLoc, Instructions); } } @@ -2148,6 +2154,83 @@ return false; } +bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + if (hasMips32r6() || hasMips64r6()) { + Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); + return false; + } + + if (!AssemblerOptions.back()->isMacro()) + Warning(IDLoc, "macro instruction expanded into multiple instructions"); + + const MCOperand &DstRegOp = Inst.getOperand(0); + assert(DstRegOp.isReg() && "expected register operand kind"); + + const MCOperand &SrcRegOp = Inst.getOperand(1); + assert(SrcRegOp.isReg() && "expected register operand kind"); + + const MCOperand &OffsetImmOp = Inst.getOperand(2); + assert(OffsetImmOp.isImm() && "expected immediate operand kind"); + + unsigned DstReg = DstRegOp.getReg(); + unsigned SrcReg = SrcRegOp.getReg(); + int64_t OffsetValue = OffsetImmOp.getImm(); + + unsigned ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + // When the value of offset+1 does not fit in 16 bits, we have to load the + // offset in AT, (D)ADDu the original source register (if there was one), and + // then use AT as the source register for the 2 generated LBu's. + bool LoadedOffsetInAT = false; + if (!isInt<16>(OffsetValue + 1)) { + LoadedOffsetInAT = true; + + // NOTE: If there is no source register specified in the ULHU, the parser + // will interpret it as $0. However, in order to tell loadImmediate() not to + // use a source register we need to pass it a Mips::NoRegister. + if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) + SrcReg = Mips::NoRegister; + + if (loadImmediate(OffsetValue, ATReg, SrcReg, !isGP64bit(), IDLoc, + Instructions)) + return true; + } + + MCInst TmpInst; + TmpInst.setOpcode(Mips::LBu); + TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? DstReg : ATReg)); + TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? ATReg : SrcReg)); + TmpInst.addOperand(MCOperand::CreateImm(LoadedOffsetInAT ? 0 : OffsetValue)); + Instructions.push_back(TmpInst); + + TmpInst.clear(); + TmpInst.setOpcode(Mips::LBu); + TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? ATReg : DstReg)); + TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? ATReg : SrcReg)); + TmpInst.addOperand( + MCOperand::CreateImm(LoadedOffsetInAT ? 1 : (OffsetValue + 1))); + Instructions.push_back(TmpInst); + + TmpInst.clear(); + TmpInst.setOpcode(Mips::SLL); + TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? DstReg : ATReg)); + TmpInst.addOperand(MCOperand::CreateReg(LoadedOffsetInAT ? DstReg : ATReg)); + TmpInst.addOperand(MCOperand::CreateImm(8)); + Instructions.push_back(TmpInst); + + TmpInst.clear(); + TmpInst.setOpcode(Mips::OR); + TmpInst.addOperand(MCOperand::CreateReg(DstReg)); + TmpInst.addOperand(MCOperand::CreateReg(DstReg)); + TmpInst.addOperand(MCOperand::CreateReg(ATReg)); + Instructions.push_back(TmpInst); + + return false; +} + void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions) { MCInst NopInst; @@ -2168,7 +2251,7 @@ unsigned TrgReg, SmallVectorImpl &Instructions) { MCInst AdduInst; - AdduInst.setOpcode(Mips::ADDu); + AdduInst.setOpcode(isGP64bit() ? Mips::DADDu : Mips::ADDu); AdduInst.addOperand(MCOperand::CreateReg(DstReg)); AdduInst.addOperand(MCOperand::CreateReg(SrcReg)); AdduInst.addOperand(MCOperand::CreateReg(TrgReg)); Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1671,6 +1671,9 @@ def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs), "jal\t$rs"> ; +def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), + "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6; + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// Index: test/MC/Mips/mips-expansions-bad.s =================================================================== --- test/MC/Mips/mips-expansions-bad.s +++ test/MC/Mips/mips-expansions-bad.s @@ -15,3 +15,16 @@ # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate dli $5, 1 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture + + .set mips32r6 + ulhu $5, 0 + # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + .set mips32 + ulhu $5, 1 + # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + .set mips64r6 + ulhu $5, 2 + # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 Index: test/MC/Mips/mips-expansions.s =================================================================== --- test/MC/Mips/mips-expansions.s +++ test/MC/Mips/mips-expansions.s @@ -68,6 +68,66 @@ # CHECK: lui $1, %hi(symbol) # CHECK: sdc1 $f0, %lo(symbol)($1) +# CHECK: lbu $1, 0($zero) # encoding: [0x00,0x00,0x01,0x90] +# CHECK: lbu $8, 1($zero) # encoding: [0x01,0x00,0x08,0x90] +# CHECK: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: lbu $1, 2($zero) # encoding: [0x02,0x00,0x01,0x90] +# CHECK: lbu $8, 3($zero) # encoding: [0x03,0x00,0x08,0x90] +# CHECK: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: lbu $1, -32768($zero) # encoding: [0x00,0x80,0x01,0x90] +# CHECK: lbu $8, -32767($zero) # encoding: [0x01,0x80,0x08,0x90] +# CHECK: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + +# CHECK: lbu $1, 0($9) # encoding: [0x00,0x00,0x21,0x91] +# CHECK: lbu $8, 1($9) # encoding: [0x01,0x00,0x28,0x91] +# CHECK: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: lbu $1, 2($9) # encoding: [0x02,0x00,0x21,0x91] +# CHECK: lbu $8, 3($9) # encoding: [0x03,0x00,0x28,0x91] +# CHECK: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: ori $1, $9, 32768 # encoding: [0x00,0x80,0x21,0x35] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: lbu $1, -32768($9) # encoding: [0x00,0x80,0x21,0x91] +# CHECK: lbu $8, -32767($9) # encoding: [0x01,0x80,0x28,0x91] +# CHECK: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34] +# CHECK: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + li $5,123 li $6,-2345 li $7,65538 @@ -96,3 +156,17 @@ ldc1 $f0, symbol sdc1 $f0, symbol + + ulhu $8, 0 + ulhu $8, 2 + ulhu $8, 0x8000 + ulhu $8, -0x8000 + ulhu $8, 0x10000 + ulhu $8, 0x18888 + + ulhu $8, 0($9) + ulhu $8, 2($9) + ulhu $8, 0x8000($9) + ulhu $8, -0x8000($9) + ulhu $8, 0x10000($9) + ulhu $8, 0x18888($9) Index: test/MC/Mips/mips64-expansions.s =================================================================== --- test/MC/Mips/mips64-expansions.s +++ test/MC/Mips/mips64-expansions.s @@ -178,3 +178,103 @@ # CHECK: ori $8, $8, 65534 # encoding: [0xfe,0xff,0x08,0x35] # CHECK: dsll $8, $8, 16 # encoding: [0x38,0x44,0x08,0x00] # CHECK: ori $8, $8, 65535 # encoding: [0xff,0xff,0x08,0x35] + +# Test ulhu with 64-bit immediate addresses. + + ulhu $8, 0x100010001 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x1000100010001 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x100010001 +# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x1000100010001 +# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + +# Test ulhu with source register and 64-bit immediate offset. + + ulhu $8, 0x100010001($9) +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, 0x1000100010001($9) +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x100010001($9) +# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + + ulhu $8, -0x1000100010001($9) +# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lbu $8, 0($1) # encoding: [0x00,0x00,0x28,0x90] +# CHECK: lbu $1, 1($1) # encoding: [0x01,0x00,0x21,0x90] +# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] +# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]