Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -215,8 +215,8 @@ bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); - bool expandUlhu(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions); + bool expandUnalignedLoads(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); void createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions); @@ -1649,6 +1649,7 @@ case Mips::BGEU: case Mips::BGTU: case Mips::Ulhu: + case Mips::Ulw: return true; default: return false; @@ -1688,7 +1689,8 @@ case Mips::BGTU: return expandCondBranches(Inst, IDLoc, Instructions); case Mips::Ulhu: - return expandUlhu(Inst, IDLoc, Instructions); + case Mips::Ulw: + return expandUnalignedLoads(Inst, IDLoc, Instructions); } } @@ -2465,14 +2467,18 @@ return false; } -bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +bool MipsAsmParser::expandUnalignedLoads( + MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions) { if (hasMips32r6() || hasMips64r6()) { Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); return false; } - warnIfNoMacro(IDLoc); + unsigned OriginalOpcode = Inst.getOpcode(); + + // ULHU should always trigger a warning if .set nomacro has been used. + if (OriginalOpcode == Mips::Ulhu) + warnIfNoMacro(IDLoc); const MCOperand &DstRegOp = Inst.getOperand(0); assert(DstRegOp.isReg() && "expected register operand kind"); @@ -2487,19 +2493,39 @@ unsigned SrcReg = SrcRegOp.getReg(); int64_t OffsetValue = OffsetImmOp.getImm(); + unsigned OffsetDiff = 0; + if (OriginalOpcode == Mips::Ulhu) + OffsetDiff = 1; + if (OriginalOpcode == Mips::Ulw) + OffsetDiff = 3; + + unsigned ATReg = 0; // NOTE: We always need AT for ULHU, as it is always used as the source // register for one of the LBu's. - unsigned ATReg = getATReg(IDLoc); - if (!ATReg) - return true; + if (OriginalOpcode == Mips::Ulhu) { + ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + } // When the value of offset+1 does not fit in 16 bits, we have to load the // offset in AT, (D)ADDu the original source register (if there was one), and // then use AT as the source register for the 2 generated LBu's. bool LoadedOffsetInAT = false; - if (!isInt<16>(OffsetValue + 1) || !isInt<16>(OffsetValue)) { + if (!isInt<16>(OffsetValue + OffsetDiff) || !isInt<16>(OffsetValue)) { + // For ULHU, we already have AT, so don't try to get it again. + if (OriginalOpcode == Mips::Ulw) { + ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + } LoadedOffsetInAT = true; + // ULHU would have already triggered the .set nomacro warning by now. + // ULW can only trigger it at this point. + if (OriginalOpcode == Mips::Ulw) + warnIfNoMacro(IDLoc); + if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(), IDLoc, Instructions)) return true; @@ -2514,48 +2540,67 @@ createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Instructions); } - unsigned FirstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg; - unsigned SecondLbuDstReg = LoadedOffsetInAT ? ATReg : DstReg; - unsigned LbuSrcReg = LoadedOffsetInAT ? ATReg : SrcReg; - - int64_t FirstLbuOffset = 0, SecondLbuOffset = 0; + int64_t FirstOffset = 0, SecondOffset = 0; if (isLittle()) { - FirstLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1); - SecondLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue; + FirstOffset = LoadedOffsetInAT ? OffsetDiff : (OffsetValue + OffsetDiff); + SecondOffset = LoadedOffsetInAT ? 0 : OffsetValue; } else { - FirstLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue; - SecondLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1); - } - - unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg; - - MCInst TmpInst; - TmpInst.setOpcode(Mips::LBu); - TmpInst.addOperand(MCOperand::createReg(FirstLbuDstReg)); - TmpInst.addOperand(MCOperand::createReg(LbuSrcReg)); - TmpInst.addOperand(MCOperand::createImm(FirstLbuOffset)); - Instructions.push_back(TmpInst); - - TmpInst.clear(); - TmpInst.setOpcode(Mips::LBu); - TmpInst.addOperand(MCOperand::createReg(SecondLbuDstReg)); - TmpInst.addOperand(MCOperand::createReg(LbuSrcReg)); - TmpInst.addOperand(MCOperand::createImm(SecondLbuOffset)); - Instructions.push_back(TmpInst); - - TmpInst.clear(); - TmpInst.setOpcode(Mips::SLL); - TmpInst.addOperand(MCOperand::createReg(SllReg)); - TmpInst.addOperand(MCOperand::createReg(SllReg)); - TmpInst.addOperand(MCOperand::createImm(8)); - Instructions.push_back(TmpInst); - - TmpInst.clear(); - TmpInst.setOpcode(Mips::OR); - TmpInst.addOperand(MCOperand::createReg(DstReg)); - TmpInst.addOperand(MCOperand::createReg(DstReg)); - TmpInst.addOperand(MCOperand::createReg(ATReg)); - Instructions.push_back(TmpInst); + FirstOffset = LoadedOffsetInAT ? 0 : OffsetValue; + SecondOffset = LoadedOffsetInAT ? OffsetDiff : (OffsetValue + OffsetDiff); + } + + if (OriginalOpcode == Mips::Ulw) { + unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg; + MCInst LeftLoadInst; + LeftLoadInst.setOpcode(Mips::LWL); + LeftLoadInst.addOperand(DstRegOp); + LeftLoadInst.addOperand(MCOperand::createReg(FinalSrcReg)); + LeftLoadInst.addOperand(MCOperand::createImm(FirstOffset)); + Instructions.push_back(LeftLoadInst); + + MCInst RightLoadInst; + RightLoadInst.setOpcode(Mips::LWR); + RightLoadInst.addOperand(DstRegOp); + RightLoadInst.addOperand(MCOperand::createReg(FinalSrcReg)); + RightLoadInst.addOperand(MCOperand::createImm(SecondOffset)); + Instructions.push_back(RightLoadInst); + } + + if (OriginalOpcode == Mips::Ulhu) { + unsigned FirstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg; + unsigned SecondLbuDstReg = LoadedOffsetInAT ? ATReg : DstReg; + unsigned LbuSrcReg = LoadedOffsetInAT ? ATReg : SrcReg; + + unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg; + + MCInst TmpInst; + TmpInst.setOpcode(Mips::LBu); + TmpInst.addOperand(MCOperand::createReg(FirstLbuDstReg)); + TmpInst.addOperand(MCOperand::createReg(LbuSrcReg)); + TmpInst.addOperand(MCOperand::createImm(FirstOffset)); + Instructions.push_back(TmpInst); + + TmpInst.clear(); + TmpInst.setOpcode(Mips::LBu); + TmpInst.addOperand(MCOperand::createReg(SecondLbuDstReg)); + TmpInst.addOperand(MCOperand::createReg(LbuSrcReg)); + TmpInst.addOperand(MCOperand::createImm(SecondOffset)); + Instructions.push_back(TmpInst); + + TmpInst.clear(); + TmpInst.setOpcode(Mips::SLL); + TmpInst.addOperand(MCOperand::createReg(SllReg)); + TmpInst.addOperand(MCOperand::createReg(SllReg)); + TmpInst.addOperand(MCOperand::createImm(8)); + Instructions.push_back(TmpInst); + + TmpInst.clear(); + TmpInst.setOpcode(Mips::OR); + TmpInst.addOperand(MCOperand::createReg(DstReg)); + TmpInst.addOperand(MCOperand::createReg(DstReg)); + TmpInst.addOperand(MCOperand::createReg(ATReg)); + Instructions.push_back(TmpInst); + } return false; } Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1710,6 +1710,9 @@ def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6; +def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), + "ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6; + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// Index: test/MC/Mips/mips-expansions-bad.s =================================================================== --- test/MC/Mips/mips-expansions-bad.s +++ test/MC/Mips/mips-expansions-bad.s @@ -36,3 +36,16 @@ ulhu $5, 2 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + + .set mips32r6 + ulw $5, 0 + # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + .set mips32 + ulw $5, 1 + # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 + .set mips64r6 + ulw $5, 2 + # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 + # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 Index: test/MC/Mips/mips-expansions.s =================================================================== --- test/MC/Mips/mips-expansions.s +++ test/MC/Mips/mips-expansions.s @@ -370,5 +370,141 @@ # CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] # CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] +# Test ULW with immediate operand. + ulw $8, 0 +# CHECK-BE: lwl $8, 0($zero) # encoding: [0x88,0x08,0x00,0x00] +# CHECK-BE: lwr $8, 3($zero) # encoding: [0x98,0x08,0x00,0x03] +# CHECK-LE: lwl $8, 3($zero) # encoding: [0x03,0x00,0x08,0x88] +# CHECK-LE: lwr $8, 0($zero) # encoding: [0x00,0x00,0x08,0x98] + + ulw $8, 2 +# CHECK-BE: lwl $8, 2($zero) # encoding: [0x88,0x08,0x00,0x02] +# CHECK-BE: lwr $8, 5($zero) # encoding: [0x98,0x08,0x00,0x05] +# CHECK-LE: lwl $8, 5($zero) # encoding: [0x05,0x00,0x08,0x88] +# CHECK-LE: lwr $8, 2($zero) # encoding: [0x02,0x00,0x08,0x98] + + ulw $8, 0x8000 +# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x8000 +# CHECK-BE: lwl $8, -32768($zero) # encoding: [0x88,0x08,0x80,0x00] +# CHECK-BE: lwr $8, -32765($zero) # encoding: [0x98,0x08,0x80,0x03] +# CHECK-LE: lwl $8, -32765($zero) # encoding: [0x03,0x80,0x08,0x88] +# CHECK-LE: lwr $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x98] + + ulw $8, 0x10000 +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 0x18888 +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -32771 +# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff] +# CHECK-BE: ori $1, $1, 32765 # encoding: [0x34,0x21,0x7f,0xfd] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK-LE: ori $1, $1, 32765 # encoding: [0xfd,0x7f,0x21,0x34] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 32765 +# CHECK-BE: ori $1, $zero, 32765 # encoding: [0x34,0x01,0x7f,0xfd] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: ori $1, $zero, 32765 # encoding: [0xfd,0x7f,0x01,0x34] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + +# Test ULW with immediate offset and a source register operand. + ulw $8, 0($9) +# CHECK-BE: lwl $8, 0($9) # encoding: [0x89,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($9) # encoding: [0x99,0x28,0x00,0x03] +# CHECK-LE: lwl $8, 3($9) # encoding: [0x03,0x00,0x28,0x89] +# CHECK-LE: lwr $8, 0($9) # encoding: [0x00,0x00,0x28,0x99] + + ulw $8, 2($9) +# CHECK-BE: lwl $8, 2($9) # encoding: [0x89,0x28,0x00,0x02] +# CHECK-BE: lwr $8, 5($9) # encoding: [0x99,0x28,0x00,0x05] +# CHECK-LE: lwl $8, 5($9) # encoding: [0x05,0x00,0x28,0x89] +# CHECK-LE: lwr $8, 2($9) # encoding: [0x02,0x00,0x28,0x99] + + ulw $8, 0x8000($9) +# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x8000($9) +# CHECK-BE: lwl $8, -32768($9) # encoding: [0x89,0x28,0x80,0x00] +# CHECK-BE: lwr $8, -32765($9) # encoding: [0x99,0x28,0x80,0x03] +# CHECK-LE: lwl $8, -32765($9) # encoding: [0x03,0x80,0x28,0x89] +# CHECK-LE: lwr $8, -32768($9) # encoding: [0x00,0x80,0x28,0x99] + + ulw $8, 0x10000($9) +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 0x18888($9) +# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -32771($9) +# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff] +# CHECK-BE: ori $1, $1, 32765 # encoding: [0x34,0x21,0x7f,0xfd] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK-LE: ori $1, $1, 32765 # encoding: [0xfd,0x7f,0x21,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 32765($9) +# CHECK-BE: ori $1, $zero, 32765 # encoding: [0x34,0x01,0x7f,0xfd] +# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21] +# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00] +# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03] +# CHECK-LE: ori $1, $zero, 32765 # encoding: [0xfd,0x7f,0x01,0x34] +# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] +# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + 1: add $4, $4, $4 Index: test/MC/Mips/mips64-expansions.s =================================================================== --- test/MC/Mips/mips64-expansions.s +++ test/MC/Mips/mips64-expansions.s @@ -369,3 +369,85 @@ # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90] # CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00] # CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01] + +# Test ulw with 64-bit immediate addresses. + ulw $8, 0x100010001 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 0x1000100010001 +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x100010001 +# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x1000100010001 +# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + +# Test ulw with source register and 64-bit immediate offset. + ulw $8, 0x100010001($9) +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, 0x1000100010001($9) +# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x100010001($9) +# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] + + ulw $8, -0x1000100010001($9) +# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34] +# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34] +# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00] +# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88] +# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98] Index: test/MC/Mips/set-nomacro.s =================================================================== --- test/MC/Mips/set-nomacro.s +++ test/MC/Mips/set-nomacro.s @@ -62,6 +62,11 @@ ulhu $5, 0 + ulw $8, 2 + ulw $8, 0x8000 + ulw $8, 2($9) + ulw $8, 0x8000($9) + add $4, $5, $6 .set noreorder @@ -173,5 +178,14 @@ ulhu $5, 0 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ulw $8, 2 +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ulw $8, 0x8000 +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ulw $8, 2($9) +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ulw $8, 0x8000($9) +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + add $4, $5, $6 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions