diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -8995,7 +8995,7 @@ void VPInterleaveRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "\"INTERLEAVE-GROUP with factor " << IG->getFactor() << " at "; + O << Indent << "INTERLEAVE-GROUP with factor " << IG->getFactor() << " at "; IG->getInsertPos()->printAsOperand(O, false); O << ", "; getAddr()->printAsOperand(O, SlotTracker); @@ -9006,7 +9006,7 @@ } for (unsigned i = 0; i < IG->getFactor(); ++i) if (Instruction *I = IG->getMember(i)) - O << "\\l\" +\n" << Indent << "\" " << VPlanIngredient(I) << " " << i; + O << "\n" << Indent << " " << VPlanIngredient(I) << " " << i; } void VPWidenCallRecipe::execute(VPTransformState &State) { diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -635,12 +635,6 @@ OS << getName(); } - void print(raw_ostream &OS) const { - // TODO: Only printing VPBB name for now since we only have dot printing - // support for VPInstructions/Recipes. - printAsOperand(OS, false); - } - /// Return true if it is legal to hoist instructions into this block. bool isLegalToHoistInto() { // There are currently no constraints that prevent an instruction to be @@ -651,6 +645,14 @@ /// Replace all operands of VPUsers in the block with \p NewValue and also /// replaces all uses of VPValues defined in the block with NewValue. virtual void dropAllReferences(VPValue *NewValue) = 0; + + virtual void print(raw_ostream &O, const Twine &Indent, + VPSlotTracker &SlotTracker) const = 0; + void print(raw_ostream &O) const { + VPSlotTracker SlotTracker(getPlan()); + print(O, "", SlotTracker); + } + void dump() const { print(dbgs()); } }; /// VPRecipeBase is a base class modeling a sequence of one or more output IR @@ -1283,12 +1285,11 @@ /// Print the recipe. void print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const override { - O << " +\n" << Indent << "\"BRANCH-ON-MASK "; + O << Indent << "BRANCH-ON-MASK "; if (VPValue *Mask = getMask()) Mask->printAsOperand(O, SlotTracker); else O << " All-One"; - O << "\\l\""; } /// Return the mask used by this recipe. Note that a full mask is represented @@ -1501,6 +1502,10 @@ void dropAllReferences(VPValue *NewValue) override; + void print(raw_ostream &O, const Twine &Indent, + VPSlotTracker &SlotTracker) const override; + using VPBlockBase::print; // Get the print(raw_stream &O) version. + private: /// Create an IR BasicBlock to hold the output instructions generated by this /// VPBasicBlock, and return it. Update the CFGState accordingly. @@ -1592,6 +1597,10 @@ void execute(struct VPTransformState *State) override; void dropAllReferences(VPValue *NewValue) override; + + void print(raw_ostream &O, const Twine &Indent, + VPSlotTracker &SlotTracker) const override; + using VPBlockBase::print; // Get the print(raw_stream &O) version. }; //===----------------------------------------------------------------------===// @@ -1844,6 +1853,8 @@ VPLoopInfo &getVPLoopInfo() { return VPLInfo; } const VPLoopInfo &getVPLoopInfo() const { return VPLInfo; } + void print(raw_ostream &O) const; + /// Dump the plan to stderr (for debugging). void dump() const; diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp --- a/llvm/lib/Transforms/Vectorize/VPlan.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp @@ -48,6 +48,13 @@ using namespace llvm; extern cl::opt EnableVPlanNativePath; +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +cl::opt + PrintExecutedVPlan("print-executed-vplan", cl::init(false), cl::Hidden, + cl::desc("Dump the VPlan that is being executed to " + "stdout. For LIT testing purposes.")); +#endif + #define DEBUG_TYPE "vplan" raw_ostream &llvm::operator<<(raw_ostream &OS, const VPValue &V) { @@ -364,6 +371,38 @@ } } + +void VPBasicBlock::print(raw_ostream &O, const Twine &Indent, + VPSlotTracker &SlotTracker) const { + O << Indent << getName() << ":\n"; + if (const VPValue *Pred = getPredicate()) { + O << Indent << "BlockPredicate:"; + Pred->printAsOperand(O, SlotTracker); + if (auto *PredInst = dyn_cast(Pred)) + O << " (" << PredInst->getParent()->getName() << ")"; + O << '\n'; + } + + auto RecipeIndent = Indent + " "; + for (const VPRecipeBase &Recipe : *this) { + Recipe.print(O, RecipeIndent, SlotTracker); + O << '\n'; + } + + O << Indent << "Successor(s):"; + for (auto *Succ : getSuccessors()) + O << Indent << " " << Succ->getName(); + O << '\n'; + + if (const VPValue *CBV = getCondBit()) { + O << Indent << "CondBit: "; + CBV->printAsOperand(O, SlotTracker); + if (auto *CBI = dyn_cast(CBV)) + O << " (" << CBI->getParent()->getName() << ")"; + O << '\n'; + } +} + void VPRegionBlock::dropAllReferences(VPValue *NewValue) { for (VPBlockBase *Block : depth_first(Entry)) // Drop all references in VPBasicBlocks and replace all uses with @@ -420,6 +459,17 @@ State->Instance.reset(); } +void VPRegionBlock::print(raw_ostream &O, const Twine &Indent, + VPSlotTracker &SlotTracker) const { + O << Indent << (isReplicator() ? " " : " ") << getName() << ": {"; + auto NewIndent = Indent + " "; + for (auto *BlockBase : depth_first(Entry)) { + O << '\n'; + BlockBase->print(O, NewIndent, SlotTracker); + } + O << Indent << "}\n"; +} + void VPRecipeBase::insertBefore(VPRecipeBase *InsertPos) { assert(!Parent && "Recipe already in some VPBasicBlock"); assert(InsertPos->getParent() && @@ -526,7 +576,7 @@ void VPInstruction::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "EMIT "; + O << Indent << "EMIT "; if (hasResult()) { printAsOperand(O, SlotTracker); @@ -564,6 +614,14 @@ /// LoopVectorBody basic-block was created for this. Introduce additional /// basic-blocks as needed, and fill them all. void VPlan::execute(VPTransformState *State) { +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + if (PrintExecutedVPlan) { + print(outs()); + outs().flush(); + } + LLVM_DEBUG(dbgs() << "VPlan being executed:\n"; dump()); +#endif + // -1. Check if the backedge taken count is needed, and if so build it. if (BackedgeTakenCount && BackedgeTakenCount->getNumUsers()) { Value *TC = State->TripCount; @@ -650,7 +708,21 @@ #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD -void VPlan::dump() const { dbgs() << *this << '\n'; } +void VPlan::print(raw_ostream &O) const { + VPSlotTracker SlotTracker(this); + + O << "VPlan {"; + for (const VPBlockBase *Block : depth_first(getEntry())) { + O << '\n'; + Block->print(O, "", SlotTracker); + } + O << "}\n"; +} + +LLVM_DUMP_METHOD +void VPlan::dump() const { + print(dbgs()); +} #endif void VPlan::updateDominatorTree(DominatorTree *DT, BasicBlock *LoopPreHeaderBB, @@ -771,42 +843,25 @@ void VPlanPrinter::dumpBasicBlock(const VPBasicBlock *BasicBlock) { OS << Indent << getUID(BasicBlock) << " [label =\n"; bumpIndent(1); - OS << Indent << "\"" << DOT::EscapeString(BasicBlock->getName()) << ":\\n\""; - bumpIndent(1); + std::string Str; + raw_string_ostream SS(Str); + // Use no indentation as we need to wrap the lines into quotes ourselves. + BasicBlock->print(SS, "", SlotTracker); + SmallVector Lines; + StringRef(Str).rtrim('\n').split(Lines, "\n"); + + auto EmitLine = [&](StringRef Line, StringRef Suffix) { + OS << Indent << '"' << DOT::EscapeString(Line.str()) << "\\l\"" << Suffix; + }; + + // Don't need the "+" after the last line as well. + for (auto Line : make_range(Lines.begin(), Lines.end() - 1)) + EmitLine(Line, " +\n"); + EmitLine(Lines.back(), "\n"); - // Dump the block predicate. - const VPValue *Pred = BasicBlock->getPredicate(); - if (Pred) { - OS << " +\n" << Indent << " \"BlockPredicate: \""; - if (const VPInstruction *PredI = dyn_cast(Pred)) { - PredI->printAsOperand(OS, SlotTracker); - OS << " (" << DOT::EscapeString(PredI->getParent()->getName()) - << ")\\l\""; - } else - Pred->printAsOperand(OS, SlotTracker); - } - - for (const VPRecipeBase &Recipe : *BasicBlock) { - OS << " +\n" << Indent << "\""; - Recipe.print(OS, Indent, SlotTracker); - OS << "\\l\""; - } - - // Dump the condition bit. - const VPValue *CBV = BasicBlock->getCondBit(); - if (CBV) { - OS << " +\n" << Indent << " \"CondBit: "; - if (const VPInstruction *CBI = dyn_cast(CBV)) { - CBI->printAsOperand(OS, SlotTracker); - OS << " (" << DOT::EscapeString(CBI->getParent()->getName()) << ")\\l\""; - } else { - CBV->printAsOperand(OS, SlotTracker); - OS << "\""; - } - } + bumpIndent(-1); + OS << Indent << "]\n"; - bumpIndent(-2); - OS << "\n" << Indent << "]\n"; dumpEdges(BasicBlock); } @@ -849,7 +904,7 @@ void VPWidenCallRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "WIDEN-CALL "; + O << Indent << "WIDEN-CALL "; auto *CI = cast(getUnderlyingInstr()); if (CI->getType()->isVoidTy()) @@ -866,7 +921,7 @@ void VPWidenSelectRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "WIDEN-SELECT "; + O << Indent << "WIDEN-SELECT "; printAsOperand(O, SlotTracker); O << " = select "; getOperand(0)->printAsOperand(O, SlotTracker); @@ -879,7 +934,7 @@ void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "WIDEN "; + O << Indent << "WIDEN "; printAsOperand(O, SlotTracker); O << " = " << getUnderlyingInstr()->getOpcodeName() << " "; printOperands(O, SlotTracker); @@ -887,7 +942,7 @@ void VPWidenIntOrFpInductionRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "WIDEN-INDUCTION"; + O << Indent << "WIDEN-INDUCTION"; if (getTruncInst()) { O << "\\l\""; O << " +\n" << Indent << "\" " << VPlanIngredient(IV) << "\\l\""; @@ -899,7 +954,7 @@ void VPWidenGEPRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "WIDEN-GEP "; + O << Indent << "WIDEN-GEP "; O << (IsPtrLoopInvariant ? "Inv" : "Var"); size_t IndicesNumber = IsIndexLoopInvariant.size(); for (size_t I = 0; I < IndicesNumber; ++I) @@ -913,12 +968,12 @@ void VPWidenPHIRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "WIDEN-PHI " << VPlanIngredient(Phi); + O << Indent << "WIDEN-PHI " << VPlanIngredient(Phi); } void VPBlendRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "BLEND "; + O << Indent << "BLEND "; Phi->printAsOperand(O, false); O << " ="; if (getNumIncomingValues() == 1) { @@ -938,7 +993,7 @@ void VPReductionRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "REDUCE "; + O << Indent << "REDUCE "; printAsOperand(O, SlotTracker); O << " = "; getChainOp()->printAsOperand(O, SlotTracker); @@ -954,7 +1009,7 @@ void VPReplicateRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << (IsUniform ? "CLONE " : "REPLICATE "); + O << Indent << (IsUniform ? "CLONE " : "REPLICATE "); if (!getUnderlyingInstr()->getType()->isVoidTy()) { printAsOperand(O, SlotTracker); @@ -969,13 +1024,13 @@ void VPPredInstPHIRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "PHI-PREDICATED-INSTRUCTION "; + O << Indent << "PHI-PREDICATED-INSTRUCTION "; printOperands(O, SlotTracker); } void VPWidenMemoryInstructionRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "WIDEN "; + O << Indent << "WIDEN "; if (!isStore()) { getVPValue()->printAsOperand(O, SlotTracker); @@ -1013,7 +1068,7 @@ void VPWidenCanonicalIVRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "EMIT "; + O << Indent << "EMIT "; getVPValue()->printAsOperand(O, SlotTracker); O << " = WIDEN-CANONICAL-INDUCTION"; } diff --git a/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll b/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll --- a/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll +++ b/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts -; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -instcombine -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 -enable-new-pm=0 | FileCheck %s -; RUN: opt < %s -passes=loop-vectorize,instcombine -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s +; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -instcombine -print-executed-vplan -disable-output -print-after=instcombine -enable-new-pm=0 2>&1 | FileCheck %s +; RUN: opt < %s -passes=loop-vectorize,instcombine -force-vector-width=4 -force-vector-interleave=1 -print-executed-vplan -disable-output -print-after=instcombine 2>&1 | FileCheck %s target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" @@ -9,7 +9,6 @@ ; PR30627. Check that a compare instruction with more than one use is not ; recognized as uniform and is vectorized. ; -; CHECK-NOT: Found uniform instruction: %cond = icmp slt i64 %i.next, %n ; CHECK: vector.body ; CHECK: %[[I:.+]] = add nuw nsw <4 x i64> %vec.ind, ; CHECK: icmp slt <4 x i64> %[[I]], %broadcast.splat @@ -36,12 +35,13 @@ } ; Check for crash exposed by D76992. -; CHECK: N0 [label = -; CHECK-NEXT: "loop:\n" + -; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi 0, %iv.next\l" + -; CHECK-NEXT: "WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>\l" + -; CHECK-NEXT: "WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>\l" -; CHECK-NEXT: ] +; CHECK: VPlan { +; CHECK-NEXT: loop: +; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %bc.resume.val, %iv.next +; CHECK-NEXT: WIDEN ir<%cond0> = icmp ir<%iv>, ir<13> +; CHECK-NEXT: WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20> +; CHECK-NEXT: Successor(s): +; CHECK-NEXT: } define void @test() { entry: br label %loop diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll --- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll @@ -1,22 +1,23 @@ ; REQUIRES: asserts -; RUN: opt -loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s +; RUN: opt -loop-vectorize -print-executed-vplan -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" ; Tests for printing VPlans. define void @print_call_and_memory(i64 %n, float* noalias %y, float* noalias %x) nounwind uwtable { -; CHECK: N0 [label = -; CHECK-NEXT: "for.body:\n" + -; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" + -; CHECK-NEXT: "CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" + -; CHECK-NEXT: "WIDEN ir<%lv> = load ir<%arrayidx>\l" + -; CHECK-NEXT: "WIDEN-CALL ir<%call> = call @llvm.sqrt.f32(ir<%lv>)\l" + -; CHECK-NEXT: "CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>\l" + -; CHECK-NEXT: "WIDEN store ir<%arrayidx2>, ir<%call>\l" -; CHECK-NEXT: ] - +; CHECK: VPlan { +; CHECK-NEXT: for.body: +; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, %bc.resume.val +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv> +; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx> +; CHECK-NEXT: WIDEN-CALL ir<%call> = call @llvm.sqrt.f32(ir<%lv>) +; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv> +; CHECK-NEXT: WIDEN store ir<%arrayidx2>, ir<%call> +; CHECK-NEXT: Successor(s): +; CHECK-NEXT: } +; entry: %cmp6 = icmp sgt i64 %n, 0 br i1 %cmp6, label %for.body, label %for.end @@ -37,18 +38,19 @@ } define void @print_widen_gep_and_select(i64 %n, float* noalias %y, float* noalias %x, float* %z) nounwind uwtable { -; CHECK: N0 [label = -; CHECK-NEXT: "for.body:\n" + -; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" + -; CHECK-NEXT: "WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" + -; CHECK-NEXT: "WIDEN ir<%lv> = load ir<%arrayidx>\l" + -; CHECK-NEXT: "WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z>\l" + -; CHECK-NEXT: "WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01>\l" + -; CHECK-NEXT: "WIDEN ir<%add> = fadd ir<%lv>, ir<%sel>\l" + -; CHECK-NEXT: "CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv>\l" + -; CHECK-NEXT: "WIDEN store ir<%arrayidx2>, ir<%add>\l" -; CHECK-NEXT: ] - +; CHECK: VPlan { +; CHECK-NEXT: for.body: +; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, %bc.resume.val +; CHECK-NEXT: WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr ir<%y>, ir<%iv> +; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z> +; CHECK-NEXT: WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01> +; CHECK-NEXT: WIDEN ir<%add> = fadd ir<%lv>, ir<%sel> +; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv> +; CHECK-NEXT: WIDEN store ir<%arrayidx2>, ir<%add> +; CHECK-NEXT: Successor(s): +; CHECK-NEXT: } +; entry: %cmp6 = icmp sgt i64 %n, 0 br i1 %cmp6, label %for.body, label %for.end @@ -71,15 +73,16 @@ } define float @print_reduction(i64 %n, float* noalias %y) { -; CHECK: N0 [label = -; CHECK-NEXT: "for.body:\n" + -; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" + -; CHECK-NEXT: "WIDEN-PHI %red = phi %red.next, 0.000000e+00\l" + -; CHECK-NEXT: "CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" + -; CHECK-NEXT: "WIDEN ir<%lv> = load ir<%arrayidx>\l" + -; CHECK-NEXT: "REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>)\l" -; CHECK-NEXT: ] - +; CHECK: VPlan { +; CHECK-NEXT: for.body: +; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, %bc.resume.val +; CHECK-NEXT: WIDEN-PHI %red = phi %red.next, 0.000000e+00 +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv> +; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx> +; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>) +; CHECK-NEXT: Successor(s): +; CHECK-NEXT: } +; entry: br label %for.body @@ -98,36 +101,40 @@ } define void @print_replicate_predicated_phi(i64 %n, i64* %x) { -; CHECK: N0 [label = -; CHECK-NEXT: "for.body:\n" + -; CHECK-NEXT: "WIDEN-INDUCTION %i = phi 0, %i.next\l" + -; CHECK-NEXT: "WIDEN ir<%cmp> = icmp ir<%i>, ir<5>\l" -; CHECK-NEXT: ] -; -; CHECK: N2 [label = -; CHECK-NEXT: "pred.udiv.entry:\n" + -; CHECK-NEXT: + -; CHECK-NEXT: "BRANCH-ON-MASK ir<%cmp>\l"\l -; CHECK-NEXT: "CondBit: ir<%cmp>" -; CHECK-NEXT: ] -; -; CHECK: N4 [label = -; CHECK-NEXT: "pred.udiv.if:\n" + -; CHECK-NEXT: "REPLICATE ir<%tmp4> = udiv ir<%n>, ir<%i> (S->V)\l" -; CHECK-NEXT: ] -; -; CHECK: N5 [label = -; CHECK-NEXT: "pred.udiv.continue:\n" + -; CHECK-NEXT: "PHI-PREDICATED-INSTRUCTION ir<%tmp4>\l" -; CHECK-NEXT: ] -; -; CHECK: N7 [label = -; CHECK-NEXT: "for.inc:\n" + -; CHECK-NEXT: "EMIT vp<%4> = not ir<%cmp>\l" + -; CHECK-NEXT: "BLEND %d = ir<0>/vp<%4> ir<%tmp4>/ir<%cmp>\l" + -; CHECK-NEXT: "CLONE ir<%idx> = getelementptr ir<%x>, ir<%i>\l" + -; CHECK-NEXT: "WIDEN store ir<%idx>, ir<%d>\l" -; CHECK-NEXT: ] +; CHECK: VPlan { +; CHECK-NEXT: for.body: +; CHECK-NEXT: WIDEN-INDUCTION %i = phi %bc.resume.val, %i.next +; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%i>, ir<5> +; CHECK-NEXT: Successor(s): if.then +; CHECK-EMPTY: +; CHECK-NEXT: if.then: +; CHECK-NEXT: Successor(s): pred.udiv +; CHECK-EMPTY: +; CHECK-NEXT: pred.udiv: { +; CHECK-NEXT: pred.udiv.entry: +; CHECK-NEXT: BRANCH-ON-MASK ir<%cmp> +; CHECK-NEXT: Successor(s): pred.udiv.if pred.udiv.continue +; CHECK-NEXT: CondBit: ir<%cmp> +; CHECK-EMPTY: +; CHECK-NEXT: pred.udiv.if: +; CHECK-NEXT: REPLICATE ir<%tmp4> = udiv ir<%n>, ir<%i> (S->V) +; CHECK-NEXT: Successor(s): pred.udiv.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.udiv.continue: +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION ir<%tmp4> +; CHECK-NEXT: Successor(s): +; CHECK-NEXT: } +; CHECK-EMPTY: +; CHECK-NEXT: if.then.0: +; CHECK-NEXT: Successor(s): for.inc +; CHECK-EMPTY: +; CHECK-NEXT: for.inc: +; CHECK-NEXT: EMIT vp<%4> = not ir<%cmp> +; CHECK-NEXT: BLEND %d = ir<0>/vp<%4> ir<%tmp4>/ir<%cmp> +; CHECK-NEXT: CLONE ir<%idx> = getelementptr ir<%x>, ir<%i> +; CHECK-NEXT: WIDEN store ir<%idx>, ir<%d> +; CHECK-NEXT: Successor(s): +; CHECK-NEXT: } ; entry: br label %for.body diff --git a/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp --- a/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp @@ -103,25 +103,28 @@ fontname=Courier label="\ TopRegion" N1 [label = - "entry:\n" + "entry:\l" + + "Successor(s): for.body\l" ] N1 -> N2 [ label=""] N2 [label = - "for.body:\n" + - "EMIT ir<%indvars.iv> = phi ir<0> ir<%indvars.iv.next>\l" + - "EMIT ir<%arr.idx> = getelementptr ir<%A> ir<%indvars.iv>\l" + - "EMIT ir<%l1> = load ir<%arr.idx>\l" + - "EMIT ir<%res> = add ir<%l1> ir<10>\l" + - "EMIT store ir<%res> ir<%arr.idx>\l" + - "EMIT ir<%indvars.iv.next> = add ir<%indvars.iv> ir<1>\l" + - "EMIT ir<%exitcond> = icmp ir<%indvars.iv.next> ir<%N>\l" + - "CondBit: ir<%exitcond> (for.body)\l" + "for.body:\l" + + " EMIT ir\<%indvars.iv\> = phi ir\<0\> ir\<%indvars.iv.next\>\l" + + " EMIT ir\<%arr.idx\> = getelementptr ir\<%A\> ir\<%indvars.iv\>\l" + + " EMIT ir\<%l1\> = load ir\<%arr.idx\>\l" + + " EMIT ir\<%res\> = add ir\<%l1\> ir\<10\>\l" + + " EMIT store ir\<%res\> ir\<%arr.idx\>\l" + + " EMIT ir\<%indvars.iv.next\> = add ir\<%indvars.iv\> ir\<1\>\l" + + " EMIT ir\<%exitcond\> = icmp ir\<%indvars.iv.next\> ir\<%N\>\l" + + "Successor(s): for.body for.end\l" + + "CondBit: ir\<%exitcond\> (for.body)\l" ] N2 -> N2 [ label="T"] N2 -> N3 [ label="F"] N3 [label = - "for.end:\n" + - "EMIT ret\l" + "for.end:\l" + + " EMIT ret\l" + + "Successor(s):\l" ] } } diff --git a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp --- a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp @@ -333,12 +333,14 @@ VPBB1->appendRecipe(I1); VPBB1->appendRecipe(I2); VPBB1->appendRecipe(I3); + VPBB1->setName("bb1"); VPInstruction *I4 = new VPInstruction(Instruction::Mul, {I2, I1}); VPInstruction *I5 = new VPInstruction(Instruction::Ret, {I4}); VPBasicBlock *VPBB2 = new VPBasicBlock(); VPBB2->appendRecipe(I4); VPBB2->appendRecipe(I5); + VPBB2->setName("bb2"); VPBlockUtils::connectBlocks(VPBB1, VPBB2); @@ -363,21 +365,46 @@ edge [fontname=Courier, fontsize=30] compound=true N0 [label = - ":\n" + - "EMIT vp<%0> = add\l" + - "EMIT vp<%1> = sub vp<%0>\l" + - "EMIT br vp<%0> vp<%1>\l" + "bb1:\l" + + " EMIT vp\<%0\> = add\l" + + " EMIT vp\<%1\> = sub vp\<%0\>\l" + + " EMIT br vp\<%0\> vp\<%1\>\l" + + "Successor(s): bb2\l" ] N0 -> N1 [ label=""] N1 [label = - ":\n" + - "EMIT vp<%3> = mul vp<%1> vp<%0>\l" + - "EMIT ret vp<%3>\l" + "bb2:\l" + + " EMIT vp\<%3\> = mul vp\<%1\> vp\<%0\>\l" + + " EMIT ret vp\<%3\>\l" + + "Successor(s):\l" ] } )"; EXPECT_EQ(ExpectedStr, FullDump); + const char *ExpectedBlock1Str = R"(bb1: + EMIT vp<%0> = add + EMIT vp<%1> = sub vp<%0> + EMIT br vp<%0> vp<%1> +Successor(s): bb2 +)"; + std::string Block1Dump; + raw_string_ostream OS1(Block1Dump); + VPBB1->print(OS1); + EXPECT_EQ(ExpectedBlock1Str, Block1Dump); + + + // Ensure that numbering is good when dumping the second block in isolation. + const char *ExpectedBlock2Str = R"(bb2: + EMIT vp<%3> = mul vp<%1> vp<%0> + EMIT ret vp<%3> +Successor(s): +)"; + std::string Block2Dump; + raw_string_ostream OS2(Block2Dump); + VPBB2->print(OS2); + EXPECT_EQ(ExpectedBlock2Str, Block2Dump); + { std::string I3Dump; raw_string_ostream OS(I3Dump);