diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11550,6 +11550,8 @@
     return false;
 
   switch (VT.getSimpleVT().SimpleTy) {
+  case MVT::f16:
+    return Subtarget->hasFullFP16();
   case MVT::f32:
   case MVT::f64:
     return true;
diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll
--- a/llvm/test/CodeGen/AArch64/f16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll
@@ -62,6 +62,26 @@
   ret half %r
 }
 
+; CHECK-CVT-LABEL: test_fmadd:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fmul s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvt s1, h2
+; CHECK-CVT-NEXT: fadd s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fmadd:
+; CHECK-FP16-NEXT: fmadd h0, h0, h1, h2
+; CHECK-FP16-NEXT: ret
+
+define half @test_fmadd(half %a, half %b, half %c) #0 {
+  %mul = fmul fast half %a, %b
+  %r = fadd fast half %mul, %c
+  ret half %r
+}
 ; CHECK-CVT-LABEL: test_fdiv:
 ; CHECK-CVT-NEXT: fcvt s1, h1
 ; CHECK-CVT-NEXT: fcvt s0, h0
@@ -1305,8 +1325,7 @@
 ; CHECK-CVT-NEXT: ret
 
 ; CHECK-FP16-LABEL: test_fmuladd:
-; CHECK-FP16-NEXT: fmul h0, h0, h1
-; CHECK-FP16-NEXT: fadd h0, h0, h2
+; CHECK-FP16-NEXT: fmadd h0, h0, h1, h2
 ; CHECK-FP16-NEXT: ret
 
 define half @test_fmuladd(half %a, half %b, half %c) #0 {
diff --git a/llvm/test/CodeGen/AArch64/sve-fp-combine.ll b/llvm/test/CodeGen/AArch64/sve-fp-combine.ll
--- a/llvm/test/CodeGen/AArch64/sve-fp-combine.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fp-combine.ll
@@ -1,5 +1,16 @@
 ; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
 
+define <vscale x 8 x half> @fmla_h_sel(<vscale x 8 x i1> %pred, <vscale x 8 x half> %acc,
+                               <vscale x 8 x half> %m1, <vscale x 8 x half> %m2) {
+; CHECK-LABEL: fmla_h_sel:
+; CHECK: fmla z0.h, p0/m, z1.h, z2.h
+; CHECK: ret
+  %mul = fmul fast <vscale x 8 x half> %m1, %m2
+  %add = fadd fast <vscale x 8 x half> %acc, %mul
+  %res = select <vscale x 8 x i1> %pred, <vscale x 8 x half> %add, <vscale x 8 x half> %acc
+  ret <vscale x 8 x half> %res
+}
+
 define <vscale x 4 x float> @fmla_s_sel(<vscale x 4 x i1> %pred, <vscale x 4 x float> %acc,
                                <vscale x 4 x float> %m1, <vscale x 4 x float> %m2) {
 ; CHECK-LABEL: fmla_s_sel:
@@ -33,6 +44,17 @@
   ret <vscale x 2 x double> %res
 }
 
+define <vscale x 8 x half> @fmls_h_sel(<vscale x 8 x i1> %pred, <vscale x 8 x half> %acc,
+                               <vscale x 8 x half> %m1, <vscale x 8 x half> %m2) {
+; CHECK-LABEL: fmls_h_sel:
+; CHECK: fmls z0.h, p0/m, z1.h, z2.h
+; CHECK: ret
+  %mul = fmul fast <vscale x 8 x half> %m1, %m2
+  %sub = fsub fast <vscale x 8 x half> %acc, %mul
+  %res = select <vscale x 8 x i1> %pred, <vscale x 8 x half> %sub, <vscale x 8 x half> %acc
+  ret <vscale x 8 x half> %res
+}
+
 define <vscale x 4 x float> @fmls_s_sel(<vscale x 4 x i1> %pred, <vscale x 4 x float> %acc,
                                <vscale x 4 x float> %m1, <vscale x 4 x float> %m2) {
 ; CHECK-LABEL: fmls_s_sel:
@@ -66,6 +88,16 @@
   ret <vscale x 2 x double> %res
 }
 
+define <vscale x 8 x half> @fmad_h(<vscale x 8 x half> %m1, <vscale x 8 x half> %m2, <vscale x 8 x half> %acc) {
+; CHECK-LABEL: fmad_h:
+; CHECK: ptrue [[PG:p[0-9]+]].h
+; CHECK-NEXT: fmad z0.h, [[PG]]/m, z1.h, z2.h
+; CHECK-NEXT: ret
+  %mul = fmul fast <vscale x 8 x half> %m1, %m2
+  %res = fadd fast <vscale x 8 x half> %acc, %mul
+  ret <vscale x 8 x half> %res
+}
+
 define <vscale x 4 x float> @fmad_s(<vscale x 4 x float> %m1, <vscale x 4 x float> %m2, <vscale x 4 x float> %acc) {
 ; CHECK-LABEL: fmad_s:
 ; CHECK: ptrue [[PG:p[0-9]+]].s
@@ -126,6 +158,16 @@
   ret <vscale x 2 x double> %res
 }
 
+define <vscale x 8 x half> @fmls_h(<vscale x 8 x half> %acc, <vscale x 8 x half> %m1, <vscale x 8 x half> %m2) {
+; CHECK-LABEL: fmls_h:
+; CHECK: ptrue [[PG:p[0-9]+]].h
+; CHECK-NEXT: fmls z0.h, [[PG]]/m, z1.h, z2.h
+; CHECK-NEXT: ret
+  %mul = fmul fast <vscale x 8 x half> %m1, %m2
+  %res = fsub fast <vscale x 8 x half> %acc, %mul
+  ret <vscale x 8 x half> %res
+}
+
 define <vscale x 4 x float> @fmls_s(<vscale x 4 x float> %acc, <vscale x 4 x float> %m1, <vscale x 4 x float> %m2) {
 ; CHECK-LABEL: fmls_s:
 ; CHECK: ptrue [[PG:p[0-9]+]].s
@@ -237,6 +279,23 @@
   ret <vscale x 2 x double> %res
 }
 
+define <vscale x 8 x half> @fnmla_h(<vscale x 8 x half> %acc, <vscale x 8 x half> %m1, <vscale x 8 x half> %m2) {
+; CHECK-LABEL: fnmla_h:
+; CHECK: ptrue [[PG:p[0-9]+]].h
+; CHECK-NEXT: fnmla z0.h, [[PG]]/m, z1.h, z2.h
+; CHECK-NEXT: ret
+  %neg_m1 = fsub fast <vscale x 8 x half>
+               shufflevector (<vscale x 8 x half>
+                 insertelement (<vscale x 8 x half> undef, half -0.000000e+00, i32 0),
+                 <vscale x 8 x half> undef,
+                 <vscale x 8 x i32> zeroinitializer),
+               %m1
+
+  %mul = fmul fast <vscale x 8 x half> %neg_m1, %m2
+  %res = fsub fast <vscale x 8 x half> %mul, %acc
+  ret <vscale x 8 x half> %res
+}
+
 define <vscale x 4 x float> @fnmla_s(<vscale x 4 x float> %acc, <vscale x 4 x float> %m1, <vscale x 4 x float> %m2) {
 ; CHECK-LABEL: fnmla_s:
 ; CHECK: ptrue [[PG:p[0-9]+]].s
@@ -288,6 +347,22 @@
   ret <vscale x 2 x double> %res
 }
 
+define <vscale x 8 x half> @fnmla_h_reversed(<vscale x 8 x half> %acc, <vscale x 8 x half> %m1, <vscale x 8 x half> %m2) {
+; CHECK-LABEL: fnmla_h_reversed:
+; CHECK: ptrue [[PG:p[0-9]+]].h
+; CHECK-NEXT: fnmla z0.h, [[PG]]/m, z1.h, z2.h
+; CHECK-NEXT: ret
+  %mul = fmul fast <vscale x 8 x half> %m1, %m2
+  %add = fadd fast <vscale x 8 x half> %mul, %acc
+  %res = fsub fast <vscale x 8 x half>
+               shufflevector (<vscale x 8 x half>
+                 insertelement (<vscale x 8 x half> undef, half -0.000000e+00, i32 0),
+                 <vscale x 8 x half> undef,
+                 <vscale x 8 x i32> zeroinitializer),
+               %add
+  ret <vscale x 8 x half> %res
+}
+
 define <vscale x 4 x float> @fnmla_s_reversed(<vscale x 4 x float> %acc, <vscale x 4 x float> %m1, <vscale x 4 x float> %m2) {
 ; CHECK-LABEL: fnmla_s_reversed:
 ; CHECK: ptrue [[PG:p[0-9]+]].s
@@ -336,6 +411,16 @@
   ret <vscale x 2 x double> %res
 }
 
+define <vscale x 8 x half> @fnmls_h(<vscale x 8 x half> %acc, <vscale x 8 x half> %m1, <vscale x 8 x half> %m2) {
+; CHECK-LABEL: fnmls_h:
+; CHECK: ptrue [[PG:p[0-9]+]].h
+; CHECK-NEXT: fnmls z0.h, [[PG]]/m, z1.h, z2.h
+; CHECK-NEXT: ret
+  %mul = fmul fast <vscale x 8 x half> %m1, %m2
+  %res = fsub fast <vscale x 8 x half> %mul, %acc
+  ret <vscale x 8 x half> %res
+}
+
 define <vscale x 4 x float> @fnmls_s(<vscale x 4 x float> %acc, <vscale x 4 x float> %m1, <vscale x 4 x float> %m2) {
 ; CHECK-LABEL: fnmls_s:
 ; CHECK: ptrue [[PG:p[0-9]+]].s