diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -1085,7 +1085,9 @@ // // Into: // %select = CSINC %reg, %x, cc - if (mi_match(Reg, MRI, m_GAdd(m_Reg(MatchReg), m_SpecificICst(1)))) { + if (mi_match(Reg, MRI, + m_any_of(m_GAdd(m_Reg(MatchReg), m_SpecificICst(1)), + m_GPtrAdd(m_Reg(MatchReg), m_SpecificICst(1))))) { Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr; Reg = MatchReg; if (Invert) { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir @@ -651,6 +651,37 @@ $w0 = COPY %select(s32) RET_ReallyLR implicit $w0 +... +--- +name: csinc_ptr_add +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x0, $x1, $x2 + ; G_SELECT cc, %true, (G_PTR_ADD %x, 1) -> CSINC %true, %x, cc + + ; CHECK-LABEL: name: csinc_ptr_add + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK: %reg0:gpr64 = COPY $x0 + ; CHECK: %reg1:gpr64 = COPY $x1 + ; CHECK: %cond:gpr32 = COPY %reg0.sub_32 + ; CHECK: %t:gpr64 = COPY $x2 + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv + ; CHECK: %select:gpr64 = CSINCXr %t, %reg1, 1, implicit $nzcv + ; CHECK: $x0 = COPY %select + ; CHECK: RET_ReallyLR implicit $x0 + %reg0:gpr(s64) = COPY $x0 + %reg1:gpr(p0) = COPY $x1 + %cond:gpr(s1) = G_TRUNC %reg0(s64) + %t:gpr(p0) = COPY $x2 + %one:gpr(s64) = G_CONSTANT i64 1 + %ptr_add:gpr(p0) = G_PTR_ADD %reg1(p0), %one + %select:gpr(p0) = G_SELECT %cond(s1), %t, %ptr_add + $x0 = COPY %select(p0) + RET_ReallyLR implicit $x0 + ... --- name: binop_dont_optimize_twice