Index: llvm/lib/Target/Sparc/SparcInstrAliases.td =================================================================== --- llvm/lib/Target/Sparc/SparcInstrAliases.td +++ llvm/lib/Target/Sparc/SparcInstrAliases.td @@ -492,6 +492,7 @@ def : MnemonicAlias<"stuha", "stha">; def : MnemonicAlias<"stsha", "stha">; +def : MnemonicAlias<"stw", "st">, Requires<[HasV9]>; def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>; def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>; Index: llvm/lib/Target/Sparc/SparcInstrInfo.td =================================================================== --- llvm/lib/Target/Sparc/SparcInstrInfo.td +++ llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -1623,6 +1623,17 @@ } } +// Section A.42 - Prefetch Data +let Predicates = [HasV9] in { + def PREFETCHr : F3_1<3, 0b101101, + (outs), (ins MEMrr:$addr, shift_imm5:$rd), + "prefetch [$addr], $rd", []>; + def PREFETCHi : F3_2<3, 0b101101, + (outs), (ins MEMri:$addr, shift_imm5:$rd), + "prefetch [$addr], $rd", []>; +} + + // Section A.43 - Read Privileged Register Instructions let Predicates = [HasV9] in { Index: llvm/test/MC/Sparc/sparcv9-instructions.s =================================================================== --- llvm/test/MC/Sparc/sparcv9-instructions.s +++ llvm/test/MC/Sparc/sparcv9-instructions.s @@ -298,3 +298,16 @@ ! V8-NEXT: rd %pc, %o7 ! V9: rd %pc, %o7 ! encoding: [0x9f,0x41,0x40,0x00] rd %pc, %o7 + + ! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00] + stw %o1, [%o0] + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: prefetch [ %i1 + 0xf80 ], 1 + ! V9: prefetch [%i1+3968], 1 ! encoding: [0xc3,0x6e,0x6f,0x80] + prefetch [ %i1 + 0xf80 ], 1 + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: prefetch [ %i1 + %i2 ], 1 + ! V9: prefetch [%i1+%i2], 1 ! encoding: [0xc3,0x6e,0x40,0x1a] + prefetch [ %i1 + %i2 ], 1