diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td --- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -11,7 +11,7 @@ // // - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) // - MIMGEncGfx8: encoding introduced with gfx8 for atomics -// - MIMGEncGfx10Default: gfx default (non-NSA) encoding +// - MIMGEncGfx10Default: gfx10 default (non-NSA) encoding // - MIMGEncGfx10NSA: gfx10 NSA encoding class MIMGEncoding; @@ -81,9 +81,17 @@ let Key = ["AsmSuffix"]; } -class mimg si_gfx10, bits<8> vi = si_gfx10> { - field bits<8> SI_GFX10 = si_gfx10; - field bits<8> VI = vi; +def MIMG { + int NOP = -1; +} + +class mimgopc { + field bits<8> BASE = base; // Opcode for all but atomics + field bits<8> VI = vi; // VI is only used for atomic instructions + field bits<8> SI = si; // SI is only used for atomic instructions + bit HAS_BASE = !ne(base, MIMG.NOP); + bit HAS_VI = !ne(vi, MIMG.NOP); + bit HAS_SI = !ne(si, MIMG.NOP); } class MIMGLZMapping { @@ -218,8 +226,8 @@ let nsa = 0; } -// Base class for all NSA MIMG instructions. Note that 1-dword addresses always -// use non-NSA variants. +// Base class for all NSA MIMG instructions. +// Note that 1-dword addresses always use non-NSA variants. class MIMG_nsa_gfx10 : MIMG, MIMGe_gfx10 { let SubtargetPredicate = isGFX10Plus; @@ -235,11 +243,11 @@ let nsa = nsah.NSA; } -class MIMG_NoSampler_Helper op, string asm, +class MIMG_NoSampler_Helper - : MIMG_gfx6789 { + : MIMG_gfx6789 { let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), @@ -248,10 +256,10 @@ #!if(BaseOpcode.HasD16, "$d16", ""); } -class MIMG_NoSampler_gfx10 - : MIMG_gfx10 { + : MIMG_gfx10 { let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), @@ -260,10 +268,10 @@ #!if(BaseOpcode.HasD16, "$d16", ""); } -class MIMG_NoSampler_nsa_gfx10 - : MIMG_nsa_gfx10 { + : MIMG_nsa_gfx10 { let InOperandList = !con(AddrIns, (ins SReg_256:$srsrc, DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, @@ -273,39 +281,47 @@ #!if(BaseOpcode.HasD16, "$d16", ""); } -multiclass MIMG_NoSampler_Src_Helper op, string asm, +multiclass MIMG_NoSampler_Src_Helper { let ssamp = 0 in { let VAddrDwords = 1 in { - def _V1 : MIMG_NoSampler_Helper ; - def _V1_gfx10 : MIMG_NoSampler_gfx10; + if op.HAS_BASE then { + def _V1 : MIMG_NoSampler_Helper ; + def _V1_gfx10 : MIMG_NoSampler_gfx10; + } } let VAddrDwords = 2 in { - def _V2 : MIMG_NoSampler_Helper ; - def _V2_gfx10 : MIMG_NoSampler_gfx10; - def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10; + if op.HAS_BASE then { + def _V2 : MIMG_NoSampler_Helper ; + def _V2_gfx10 : MIMG_NoSampler_gfx10; + def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10; + } } let VAddrDwords = 3 in { - def _V3 : MIMG_NoSampler_Helper ; - def _V3_gfx10 : MIMG_NoSampler_gfx10; - def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10; + if op.HAS_BASE then { + def _V3 : MIMG_NoSampler_Helper ; + def _V3_gfx10 : MIMG_NoSampler_gfx10; + def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10; + } } let VAddrDwords = 4 in { - def _V4 : MIMG_NoSampler_Helper ; - def _V4_gfx10 : MIMG_NoSampler_gfx10; - def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10; + if op.HAS_BASE then { + def _V4 : MIMG_NoSampler_Helper ; + def _V4_gfx10 : MIMG_NoSampler_gfx10; + def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10; + } } } } -multiclass MIMG_NoSampler op, string asm, bit has_d16, bit mip = 0, +multiclass MIMG_NoSampler { def "" : MIMGBaseOpcode { let Coordinates = !not(isResInfo); @@ -328,11 +344,11 @@ } } -class MIMG_Store_Helper op, string asm, +class MIMG_Store_Helper - : MIMG_gfx6789 { + : MIMG_gfx6789 { let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), @@ -341,10 +357,10 @@ #!if(BaseOpcode.HasD16, "$d16", ""); } -class MIMG_Store_gfx10 - : MIMG_gfx10 { + : MIMG_gfx10 { let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), @@ -353,10 +369,10 @@ #!if(BaseOpcode.HasD16, "$d16", ""); } -class MIMG_Store_nsa_gfx10 - : MIMG_nsa_gfx10 { + : MIMG_nsa_gfx10 { let InOperandList = !con((ins DataRC:$vdata), AddrIns, (ins SReg_256:$srsrc, DMask:$dmask, @@ -367,37 +383,45 @@ #!if(BaseOpcode.HasD16, "$d16", ""); } -multiclass MIMG_Store_Addr_Helper { let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0, DisableWQM = 1, ssamp = 0 in { let VAddrDwords = 1 in { - def _V1 : MIMG_Store_Helper ; - def _V1_gfx10 : MIMG_Store_gfx10 ; + if op.HAS_BASE then { + def _V1 : MIMG_Store_Helper ; + def _V1_gfx10 : MIMG_Store_gfx10 ; + } } let VAddrDwords = 2 in { - def _V2 : MIMG_Store_Helper ; - def _V2_gfx10 : MIMG_Store_gfx10 ; - def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 ; + if op.HAS_BASE then { + def _V2 : MIMG_Store_Helper ; + def _V2_gfx10 : MIMG_Store_gfx10 ; + def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 ; + } } let VAddrDwords = 3 in { - def _V3 : MIMG_Store_Helper ; - def _V3_gfx10 : MIMG_Store_gfx10 ; - def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 ; + if op.HAS_BASE then { + def _V3 : MIMG_Store_Helper ; + def _V3_gfx10 : MIMG_Store_gfx10 ; + def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 ; + } } let VAddrDwords = 4 in { - def _V4 : MIMG_Store_Helper ; - def _V4_gfx10 : MIMG_Store_gfx10 ; - def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 ; + if op.HAS_BASE then { + def _V4 : MIMG_Store_Helper ; + def _V4_gfx10 : MIMG_Store_gfx10 ; + def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 ; + } } } } -multiclass MIMG_Store op, string asm, bit has_d16, bit mip = 0> { +multiclass MIMG_Store { def "" : MIMGBaseOpcode { let Store = 1; let LodOrClampOrMip = mip; @@ -430,24 +454,24 @@ let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"; } -class MIMG_Atomic_si - : MIMG_Atomic_gfx6789_base { let AssemblerPredicate = isGFX6GFX7; } -class MIMG_Atomic_vi : MIMG_Atomic_gfx6789_base { let AssemblerPredicate = isGFX8GFX9; let MIMGEncoding = MIMGEncGfx8; } -class MIMG_Atomic_gfx10 - : MIMG_gfx10(op.SI_GFX10), (outs DataRC:$vdst), + : MIMG_gfx10(op.BASE), (outs DataRC:$vdst), !if(enableDisasm, "AMDGPU", "")> { let Constraints = "$vdst = $vdata"; let AsmMatchConverter = "cvtMIMGAtomic"; @@ -458,10 +482,10 @@ let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"; } -class MIMG_Atomic_nsa_gfx10 - : MIMG_nsa_gfx10(op.SI_GFX10), (outs DataRC:$vdst), num_addrs, + : MIMG_nsa_gfx10(op.BASE), (outs DataRC:$vdst), num_addrs, !if(enableDisasm, "AMDGPU", "")> { let Constraints = "$vdst = $vdata"; let AsmMatchConverter = "cvtMIMGAtomic"; @@ -474,39 +498,64 @@ let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"; } -multiclass MIMG_Atomic_Addr_Helper_m { + bit enableDasm = 0, + bit isFP = 0> { let hasSideEffects = 1, // FIXME: remove this mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1, - ssamp = 0 in { + ssamp = 0, FPAtomic = isFP in { let VAddrDwords = 1 in { - def _V1_si : MIMG_Atomic_si ; - def _V1_vi : MIMG_Atomic_vi ; - def _V1_gfx10 : MIMG_Atomic_gfx10 ; + if op.HAS_SI then { + def _V1_si : MIMG_Atomic_si ; + } + if op.HAS_VI then { + def _V1_vi : MIMG_Atomic_vi ; + } + if op.HAS_BASE then { + def _V1_gfx10 : MIMG_Atomic_gfx10 ; + } } let VAddrDwords = 2 in { - def _V2_si : MIMG_Atomic_si ; - def _V2_vi : MIMG_Atomic_vi ; - def _V2_gfx10 : MIMG_Atomic_gfx10 ; - def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 ; + if op.HAS_SI then { + def _V2_si : MIMG_Atomic_si ; + } + if op.HAS_VI then { + def _V2_vi : MIMG_Atomic_vi ; + } + if op.HAS_BASE then { + def _V2_gfx10 : MIMG_Atomic_gfx10 ; + def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 ; + } } let VAddrDwords = 3 in { - def _V3_si : MIMG_Atomic_si ; - def _V3_vi : MIMG_Atomic_vi ; - def _V3_gfx10 : MIMG_Atomic_gfx10 ; - def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 ; + if op.HAS_SI then { + def _V3_si : MIMG_Atomic_si ; + } + if op.HAS_VI then { + def _V3_vi : MIMG_Atomic_vi ; + } + if op.HAS_BASE then { + def _V3_gfx10 : MIMG_Atomic_gfx10 ; + def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 ; + } } let VAddrDwords = 4 in { - def _V4_si : MIMG_Atomic_si ; - def _V4_vi : MIMG_Atomic_vi ; - def _V4_gfx10 : MIMG_Atomic_gfx10 ; - def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 ; + if op.HAS_VI then { + def _V4_vi : MIMG_Atomic_vi ; + } + if op.HAS_SI then { + def _V4_si : MIMG_Atomic_si ; + } + if op.HAS_BASE then { + def _V4_gfx10 : MIMG_Atomic_gfx10 ; + def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 ; + } } } } -multiclass MIMG_Atomic { // 64-bit atomics +multiclass MIMG_Atomic { // 64-bit atomics def "" : MIMGBaseOpcode { let Atomic = 1; let AtomicX2 = isCmpSwap; @@ -517,15 +566,15 @@ // using dmask and tfe. Only 32-bit variant is registered with disassembler. // Other variants are reconstructed by disassembler using dmask and tfe. let VDataDwords = !if(isCmpSwap, 2, 1) in - defm _V1 : MIMG_Atomic_Addr_Helper_m ; + defm _V1 : MIMG_Atomic_Addr_Helper_m ; let VDataDwords = !if(isCmpSwap, 4, 2) in - defm _V2 : MIMG_Atomic_Addr_Helper_m ; + defm _V2 : MIMG_Atomic_Addr_Helper_m ; } } -class MIMG_Sampler_Helper op, string asm, RegisterClass dst_rc, +class MIMG_Sampler_Helper - : MIMG_gfx6789 { + : MIMG_gfx6789 { let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), @@ -534,10 +583,10 @@ #!if(BaseOpcode.HasD16, "$d16", ""); } -class MIMG_Sampler_gfx10 - : MIMG_gfx10 { + : MIMG_gfx10 { let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), @@ -547,10 +596,10 @@ #!if(BaseOpcode.HasD16, "$d16", ""); } -class MIMG_Sampler_nsa_gfx10 - : MIMG_nsa_gfx10 { + : MIMG_nsa_gfx10 { let InOperandList = !con(AddrIns, (ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc, @@ -632,25 +681,29 @@ lhs)))); } -multiclass MIMG_Sampler_Src_Helper op, string asm, +multiclass MIMG_Sampler_Src_Helper { foreach addr = MIMG_Sampler_AddrSizes.MachineInstrs in { let VAddrDwords = addr.NumWords in { - def _V # addr.NumWords - : MIMG_Sampler_Helper ; - def _V # addr.NumWords # _gfx10 - : MIMG_Sampler_gfx10 ; + if op.HAS_BASE then { + def _V # addr.NumWords + : MIMG_Sampler_Helper ; + def _V # addr.NumWords # _gfx10 + : MIMG_Sampler_gfx10 ; + } } } foreach addr = MIMG_Sampler_AddrSizes.NSAInstrs in { let VAddrDwords = addr.NumWords in { - def _V # addr.NumWords # _nsa_gfx10 - : MIMG_Sampler_nsa_gfx10; + if op.HAS_BASE then { + def _V # addr.NumWords # _nsa_gfx10 + : MIMG_Sampler_nsa_gfx10; + } } } } @@ -663,7 +716,7 @@ let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); } -multiclass MIMG_Sampler op, AMDGPUSampleVariant sample, bit wqm = 0, +multiclass MIMG_Sampler { def "" : MIMG_Sampler_BaseOpcode { @@ -686,10 +739,10 @@ } } -multiclass MIMG_Sampler_WQM op, AMDGPUSampleVariant sample> +multiclass MIMG_Sampler_WQM : MIMG_Sampler; -multiclass MIMG_Gather op, AMDGPUSampleVariant sample, bit wqm = 0, +multiclass MIMG_Gather { def "" : MIMG_Sampler_BaseOpcode { let HasD16 = 1; @@ -707,11 +760,11 @@ } } -multiclass MIMG_Gather_WQM op, AMDGPUSampleVariant sample> +multiclass MIMG_Gather_WQM : MIMG_Gather; -class MIMG_IntersectRay_gfx10 - : MIMG_gfx10 { +class MIMG_IntersectRay_gfx10 + : MIMG_gfx10 { let InOperandList = !con((ins AddrRC:$vaddr0, SReg_128:$srsrc), !if(A16, (ins GFX10A16:$a16), (ins))); @@ -720,15 +773,15 @@ let nsa = 0; } -class MIMG_IntersectRay_nsa_gfx10 - : MIMG_nsa_gfx10 { +class MIMG_IntersectRay_nsa_gfx10 + : MIMG_nsa_gfx10 { let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc), !if(A16, (ins GFX10A16:$a16), (ins))); let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc"#!if(A16, "$a16", ""); } -multiclass MIMG_IntersectRay { +multiclass MIMG_IntersectRay { def "" : MIMGBaseOpcode; let SubtargetPredicate = HasGFX10_BEncoding, AssemblerPredicate = HasGFX10_BEncoding, @@ -762,131 +815,131 @@ //===----------------------------------------------------------------------===// // MIMG Instructions //===----------------------------------------------------------------------===// -defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load", 1>; -defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip", 1, 1>; -defm IMAGE_LOAD_PCK : MIMG_NoSampler <0x00000002, "image_load_pck", 0>; -defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <0x00000003, "image_load_pck_sgn", 0>; -defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <0x00000004, "image_load_mip_pck", 0, 1>; -defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <0x00000005, "image_load_mip_pck_sgn", 0, 1>; -defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store", 1>; -defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip", 1, 1>; -defm IMAGE_STORE_PCK : MIMG_Store <0x0000000a, "image_store_pck", 0>; -defm IMAGE_STORE_MIP_PCK : MIMG_Store <0x0000000b, "image_store_mip_pck", 0, 1>; - -defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo", 0, 1, 1>; - -defm IMAGE_ATOMIC_SWAP : MIMG_Atomic , "image_atomic_swap">; -defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic , "image_atomic_cmpswap", 1>; -defm IMAGE_ATOMIC_ADD : MIMG_Atomic , "image_atomic_add">; -defm IMAGE_ATOMIC_SUB : MIMG_Atomic , "image_atomic_sub">; -//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI -defm IMAGE_ATOMIC_SMIN : MIMG_Atomic , "image_atomic_smin">; -defm IMAGE_ATOMIC_UMIN : MIMG_Atomic , "image_atomic_umin">; -defm IMAGE_ATOMIC_SMAX : MIMG_Atomic , "image_atomic_smax">; -defm IMAGE_ATOMIC_UMAX : MIMG_Atomic , "image_atomic_umax">; -defm IMAGE_ATOMIC_AND : MIMG_Atomic , "image_atomic_and">; -defm IMAGE_ATOMIC_OR : MIMG_Atomic , "image_atomic_or">; -defm IMAGE_ATOMIC_XOR : MIMG_Atomic , "image_atomic_xor">; -defm IMAGE_ATOMIC_INC : MIMG_Atomic , "image_atomic_inc">; -defm IMAGE_ATOMIC_DEC : MIMG_Atomic , "image_atomic_dec">; -//let FPAtomic = 1 in { -//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d, 1>; -- not on VI -//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI -//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI -//} // End let FPAtomic = 1 -defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, AMDGPUSample>; -defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, AMDGPUSample_cl>; -defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, AMDGPUSample_d>; -defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, AMDGPUSample_d_cl>; -defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler <0x000000a2, AMDGPUSample_d, 0, 1>; -defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler <0x000000a3, AMDGPUSample_d_cl, 0, 1>; -defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, AMDGPUSample_l>; -defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, AMDGPUSample_b>; -defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, AMDGPUSample_b_cl>; -defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, AMDGPUSample_lz>; -defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, AMDGPUSample_c>; -defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, AMDGPUSample_c_cl>; -defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, AMDGPUSample_c_d>; -defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, AMDGPUSample_c_d_cl>; -defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler <0x000000aa, AMDGPUSample_c_d, 0, 1>; -defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler <0x000000ab, AMDGPUSample_c_d_cl, 0, 1>; -defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, AMDGPUSample_c_l>; -defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, AMDGPUSample_c_b>; -defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, AMDGPUSample_c_b_cl>; -defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, AMDGPUSample_c_lz>; -defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, AMDGPUSample_o>; -defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, AMDGPUSample_cl_o>; -defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, AMDGPUSample_d_o>; -defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, AMDGPUSample_d_cl_o>; -defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler <0x000000b2, AMDGPUSample_d_o, 0, 1>; -defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler <0x000000b3, AMDGPUSample_d_cl_o, 0, 1>; -defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, AMDGPUSample_l_o>; -defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, AMDGPUSample_b_o>; -defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, AMDGPUSample_b_cl_o>; -defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, AMDGPUSample_lz_o>; -defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, AMDGPUSample_c_o>; -defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, AMDGPUSample_c_cl_o>; -defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, AMDGPUSample_c_d_o>; -defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, AMDGPUSample_c_d_cl_o>; -defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler <0x000000ba, AMDGPUSample_c_d_o, 0, 1>; -defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler <0x000000bb, AMDGPUSample_c_d_cl_o, 0, 1>; -defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, AMDGPUSample_c_l_o>; -defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, AMDGPUSample_c_b_cl_o>; -defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, AMDGPUSample_c_b_o>; -defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, AMDGPUSample_c_lz_o>; -defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, AMDGPUSample>; -defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, AMDGPUSample_cl>; -defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, AMDGPUSample_l>; -defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, AMDGPUSample_b>; -defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, AMDGPUSample_b_cl>; -defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, AMDGPUSample_lz>; -defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, AMDGPUSample_c>; -defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, AMDGPUSample_c_cl>; -defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, AMDGPUSample_c_l>; -defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, AMDGPUSample_c_b>; -defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, AMDGPUSample_c_b_cl>; -defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, AMDGPUSample_c_lz>; -defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, AMDGPUSample_o>; -defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, AMDGPUSample_cl_o>; -defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, AMDGPUSample_l_o>; -defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, AMDGPUSample_b_o>; -defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, AMDGPUSample_b_cl_o>; -defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, AMDGPUSample_lz_o>; -defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, AMDGPUSample_c_o>; -defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, AMDGPUSample_c_cl_o>; -defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, AMDGPUSample_c_l_o>; -defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, AMDGPUSample_c_b_o>; -defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, AMDGPUSample_c_b_cl_o>; -defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, AMDGPUSample_c_lz_o>; - -defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, AMDGPUSample, 1, 0, 1, "image_get_lod">; - -defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, AMDGPUSample_cd>; -defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, AMDGPUSample_cd_cl>; -defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, AMDGPUSample_c_cd>; -defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, AMDGPUSample_c_cd_cl>; -defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, AMDGPUSample_cd_o>; -defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, AMDGPUSample_cd_cl_o>; -defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, AMDGPUSample_c_cd_o>; -defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, AMDGPUSample_c_cd_cl_o>; -defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler <0x000000e8, AMDGPUSample_cd, 0, 1>; -defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler <0x000000e9, AMDGPUSample_cd_cl, 0, 1>; -defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler <0x000000ea, AMDGPUSample_c_cd, 0, 1>; -defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler <0x000000eb, AMDGPUSample_c_cd_cl, 0, 1>; -defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler <0x000000ec, AMDGPUSample_cd_o, 0, 1>; -defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler <0x000000ed, AMDGPUSample_cd_cl_o, 0, 1>; -defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler <0x000000ee, AMDGPUSample_c_cd_o, 0, 1>; -defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler <0x000000ef, AMDGPUSample_c_cd_cl_o, 0, 1>; -//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; -//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; +defm IMAGE_LOAD : MIMG_NoSampler , "image_load", 1>; +defm IMAGE_LOAD_MIP : MIMG_NoSampler , "image_load_mip", 1, 1>; +defm IMAGE_LOAD_PCK : MIMG_NoSampler , "image_load_pck", 0>; +defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler , "image_load_pck_sgn", 0>; +defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler , "image_load_mip_pck", 0, 1>; +defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler , "image_load_mip_pck_sgn", 0, 1>; +defm IMAGE_STORE : MIMG_Store , "image_store", 1>; +defm IMAGE_STORE_MIP : MIMG_Store , "image_store_mip", 1, 1>; +defm IMAGE_STORE_PCK : MIMG_Store , "image_store_pck", 0>; +defm IMAGE_STORE_MIP_PCK : MIMG_Store , "image_store_mip_pck", 0, 1>; + +defm IMAGE_GET_RESINFO : MIMG_NoSampler , "image_get_resinfo", 0, 1, 1>; + +defm IMAGE_ATOMIC_SWAP : MIMG_Atomic , "image_atomic_swap">; +defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic , "image_atomic_cmpswap", 1>; +defm IMAGE_ATOMIC_ADD : MIMG_Atomic , "image_atomic_add">; +defm IMAGE_ATOMIC_SUB : MIMG_Atomic , "image_atomic_sub">; +defm IMAGE_ATOMIC_RSUB : MIMG_Atomic , "image_atomic_rsub">; +defm IMAGE_ATOMIC_SMIN : MIMG_Atomic , "image_atomic_smin">; +defm IMAGE_ATOMIC_UMIN : MIMG_Atomic , "image_atomic_umin">; +defm IMAGE_ATOMIC_SMAX : MIMG_Atomic , "image_atomic_smax">; +defm IMAGE_ATOMIC_UMAX : MIMG_Atomic , "image_atomic_umax">; +defm IMAGE_ATOMIC_AND : MIMG_Atomic , "image_atomic_and">; +defm IMAGE_ATOMIC_OR : MIMG_Atomic , "image_atomic_or">; +defm IMAGE_ATOMIC_XOR : MIMG_Atomic , "image_atomic_xor">; +defm IMAGE_ATOMIC_INC : MIMG_Atomic , "image_atomic_inc">; +defm IMAGE_ATOMIC_DEC : MIMG_Atomic , "image_atomic_dec">; +defm IMAGE_ATOMIC_FCMPSWAP : MIMG_Atomic , "image_atomic_fcmpswap", 0, 1>; +defm IMAGE_ATOMIC_FMIN : MIMG_Atomic , "image_atomic_fmin", 0, 1>; +defm IMAGE_ATOMIC_FMAX : MIMG_Atomic , "image_atomic_fmax", 0, 1>; +defm IMAGE_SAMPLE : MIMG_Sampler_WQM , AMDGPUSample>; +defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM , AMDGPUSample_cl>; +defm IMAGE_SAMPLE_D : MIMG_Sampler , AMDGPUSample_d>; +defm IMAGE_SAMPLE_D_CL : MIMG_Sampler , AMDGPUSample_d_cl>; +defm IMAGE_SAMPLE_D_G16 : MIMG_Sampler , AMDGPUSample_d, 0, 1>; +defm IMAGE_SAMPLE_D_CL_G16 : MIMG_Sampler , AMDGPUSample_d_cl, 0, 1>; +defm IMAGE_SAMPLE_L : MIMG_Sampler , AMDGPUSample_l>; +defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM , AMDGPUSample_b>; +defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM , AMDGPUSample_b_cl>; +defm IMAGE_SAMPLE_LZ : MIMG_Sampler , AMDGPUSample_lz>; +defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM , AMDGPUSample_c>; +defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM , AMDGPUSample_c_cl>; +defm IMAGE_SAMPLE_C_D : MIMG_Sampler , AMDGPUSample_c_d>; +defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler , AMDGPUSample_c_d_cl>; +defm IMAGE_SAMPLE_C_D_G16 : MIMG_Sampler , AMDGPUSample_c_d, 0, 1>; +defm IMAGE_SAMPLE_C_D_CL_G16 : MIMG_Sampler , AMDGPUSample_c_d_cl, 0, 1>; +defm IMAGE_SAMPLE_C_L : MIMG_Sampler , AMDGPUSample_c_l>; +defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM , AMDGPUSample_c_b>; +defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM , AMDGPUSample_c_b_cl>; +defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler , AMDGPUSample_c_lz>; +defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM , AMDGPUSample_o>; +defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM , AMDGPUSample_cl_o>; +defm IMAGE_SAMPLE_D_O : MIMG_Sampler , AMDGPUSample_d_o>; +defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler , AMDGPUSample_d_cl_o>; +defm IMAGE_SAMPLE_D_O_G16 : MIMG_Sampler , AMDGPUSample_d_o, 0, 1>; +defm IMAGE_SAMPLE_D_CL_O_G16 : MIMG_Sampler , AMDGPUSample_d_cl_o, 0, 1>; +defm IMAGE_SAMPLE_L_O : MIMG_Sampler , AMDGPUSample_l_o>; +defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM , AMDGPUSample_b_o>; +defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM , AMDGPUSample_b_cl_o>; +defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler , AMDGPUSample_lz_o>; +defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM , AMDGPUSample_c_o>; +defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM , AMDGPUSample_c_cl_o>; +defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler , AMDGPUSample_c_d_o>; +defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler , AMDGPUSample_c_d_cl_o>; +defm IMAGE_SAMPLE_C_D_O_G16 : MIMG_Sampler , AMDGPUSample_c_d_o, 0, 1>; +defm IMAGE_SAMPLE_C_D_CL_O_G16 : MIMG_Sampler , AMDGPUSample_c_d_cl_o, 0, 1>; +defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler , AMDGPUSample_c_l_o>; +defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM , AMDGPUSample_c_b_cl_o>; +defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM , AMDGPUSample_c_b_o>; +defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler , AMDGPUSample_c_lz_o>; +defm IMAGE_GATHER4 : MIMG_Gather_WQM , AMDGPUSample>; +defm IMAGE_GATHER4_CL : MIMG_Gather_WQM , AMDGPUSample_cl>; +defm IMAGE_GATHER4_L : MIMG_Gather , AMDGPUSample_l>; +defm IMAGE_GATHER4_B : MIMG_Gather_WQM , AMDGPUSample_b>; +defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM , AMDGPUSample_b_cl>; +defm IMAGE_GATHER4_LZ : MIMG_Gather , AMDGPUSample_lz>; +defm IMAGE_GATHER4_C : MIMG_Gather_WQM , AMDGPUSample_c>; +defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM , AMDGPUSample_c_cl>; +defm IMAGE_GATHER4_C_L : MIMG_Gather , AMDGPUSample_c_l>; +defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM , AMDGPUSample_c_b>; +defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM , AMDGPUSample_c_b_cl>; +defm IMAGE_GATHER4_C_LZ : MIMG_Gather , AMDGPUSample_c_lz>; +defm IMAGE_GATHER4_O : MIMG_Gather_WQM , AMDGPUSample_o>; +defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM , AMDGPUSample_cl_o>; +defm IMAGE_GATHER4_L_O : MIMG_Gather , AMDGPUSample_l_o>; +defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM , AMDGPUSample_b_o>; +defm IMAGE_GATHER4_B_CL_O : MIMG_Gather , AMDGPUSample_b_cl_o>; +defm IMAGE_GATHER4_LZ_O : MIMG_Gather , AMDGPUSample_lz_o>; +defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM , AMDGPUSample_c_o>; +defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM , AMDGPUSample_c_cl_o>; +defm IMAGE_GATHER4_C_L_O : MIMG_Gather , AMDGPUSample_c_l_o>; +defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM , AMDGPUSample_c_b_o>; +defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM , AMDGPUSample_c_b_cl_o>; +defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather , AMDGPUSample_c_lz_o>; +//defm IMAGE_GATHER4H : MIMG_Gather_WQM , ?>; + +defm IMAGE_GET_LOD : MIMG_Sampler , AMDGPUSample, 1, 0, 1, "image_get_lod">; + +defm IMAGE_SAMPLE_CD : MIMG_Sampler , AMDGPUSample_cd>; +defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler , AMDGPUSample_cd_cl>; +defm IMAGE_SAMPLE_C_CD : MIMG_Sampler , AMDGPUSample_c_cd>; +defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler , AMDGPUSample_c_cd_cl>; +defm IMAGE_SAMPLE_CD_O : MIMG_Sampler , AMDGPUSample_cd_o>; +defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler , AMDGPUSample_cd_cl_o>; +defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler , AMDGPUSample_c_cd_o>; +defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler , AMDGPUSample_c_cd_cl_o>; +defm IMAGE_SAMPLE_CD_G16 : MIMG_Sampler , AMDGPUSample_cd, 0, 1>; +defm IMAGE_SAMPLE_CD_CL_G16 : MIMG_Sampler , AMDGPUSample_cd_cl, 0, 1>; +defm IMAGE_SAMPLE_C_CD_G16 : MIMG_Sampler , AMDGPUSample_c_cd, 0, 1>; +defm IMAGE_SAMPLE_C_CD_CL_G16 : MIMG_Sampler , AMDGPUSample_c_cd_cl, 0, 1>; +defm IMAGE_SAMPLE_CD_O_G16 : MIMG_Sampler , AMDGPUSample_cd_o, 0, 1>; +defm IMAGE_SAMPLE_CD_CL_O_G16 : MIMG_Sampler , AMDGPUSample_cd_cl_o, 0, 1>; +defm IMAGE_SAMPLE_C_CD_O_G16 : MIMG_Sampler , AMDGPUSample_c_cd_o, 0, 1>; +defm IMAGE_SAMPLE_C_CD_CL_O_G16 : MIMG_Sampler , AMDGPUSample_c_cd_cl_o, 0, 1>; + +//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", mimgopc<0x7e>>; +//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", mimgopc<0x7f>>; let SubtargetPredicate = HasGFX10_BEncoding in -defm IMAGE_MSAA_LOAD : MIMG_NoSampler <0x00000080, "image_msaa_load", 1>; +defm IMAGE_MSAA_LOAD : MIMG_NoSampler , "image_msaa_load", 1>; -defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay<0xe6, "image_bvh_intersect_ray", 11, 0>; -defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay<0xe6, "image_bvh_intersect_ray", 8, 1>; -defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay<0xe7, "image_bvh64_intersect_ray", 12, 0>; -defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay<0xe7, "image_bvh64_intersect_ray", 9, 1>; +defm IMAGE_BVH_INTERSECT_RAY : MIMG_IntersectRay, "image_bvh_intersect_ray", 11, 0>; +defm IMAGE_BVH_INTERSECT_RAY_a16 : MIMG_IntersectRay, "image_bvh_intersect_ray", 8, 1>; +defm IMAGE_BVH64_INTERSECT_RAY : MIMG_IntersectRay, "image_bvh64_intersect_ray", 12, 0>; +defm IMAGE_BVH64_INTERSECT_RAY_a16 : MIMG_IntersectRay, "image_bvh64_intersect_ray", 9, 1>; /********** ========================================= **********/ /********** Table of dimension-aware image intrinsics **********/ diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s --- a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s @@ -136,14 +136,14 @@ image_atomic_dec v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; GFX10: image_atomic_dec v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x70,0xf0,0x20,0x04,0x18,0x00] -;image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc -; TODO-GFX10: ; encoding: [0x00,0x23,0x74,0xf0,0x20,0x04,0x18,0x00] +image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc +; GFX10: image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x23,0x74,0xf0,0x20,0x04,0x18,0x00] -;image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc -; TODO-GFX10: ; encoding: [0x00,0x21,0x78,0xf0,0x20,0x04,0x18,0x00] +image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc +; GFX10: image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x78,0xf0,0x20,0x04,0x18,0x00] -;image_atomic_fmax v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc -; TODO-GFX10: ; encoding: [0x00,0x21,0x7c,0xf0,0x20,0x04,0x18,0x00] +image_atomic_fmax v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc +; GFX10: image_atomic_fmax v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x7c,0xf0,0x20,0x04,0x18,0x00] image_sample v[64:66], v32, s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; GFX10: image_sample v[64:66], v32, s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x07,0x80,0xf0,0x20,0x40,0x21,0x03] diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s --- a/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s +++ b/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s @@ -1110,6 +1110,48 @@ image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm da // CHECK: [0x00,0x51,0x48,0xf0,0x02,0x01,0x03,0x00] +image_atomic_rsub v1, v2, s[12:19] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0x02,0x01,0x03,0x00] + +image_atomic_rsub v252, v2, s[12:19] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0x02,0xfc,0x03,0x00] + +image_atomic_rsub v1, v255, s[12:19] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0xff,0x01,0x03,0x00] + +image_atomic_rsub v1, v2, s[16:23] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0x02,0x01,0x04,0x00] + +image_atomic_rsub v1, v2, s[96:103] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0x02,0x01,0x18,0x00] + +image_atomic_rsub v1, v2, ttmp[4:11] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0x02,0x01,0x1d,0x00] + +image_atomic_rsub v[1:2], v2, s[12:19] dmask:0x3 unorm +// CHECK: [0x00,0x13,0x4c,0xf0,0x02,0x01,0x03,0x00] + +image_atomic_rsub v1, v[2:3], s[12:19] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0x02,0x01,0x03,0x00] + +image_atomic_rsub v1, v[2:4], s[12:19] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0x02,0x01,0x03,0x00] + +image_atomic_rsub v1, v[2:5], s[12:19] dmask:0x1 unorm +// CHECK: [0x00,0x11,0x4c,0xf0,0x02,0x01,0x03,0x00] + +image_atomic_rsub v1, v2, s[12:19] dmask:0x1 unorm glc +// CHECK: [0x00,0x31,0x4c,0xf0,0x02,0x01,0x03,0x00] + +image_atomic_rsub v1, v2, s[12:19] dmask:0x1 unorm slc +// CHECK: [0x00,0x11,0x4c,0xf2,0x02,0x01,0x03,0x00] + +image_atomic_rsub v1, v2, s[12:19] dmask:0x1 unorm lwe +// CHECK: [0x00,0x11,0x4e,0xf0,0x02,0x01,0x03,0x00] + +image_atomic_rsub v1, v2, s[12:19] dmask:0x1 unorm da +// CHECK: [0x00,0x51,0x4c,0xf0,0x02,0x01,0x03,0x00] + image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm // CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x03,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt --- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt @@ -204,9 +204,14 @@ # GFX10: image_atomic_dec v16, v8, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x31,0x70,0xf0,0x08,0x10,0x18,0x00] 0x00,0x31,0x70,0xf0,0x08,0x10,0x18,0x00 -# TODO: image_atomic_fcmpswap -# TODO: image_atomic_fmin -# TODO: image_atomic_fmax +# GFX10: image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x23,0x74,0xf0,0x20,0x04,0x18,0x00] +0x00,0x23,0x74,0xf0,0x20,0x04,0x18,0x00 + +# GFX10: image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x78,0xf0,0x20,0x04,0x18,0x00] +0x00,0x21,0x78,0xf0,0x20,0x04,0x18,0x00 + +# GFX10: image_atomic_fmax v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x7c,0xf0,0x20,0x04,0x18,0x00] +0x00,0x21,0x7c,0xf0,0x20,0x04,0x18,0x00 # GFX10: image_sample v[16:19], v8, s[96:103], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0x80,0xf0,0x08,0x10,0x18,0x00] 0x00,0x0f,0x80,0xf0,0x08,0x10,0x18,0x00