diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -265,14 +265,19 @@ /// \p Handler to move them to the assigned locations. /// /// \return True if everything has succeeded, false otherwise. - bool handleAssignments(MachineIRBuilder &MIRBuilder, - SmallVectorImpl &Args, - ValueHandler &Handler) const; - bool handleAssignments(CCState &CCState, - SmallVectorImpl &ArgLocs, - MachineIRBuilder &MIRBuilder, - SmallVectorImpl &Args, - ValueHandler &Handler) const; + bool handleAssignments( + MachineIRBuilder &MIRBuilder, SmallVectorImpl &Args, + ValueHandler &Handler, + std::function TypeIsValidForThisReturn = + [](EVT T) { return false; }, + Register ThisReturnReg = Register()) const; + bool handleAssignments( + CCState &CCState, SmallVectorImpl &ArgLocs, + MachineIRBuilder &MIRBuilder, SmallVectorImpl &Args, + ValueHandler &Handler, + std::function TypeIsValidForThisReturn = + [](EVT T) { return false; }, + Register ThisReturnReg = Register()) const; /// Analyze passed or returned values from a call, supplied in \p ArgInfo, /// incorporating info about the passed values into \p CCState. diff --git a/llvm/include/llvm/CodeGen/TargetCallingConv.h b/llvm/include/llvm/CodeGen/TargetCallingConv.h --- a/llvm/include/llvm/CodeGen/TargetCallingConv.h +++ b/llvm/include/llvm/CodeGen/TargetCallingConv.h @@ -119,7 +119,7 @@ void setNest() { IsNest = 1; } bool isReturned() const { return IsReturned; } - void setReturned() { IsReturned = 1; } + void setReturned(bool V = true) { IsReturned = V; } bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; } void setInConsecutiveRegs(bool Flag = true) { IsInConsecutiveRegs = Flag; } diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -170,6 +170,9 @@ Flags.setByValAlign(FrameAlign); } Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty)); + + if (Flags.isSwiftSelf()) + Flags.setReturned(false); } template void @@ -223,21 +226,23 @@ MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]); } -bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder, - SmallVectorImpl &Args, - ValueHandler &Handler) const { +bool CallLowering::handleAssignments( + MachineIRBuilder &MIRBuilder, SmallVectorImpl &Args, + ValueHandler &Handler, std::function TypeIsValidForThisReturn, + Register ThisReturnReg) const { MachineFunction &MF = MIRBuilder.getMF(); const Function &F = MF.getFunction(); SmallVector ArgLocs; CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); - return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler); + return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler, + TypeIsValidForThisReturn, ThisReturnReg); } -bool CallLowering::handleAssignments(CCState &CCInfo, - SmallVectorImpl &ArgLocs, - MachineIRBuilder &MIRBuilder, - SmallVectorImpl &Args, - ValueHandler &Handler) const { +bool CallLowering::handleAssignments( + CCState &CCInfo, SmallVectorImpl &ArgLocs, + MachineIRBuilder &MIRBuilder, SmallVectorImpl &Args, + ValueHandler &Handler, std::function TypeIsValidForThisReturn, + Register ThisReturnReg) const { MachineFunction &MF = MIRBuilder.getMF(); const Function &F = MF.getFunction(); const DataLayout &DL = F.getParent()->getDataLayout(); @@ -330,6 +335,15 @@ if (PartIdx == NumParts - 1) Flags.setSplitEnd(); } + + // TODO: Also check if there is a valid extension that preserves the + // bits. However currently this call lowering doesn't support non-exact + // split parts, so that can't be tested. + if (OrigFlags.isReturned() && + (NumParts * NewVT.getSizeInBits() != CurVT.getSizeInBits())) { + Flags.setReturned(false); + } + Args[i].Regs.push_back(Unmerge.getReg(PartIdx)); Args[i].Flags.push_back(Flags); if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, @@ -394,6 +408,13 @@ assert(VA.isRegLoc() && "custom loc should have been handled already"); + if (i == 0 && ThisReturnReg.isValid() && + Handler.isIncomingArgumentHandler() && + TypeIsValidForThisReturn(VAVT)) { + Handler.assignValueToReg(Args[i].Regs[i], ThisReturnReg, VA); + continue; + } + // GlobalISel does not currently work for scalable vectors. if (OrigVT.getFixedSizeInBits() >= VAVT.getFixedSizeInBits() || !Handler.isIncomingArgumentHandler()) { diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp --- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -152,6 +152,16 @@ MachineInstrBuilder MIB; }; +/// A special return arg handler for "returned" attribute arg calls. +struct ReturnedArgCallReturnHandler : public CallReturnHandler { + ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI, + MachineInstrBuilder MIB, CCAssignFn *AssignFn) + : CallReturnHandler(MIRBuilder, MRI, MIB, AssignFn) {} + + void markPhysRegUsed(MCRegister PhysReg) override {} +}; + struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler { OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB, CCAssignFn *AssignFn, @@ -878,6 +888,17 @@ if (!handleAssignments(MIRBuilder, OutArgs, Handler)) return false; + if (!OutArgs.empty() && OutArgs[0].Flags[0].isReturned()) { + // For 'this' returns, use the X0-preserving mask if applicable + Mask = TRI->getThisReturnPreservedMask(MF, Info.CallConv); + if (!Mask) { + OutArgs[0].Flags[0].setReturned(false); + Mask = TRI->getCallPreservedMask(MF, Info.CallConv); + } + } else { + Mask = TRI->getCallPreservedMask(MF, Info.CallConv); + } + if (Info.IsVarArg && Info.IsMustTailCall) { // Now we know what's being passed to the function. Add uses to the call for // the forwarded registers that we *aren't* passing as parameters. This will @@ -979,14 +1000,8 @@ MIB.add(Info.Callee); // Tell the call which registers are clobbered. - auto TRI = MF.getSubtarget().getRegisterInfo(); - const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv); - if (MF.getSubtarget().hasCustomCallingConv()) - TRI->UpdateCustomCallPreservedMask(MF, &Mask); - MIB.addRegMask(Mask); - - if (TRI->isAnyArgRegReserved(MF)) - TRI->emitReservedArgRegCallError(MF); + const uint32_t *Mask; + const auto *TRI = MF.getSubtarget().getRegisterInfo(); // Do the actual argument marshalling. OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed, @@ -994,6 +1009,25 @@ if (!handleAssignments(MIRBuilder, OutArgs, Handler)) return false; + bool UsingReturnedArg = !OutArgs.empty() && OutArgs[0].Flags[0].isReturned(); + if (UsingReturnedArg) { + // For 'this' returns, use the X0-preserving mask if applicable + Mask = TRI->getThisReturnPreservedMask(MF, Info.CallConv); + if (!Mask) { + OutArgs[0].Flags[0].setReturned(false); + Mask = TRI->getCallPreservedMask(MF, Info.CallConv); + } + } else { + Mask = TRI->getCallPreservedMask(MF, Info.CallConv); + } + + if (MF.getSubtarget().hasCustomCallingConv()) + TRI->UpdateCustomCallPreservedMask(MF, &Mask); + MIB.addRegMask(Mask); + + if (TRI->isAnyArgRegReserved(MF)) + TRI->emitReservedArgRegCallError(MF); + // Now we can add the actual call instruction to the correct basic block. MIRBuilder.insertInstr(MIB); @@ -1011,7 +1045,12 @@ if (!Info.OrigRet.Ty->isVoidTy()) { CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv); CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn); - if (!handleAssignments(MIRBuilder, InArgs, Handler)) + ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB, + RetAssignFn); + if (!handleAssignments( + MIRBuilder, InArgs, UsingReturnedArg ? ReturnedArgHandler : Handler, + [](EVT VT) { return VT.getSizeInBits() == 64; }, + UsingReturnedArg ? OutArgs[0].Regs[0] : Register())) return false; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll @@ -788,8 +788,8 @@ ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x1 = COPY [[LOAD]](p0) - ; CHECK: BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0 - ; CHECK: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1 + ; CHECK: [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY]](p0) ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK: G_BR %bb.59 ; CHECK: bb.57.bb62: @@ -797,8 +797,8 @@ ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x1 = COPY [[COPY2]](p0) - ; CHECK: BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0 - ; CHECK: [[COPY4:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1 + ; CHECK: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0) ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK: G_BR %bb.59 ; CHECK: bb.58.bb64: @@ -812,8 +812,8 @@ ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x1 = COPY [[COPY5]](p0) - ; CHECK: BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0 - ; CHECK: [[COPY6:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1 + ; CHECK: [[COPY6:%[0-9]+]]:_(p0) = COPY [[COPY]](p0) ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK: bb.59.bb68: ; CHECK: RET_ReallyLR diff --git a/llvm/test/CodeGen/AArch64/arm64-this-return.ll b/llvm/test/CodeGen/AArch64/arm64-this-return.ll --- a/llvm/test/CodeGen/AArch64/arm64-this-return.ll +++ b/llvm/test/CodeGen/AArch64/arm64-this-return.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s +; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=1 | FileCheck %s %struct.A = type { i8 } %struct.B = type { i32 }