diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -3297,7 +3297,7 @@ } // Mask setting all 0s or 1s -multiclass avx512_mask_setop { +multiclass avx512_mask_setop { let Predicates = [HasAVX512] in let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1, SchedRW = [WriteZero] in @@ -3305,14 +3305,14 @@ [(set KRC:$dst, (VT Val))]>; } -multiclass avx512_mask_setop_w { +multiclass avx512_mask_setop_w { defm W : avx512_mask_setop; defm D : avx512_mask_setop; defm Q : avx512_mask_setop; } -defm KSET0 : avx512_mask_setop_w; -defm KSET1 : avx512_mask_setop_w; +defm KSET0 : avx512_mask_setop_w<(immAllZerosV)>; +defm KSET1 : avx512_mask_setop_w<(immAllOnesV)>; // With AVX-512 only, 8-bit mask is promoted to 16-bit mask. let Predicates = [HasAVX512] in { @@ -5300,7 +5300,7 @@ //===----------------------------------------------------------------------===// multiclass avx512_fp_scalar opc, string OpcodeStr,X86VectorVTInfo _, - SDNode OpNode, SDNode VecNode, + PatFrags OpNode, SDNode VecNode, X86FoldableSchedWrite sched, bit IsCommutable> { let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rr_Int : AVX512_maskable_scalar opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_binop_s_round opc, string OpcodeStr, PatFrags OpNode, SDNode VecNode, SDNode RndNode, X86SchedWriteSizes sched, bit IsCommutable> { defm SSZ : avx512_fp_scalar opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_213_rm opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _, string Suff> { let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0, @@ -6473,7 +6473,7 @@ AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; } -multiclass avx512_fma3p_213_common opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_213_common opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched, AVX512VLVectorVTInfo _, string Suff> { @@ -6494,7 +6494,7 @@ } } -multiclass avx512_fma3p_213_f opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_213_f opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd> { defm PS : avx512_fma3p_213_common; -multiclass avx512_fma3p_231_rm opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_231_rm opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _, string Suff> { let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0, @@ -6564,7 +6564,7 @@ 1, 1>, AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; } -multiclass avx512_fma3p_231_common opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_231_common opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched, AVX512VLVectorVTInfo _, string Suff> { @@ -6585,7 +6585,7 @@ } } -multiclass avx512_fma3p_231_f opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_231_f opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd > { defm PS : avx512_fma3p_231_common; -multiclass avx512_fma3p_132_rm opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_132_rm opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _, string Suff> { let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0, @@ -6656,7 +6656,7 @@ 1, 1>, AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[sched]>; } -multiclass avx512_fma3p_132_common opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_132_common opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched, AVX512VLVectorVTInfo _, string Suff> { @@ -6677,7 +6677,7 @@ } } -multiclass avx512_fma3p_132_f opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_fma3p_132_f opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd > { defm PS : avx512_fma3p_132_common opc213, bits<8> opc231, bits<8> opc132, - string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, + string OpcodeStr, SDPatternOperator OpNode, SDNode OpNodeRnd, X86VectorVTInfo _, string SUFF> { let ExeDomain = _.ExeDomain in { defm NAME#213#SUFF#Z: avx512_fma3s_common opc213, bits<8> opc231, bits<8> opc132, - string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd> { + string OpcodeStr, SDPatternOperator OpNode, SDNode OpNodeRnd> { let Predicates = [HasAVX512] in { defm NAME : avx512_fma3s_all, @@ -6795,7 +6795,7 @@ defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86any_Fnmadd, X86FnmaddRnd>; defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86any_Fnmsub, X86FnmsubRnd>; -multiclass avx512_scalar_fma_patterns { @@ -7408,7 +7408,7 @@ // Convert float/double to signed/unsigned int 32/64 with truncation multiclass avx512_cvt_s_all opc, string asm, X86VectorVTInfo _SrcRC, - X86VectorVTInfo _DstRC, SDNode OpNode, + X86VectorVTInfo _DstRC, PatFrags OpNode, SDNode OpNodeInt, SDNode OpNodeSAE, X86FoldableSchedWrite sched, string aliasStr>{ let Predicates = [HasAVX512], ExeDomain = _SrcRC.ExeDomain in { @@ -7595,7 +7595,7 @@ //===----------------------------------------------------------------------===// multiclass avx512_vcvt_fp opc, string OpcodeStr, X86VectorVTInfo _, - X86VectorVTInfo _Src, SDNode OpNode, SDNode MaskOpNode, + X86VectorVTInfo _Src, SDPatternOperator OpNode, SDPatternOperator MaskOpNode, X86FoldableSchedWrite sched, string Broadcast = _.BroadcastStr, string Alias = "", X86MemOperand MemOp = _Src.MemOp, @@ -7665,7 +7665,7 @@ // Conversion with rounding control (RC) multiclass avx512_vcvt_fp_rc opc, string OpcodeStr, X86VectorVTInfo _, - X86VectorVTInfo _Src, SDNode OpNodeRnd, + X86VectorVTInfo _Src, SDPatternOperator OpNodeRnd, X86FoldableSchedWrite sched> { let Uses = [MXCSR] in defm rrb : AVX512_maskable opc, string OpcodeStr, X86VectorVTInfo _, - X86VectorVTInfo _Src, SDNode OpNode, - SDNode MaskOpNode, + X86VectorVTInfo _Src, SDPatternOperator OpNode, + SDNode MaskOpNode, X86FoldableSchedWrite sched, string Broadcast = _.BroadcastStr, string Alias = "", X86MemOperand MemOp = _Src.MemOp, @@ -7802,8 +7802,8 @@ // Convert Signed/Unsigned Doubleword to Double let Uses = [], mayRaiseFPException = 0 in -multiclass avx512_cvtdq2pd opc, string OpcodeStr, SDNode OpNode, - SDNode MaskOpNode, SDNode OpNode128, +multiclass avx512_cvtdq2pd opc, string OpcodeStr, SDPatternOperator OpNode, + SDNode MaskOpNode, PatFrags OpNode128, SDNode MaskOpNode128, X86SchedWriteWidths sched> { // No rounding in this op @@ -7828,7 +7828,7 @@ } // Convert Signed/Unsigned Doubleword to Float -multiclass avx512_cvtdq2ps opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_cvtdq2ps opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched> { let Predicates = [HasAVX512] in @@ -7846,7 +7846,7 @@ } // Convert Float to Signed/Unsigned Doubleword with truncation -multiclass avx512_cvttps2dq opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_cvttps2dq opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched> { let Predicates = [HasAVX512] in { @@ -7882,7 +7882,7 @@ } // Convert Double to Signed/Unsigned Doubleword with truncation -multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched> { let Predicates = [HasAVX512] in { @@ -8028,7 +8028,7 @@ } // Convert Double to Signed/Unsigned Quardword with truncation -multiclass avx512_cvttpd2qq opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_cvttpd2qq opc, string OpcodeStr, PatFrags OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched> { let Predicates = [HasDQI] in { @@ -8046,7 +8046,7 @@ } // Convert Signed/Unsigned Quardword to Double -multiclass avx512_cvtqq2pd opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_cvtqq2pd opc, string OpcodeStr, PatFrags OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched> { let Predicates = [HasDQI] in { @@ -8091,7 +8091,7 @@ } // Convert Float to Signed/Unsigned Quardword with truncation -multiclass avx512_cvttps2qq opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_cvttps2qq opc, string OpcodeStr, PatFrags OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched> { let Predicates = [HasDQI] in { @@ -8118,7 +8118,7 @@ } // Convert Signed/Unsigned Quardword to Float -multiclass avx512_cvtqq2ps opc, string OpcodeStr, SDNode OpNode, +multiclass avx512_cvtqq2ps opc, string OpcodeStr, PatFrags OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched> { let Predicates = [HasDQI] in { @@ -10094,7 +10094,8 @@ // op(broadcast(eltVt),imm) //all instruction created with FROUND_CURRENT multiclass avx512_unary_fp_packed_imm opc, string OpcodeStr, - SDNode OpNode, SDNode MaskOpNode, + SDPatternOperator OpNode, + SDPatternOperator MaskOpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { @@ -10139,8 +10140,8 @@ } multiclass avx512_common_unary_fp_sae_packed_imm opc, SDNode OpNode, - SDNode MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched, + AVX512VLVectorVTInfo _, bits<8> opc, SDPatternOperator OpNode, + SDPatternOperator MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched, Predicate prd>{ let Predicates = [prd] in { defm Z : avx512_unary_fp_packed_imm opcPs, bits<8> opcPd, SDNode OpNode, - SDNode MaskOpNode, SDNode OpNodeSAE, + bits<8> opcPs, bits<8> opcPd, SDPatternOperator OpNode, + SDPatternOperator MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched, Predicate prd>{ defm PS : avx512_common_unary_fp_sae_packed_imm, @@ -11563,7 +11564,7 @@ // TODO: Some canonicalization in lowering would simplify the number of // patterns we have to try to match. -multiclass AVX512_scalar_math_fp_patterns { let Predicates = [HasAVX512] in { @@ -11635,7 +11636,7 @@ defm : AVX512_scalar_math_fp_patterns; defm : AVX512_scalar_math_fp_patterns; -multiclass AVX512_scalar_unary_math_patterns { let Predicates = [HasAVX512] in { def : Pat<(_.VT (Move _.VT:$dst, diff --git a/llvm/lib/Target/X86/X86InstrFMA.td b/llvm/lib/Target/X86/X86InstrFMA.td --- a/llvm/lib/Target/X86/X86InstrFMA.td +++ b/llvm/lib/Target/X86/X86InstrFMA.td @@ -35,7 +35,7 @@ multiclass fma3p_rm_213 opc, string OpcodeStr, RegisterClass RC, ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, - SDNode Op, X86FoldableSchedWrite sched> { + SDPatternOperator Op, X86FoldableSchedWrite sched> { def r : FMA3 opc, string OpcodeStr, RegisterClass RC, ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, - SDNode Op, X86FoldableSchedWrite sched> { + SDPatternOperator Op, X86FoldableSchedWrite sched> { let hasSideEffects = 0 in def r : FMA3 opc, string OpcodeStr, RegisterClass RC, ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, - SDNode Op, X86FoldableSchedWrite sched> { + SDPatternOperator Op, X86FoldableSchedWrite sched> { let hasSideEffects = 0 in def r : FMA3 opc132, bits<8> opc213, bits<8> opc231, string OpcodeStr, string PackTy, string Suff, PatFrag MemFrag128, PatFrag MemFrag256, - SDNode Op, ValueType OpTy128, ValueType OpTy256, + SDPatternOperator Op, ValueType OpTy128, ValueType OpTy256, X86SchedWriteWidths sched> { defm NAME#213#Suff : fma3p_rm_213; @@ -241,7 +241,7 @@ hasSideEffects = 0, Uses = [MXCSR], mayRaiseFPException = 1 in multiclass fma3s_forms opc132, bits<8> opc213, bits<8> opc231, string OpStr, string PackTy, string Suff, - SDNode OpNode, RegisterClass RC, + SDPatternOperator OpNode, RegisterClass RC, X86MemOperand x86memop, X86FoldableSchedWrite sched> { defm NAME#213#Suff : fma3s_rm_213; @@ -305,7 +305,7 @@ } multiclass fma3s opc132, bits<8> opc213, bits<8> opc231, - string OpStr, SDNode OpNode, X86FoldableSchedWrite sched> { + string OpStr, SDPatternOperator OpNode, X86FoldableSchedWrite sched> { let ExeDomain = SSEPackedSingle in defm NAME : fma3s_forms, @@ -329,7 +329,7 @@ defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86any_Fnmsub, SchedWriteFMA.Scl>, VEX_LIG; -multiclass scalar_fma_patterns { let Predicates = [HasFMA, NoAVX512] in { @@ -388,7 +388,7 @@ let Uses = [MXCSR], mayRaiseFPException = 1 in multiclass fma4s opc, string OpcodeStr, RegisterClass RC, - X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, + X86MemOperand x86memop, ValueType OpVT, SDPatternOperator OpNode, PatFrag mem_frag, X86FoldableSchedWrite sched> { let isCommutable = 1 in def rr : FMA4S opc, string OpcodeStr, SDNode OpNode, +multiclass fma4p opc, string OpcodeStr, SDPatternOperator OpNode, ValueType OpVT128, ValueType OpVT256, PatFrag ld_frag128, PatFrag ld_frag256, X86SchedWriteWidths sched> { @@ -602,7 +602,7 @@ loadv2f64, loadv4f64, SchedWriteFMA>; } -multiclass scalar_fma4_patterns { let Predicates = [HasFMA4] in { diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td --- a/llvm/lib/Target/X86/X86InstrFPStack.td +++ b/llvm/lib/Target/X86/X86InstrFPStack.td @@ -168,7 +168,7 @@ FpI_, Requires<[FPStackf64]>; // Factoring for arithmetic. -multiclass FPBinary_rr { +multiclass FPBinary_rr { // Register op register -> register // These are separated out because they have no reversed form. def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, @@ -181,7 +181,7 @@ // The FopST0 series are not included here because of the irregularities // in where the 'r' goes in assembly output. // These instructions cannot address 80-bit memory. -multiclass FPBinary { // ST(0) = ST(0) + [mem] def _Fp32m : FpIf32<(outs RFP32:$dst), @@ -343,7 +343,7 @@ } // SchedRW // Unary operations. -multiclass FPUnary { +multiclass FPUnary { def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src))]>; def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2587,7 +2587,7 @@ } multiclass bmi_bzhi opc, string mnemonic, RegisterClass RC, - X86MemOperand x86memop, Intrinsic Int, + X86MemOperand x86memop, SDNode Int, PatFrag ld_frag, X86FoldableSchedWrite Sched> { def rr : I opc, string OpcodeStr, SDNode OpNode, +multiclass sse12_fp_scalar opc, string OpcodeStr, SDPatternOperator OpNode, RegisterClass RC, X86MemOperand x86memop, Domain d, X86FoldableSchedWrite sched, bit Is2Addr = 1> { @@ -63,7 +63,7 @@ } /// sse12_fp_packed - SSE 1 & 2 packed instructions class -multiclass sse12_fp_packed opc, string OpcodeStr, SDNode OpNode, +multiclass sse12_fp_packed opc, string OpcodeStr, SDPatternOperator OpNode, RegisterClass RC, ValueType vt, X86MemOperand x86memop, PatFrag mem_frag, Domain d, X86FoldableSchedWrite sched, @@ -616,7 +616,7 @@ // SSE 1 & 2 - Move Low packed FP Instructions //===----------------------------------------------------------------------===// -multiclass sse12_mov_hilo_packed_baseopc, SDNode pdnode, +multiclass sse12_mov_hilo_packed_baseopc, SDPatternOperator pdnode, string base_opc, string asm_opr> { // No pattern as they need be special cased between high and low. let hasSideEffects = 0, mayLoad = 1 in @@ -811,7 +811,7 @@ //===----------------------------------------------------------------------===// multiclass sse12_cvt_s opc, RegisterClass SrcRC, RegisterClass DstRC, - SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag, + SDPatternOperator OpNode, X86MemOperand x86memop, PatFrag ld_frag, string asm, string mem, X86FoldableSchedWrite sched, Domain d, SchedRead Int2Fpu = ReadDefault> { @@ -1837,7 +1837,7 @@ } // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS -multiclass sse12_ord_cmp opc, RegisterClass RC, SDNode OpNode, +multiclass sse12_ord_cmp opc, RegisterClass RC, SDPatternOperator OpNode, ValueType vt, X86MemOperand x86memop, PatFrag ld_frag, string OpcodeStr, Domain d, X86FoldableSchedWrite sched = WriteFComX> { @@ -2589,7 +2589,7 @@ /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those /// classes below multiclass basic_sse12_fp_binop_p opc, string OpcodeStr, - SDNode OpNode, X86SchedWriteSizes sched> { + SDPatternOperator OpNode, X86SchedWriteSizes sched> { let Uses = [MXCSR], mayRaiseFPException = 1 in { let Predicates = [HasAVX, NoVLX] in { defm V#NAME#PS : sse12_fp_packed opc, string OpcodeStr, SDNode OpNode, +multiclass basic_sse12_fp_binop_s opc, string OpcodeStr, SDPatternOperator OpNode, X86SchedWriteSizes sched> { let Uses = [MXCSR], mayRaiseFPException = 1 in { defm V#NAME#SS : sse12_fp_scalar { +multiclass scalar_math_patterns { let Predicates = [BasePredicate] in { // extracted scalar math op with insert via movss/movsd def : Pat<(VT (Move (VT VR128:$dst), @@ -2791,7 +2791,7 @@ /// the HW instructions are 2 operand / destructive. multiclass sse_fp_unop_s opc, string OpcodeStr, RegisterClass RC, ValueType ScalarVT, X86MemOperand x86memop, - Operand intmemop, SDNode OpNode, Domain d, + Operand intmemop, SDPatternOperator OpNode, Domain d, X86FoldableSchedWrite sched, Predicate target> { let isCodeGenOnly = 1, hasSideEffects = 0 in { def r : I opc, string OpcodeStr, RegisterClass RC, ValueType ScalarVT, X86MemOperand x86memop, - Operand intmemop, SDNode OpNode, Domain d, + Operand intmemop, SDPatternOperator OpNode, Domain d, X86FoldableSchedWrite sched, Predicate target> { let isCodeGenOnly = 1, hasSideEffects = 0 in { def r : I opc, string OpcodeStr, SDNode OpNode, +multiclass sse1_fp_unop_p opc, string OpcodeStr, SDPatternOperator OpNode, X86SchedWriteWidths sched, list prds> { let Predicates = prds in { def V#NAME#PSr : PSI opc, string OpcodeStr, - SDNode OpNode, X86SchedWriteWidths sched> { + SDPatternOperator OpNode, X86SchedWriteWidths sched> { let Predicates = [HasAVX, NoVLX] in { def V#NAME#PDr : PDI opc, string OpcodeStr, SDNode OpNode, +multiclass sse1_fp_unop_s opc, string OpcodeStr, SDPatternOperator OpNode, X86SchedWriteWidths sched, Predicate AVXTarget> { defm SS : sse_fp_unop_s, XS; @@ -2992,7 +2992,7 @@ XS, VEX_4V, VEX_LIG, VEX_WIG; } -multiclass sse2_fp_unop_s opc, string OpcodeStr, SDNode OpNode, +multiclass sse2_fp_unop_s opc, string OpcodeStr, SDPatternOperator OpNode, X86SchedWriteWidths sched, Predicate AVXTarget> { defm SD : sse_fp_unop_s, XD; @@ -3018,7 +3018,7 @@ // There is no f64 version of the reciprocal approximation instructions. -multiclass scalar_unary_math_patterns { let Predicates = [BasePredicate] in { def : Pat<(VT (Move VT:$dst, (scalar_to_vector @@ -5386,7 +5386,7 @@ multiclass sse41_fp_unop_p opc, string OpcodeStr, X86MemOperand x86memop, RegisterClass RC, - ValueType VT, PatFrag mem_frag, SDNode OpNode, + ValueType VT, PatFrag mem_frag, PatFrags OpNode, X86FoldableSchedWrite sched> { // Intrinsic operation, reg. // Vector intrinsic operation, reg