diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8368,6 +8368,10 @@
         TargetLowering::Legal)
       return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
                          N0.getOperand(0), DAG.getValueType(ExtVT));
+    // Even if we can't convert to sext_inreg, we might be able to remove
+    // this shift pair if the input is already sign extended.
+    if (DAG.ComputeNumSignBits(N0.getOperand(0)) > N1C->getZExtValue())
+      return N0.getOperand(0);
   }
 
   // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -89,9 +89,8 @@
   GORCI,
   GORCIW,
   // Vector Extension
-  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT
-  // sign extended from the vector element size. NOTE: The result size will
-  // never be less than the vector element size.
+  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
+  // extended from the vector element size.
   VMV_X_S,
   // Splats an i64 scalar to a vector type (with element type i64) where the
   // scalar is a sign-extended i32.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1480,23 +1480,32 @@
 }
 
 // Custom-lower EXTRACT_VECTOR_ELT operations to slide the vector down, then
-// extract the first element: (extractelt (slidedown vec, idx), 0). This is
-// done to maintain partity with the legalization of RV32 vXi64 legalization.
+// extract the first element: (extractelt (slidedown vec, idx), 0). For integer
+// types this is done using VMV_X_S to allow us to glean information about the
+// sign bits of the result.
 SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDLoc DL(Op);
   SDValue Idx = Op.getOperand(1);
-  if (isNullConstant(Idx))
-    return Op;
-
   SDValue Vec = Op.getOperand(0);
   EVT EltVT = Op.getValueType();
   EVT VecVT = Vec.getValueType();
-  SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT,
-                                  DAG.getUNDEF(VecVT), Vec, Idx);
+  MVT XLenVT = Subtarget.getXLenVT();
+
+  // If the index is 0, the vector is already in the right position.
+  if (!isNullConstant(Idx)) {
+    Vec = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT, DAG.getUNDEF(VecVT), Vec,
+                      Idx);
+  }
+
+  if (!EltVT.isInteger()) {
+    // Floating-point extracts are handled in TableGen.
+    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec,
+                       DAG.getConstant(0, DL, XLenVT));
+  }
 
-  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Slidedown,
-                     DAG.getConstant(0, DL, Subtarget.getXLenVT()));
+  SDValue Elt0 = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Vec);
+  return DAG.getNode(ISD::TRUNCATE, DL, EltVT, Elt0);
 }
 
 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -708,53 +708,47 @@
 // Vector Element Inserts/Extracts
 //===----------------------------------------------------------------------===//
 
-// The built-in TableGen 'extractelt' and 'insertelt' nodes must return the
-// same type as the vector element type. On RISC-V, XLenVT is the only legal
-// integer type, so for integer inserts/extracts we use a custom node which
-// returns XLenVT.
+// The built-in TableGen 'insertelt' node must return the same type as the
+// vector element type. On RISC-V, XLenVT is the only legal integer type, so
+// for integer inserts we use a custom node which inserts an XLenVT-typed
+// value.
 def riscv_insert_vector_elt
     : SDNode<"ISD::INSERT_VECTOR_ELT",
              SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, XLenVT>,
                                   SDTCisPtrTy<3>]>, []>;
-def riscv_extract_vector_elt
-    : SDNode<"ISD::EXTRACT_VECTOR_ELT",
-             SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisPtrTy<2>]>, []>;
-
-multiclass VPatInsertExtractElt_XI_Idx<bit IsFloat> {
-  defvar vtilist = !if(IsFloat, AllFloatVectors, AllIntegerVectors);
-  defvar insertelt_node = !if(IsFloat, insertelt, riscv_insert_vector_elt);
-  defvar extractelt_node = !if(IsFloat, extractelt, riscv_extract_vector_elt);
-  foreach vti = vtilist in {
-    defvar MX = vti.LMul.MX;
-    defvar vmv_xf_s_inst = !cast<Instruction>(!strconcat("PseudoV",
-                                                         !if(IsFloat, "F", ""),
-                                                         "MV_",
-                                                         vti.ScalarSuffix,
-                                                         "_S_", MX));
-    defvar vmv_s_xf_inst = !cast<Instruction>(!strconcat("PseudoV",
-                                                         !if(IsFloat, "F", ""),
-                                                         "MV_S_",
-                                                         vti.ScalarSuffix,
-                                                         "_", MX));
-    // Only pattern-match insert/extract-element operations where the index is
-    // 0. Any other index will have been custom-lowered to slide the vector
-    // correctly into place (and, in the case of insert, slide it back again
-    // afterwards).
-    def : Pat<(vti.Scalar (extractelt_node (vti.Vector vti.RegClass:$rs2), 0)),
-              (vmv_xf_s_inst vti.RegClass:$rs2, vti.SEW)>;
-
-    def : Pat<(vti.Vector (insertelt_node (vti.Vector vti.RegClass:$merge),
-                                          vti.ScalarRegClass:$rs1, 0)),
-              (vmv_s_xf_inst vti.RegClass:$merge,
-                      (vti.Scalar vti.ScalarRegClass:$rs1),
-                      vti.AVL, vti.SEW)>;
-  }
-}
 
 let Predicates = [HasStdExtV] in
-defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/0>;
+foreach vti = AllIntegerVectors in {
+  def : Pat<(vti.Vector (riscv_insert_vector_elt (vti.Vector vti.RegClass:$merge),
+                                                 vti.ScalarRegClass:$rs1, 0)),
+            (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
+                vti.RegClass:$merge,
+                (vti.Scalar vti.ScalarRegClass:$rs1),
+                vti.AVL, vti.SEW)>;
+}
+
 let Predicates = [HasStdExtV, HasStdExtF] in
-defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/1>;
+foreach vti = AllFloatVectors in {
+  defvar MX = vti.LMul.MX;
+  defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",
+                                                       vti.ScalarSuffix,
+                                                       "_S_", MX));
+  defvar vmv_s_f_inst = !cast<Instruction>(!strconcat("PseudoVFMV_S_",
+                                                       vti.ScalarSuffix,
+                                                       "_", vti.LMul.MX));
+  // Only pattern-match insert/extract-element operations where the index is
+  // 0. Any other index will have been custom-lowered to slide the vector
+  // correctly into place (and, in the case of insert, slide it back again
+  // afterwards).
+  def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)),
+            (vmv_f_s_inst vti.RegClass:$rs2, vti.SEW)>;
+
+  def : Pat<(vti.Vector (insertelt (vti.Vector vti.RegClass:$merge),
+                                   vti.ScalarRegClass:$rs1, 0)),
+            (vmv_s_f_inst vti.RegClass:$merge,
+                    (vti.Scalar vti.ScalarRegClass:$rs1),
+                    vti.AVL, vti.SEW)>;
+}
 
 //===----------------------------------------------------------------------===//
 // Miscellaneous RISCVISD SDNodes
diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll
--- a/llvm/test/CodeGen/Mips/atomic.ll
+++ b/llvm/test/CodeGen/Mips/atomic.ll
@@ -4311,19 +4311,19 @@
 ; MIPS32-NEXT:    addu $1, $2, $25
 ; MIPS32-NEXT:    lw $1, %got(y)($1)
 ; MIPS32-NEXT:    addiu $2, $zero, -4
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    and $3, $1, $2
 ; MIPS32-NEXT:    andi $1, $1, 3
-; MIPS32-NEXT:    sll $3, $1, 3
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    sllv $6, $1, $3
+; MIPS32-NEXT:    sll $1, $1, 3
+; MIPS32-NEXT:    ori $2, $zero, 255
+; MIPS32-NEXT:    sllv $6, $2, $1
 ; MIPS32-NEXT:    nor $7, $zero, $6
-; MIPS32-NEXT:    andi $1, $4, 255
-; MIPS32-NEXT:    sllv $4, $1, $3
-; MIPS32-NEXT:    andi $1, $5, 255
-; MIPS32-NEXT:    sllv $5, $1, $3
+; MIPS32-NEXT:    andi $2, $4, 255
+; MIPS32-NEXT:    sllv $4, $2, $1
+; MIPS32-NEXT:    andi $2, $5, 255
+; MIPS32-NEXT:    sllv $5, $2, $1
 ; MIPS32-NEXT:  $BB12_1: # %entry
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32-NEXT:    ll $8, 0($2)
+; MIPS32-NEXT:    ll $8, 0($3)
 ; MIPS32-NEXT:    and $9, $8, $6
 ; MIPS32-NEXT:    bne $9, $4, $BB12_3
 ; MIPS32-NEXT:    nop
@@ -4331,17 +4331,16 @@
 ; MIPS32-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; MIPS32-NEXT:    and $8, $8, $7
 ; MIPS32-NEXT:    or $8, $8, $5
-; MIPS32-NEXT:    sc $8, 0($2)
+; MIPS32-NEXT:    sc $8, 0($3)
 ; MIPS32-NEXT:    beqz $8, $BB12_1
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB12_3: # %entry
-; MIPS32-NEXT:    srlv $1, $9, $3
-; MIPS32-NEXT:    sll $1, $1, 24
-; MIPS32-NEXT:    sra $1, $1, 24
+; MIPS32-NEXT:    srlv $2, $9, $1
+; MIPS32-NEXT:    sll $2, $2, 24
+; MIPS32-NEXT:    sra $2, $2, 24
 ; MIPS32-NEXT:  # %bb.4: # %entry
-; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    sra $2, $1, 24
+; MIPS32-NEXT:    nop
 ;
 ; MIPS32O0-LABEL: AtomicCmpSwap8:
 ; MIPS32O0:       # %bb.0: # %entry
@@ -4511,19 +4510,19 @@
 ; MIPS4-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap8)))
 ; MIPS4-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS4-NEXT:    daddiu $2, $zero, -4
-; MIPS4-NEXT:    and $2, $1, $2
+; MIPS4-NEXT:    and $3, $1, $2
 ; MIPS4-NEXT:    andi $1, $1, 3
-; MIPS4-NEXT:    sll $3, $1, 3
-; MIPS4-NEXT:    ori $1, $zero, 255
-; MIPS4-NEXT:    sllv $6, $1, $3
+; MIPS4-NEXT:    sll $1, $1, 3
+; MIPS4-NEXT:    ori $2, $zero, 255
+; MIPS4-NEXT:    sllv $6, $2, $1
 ; MIPS4-NEXT:    nor $7, $zero, $6
-; MIPS4-NEXT:    andi $1, $4, 255
-; MIPS4-NEXT:    sllv $4, $1, $3
-; MIPS4-NEXT:    andi $1, $5, 255
-; MIPS4-NEXT:    sllv $5, $1, $3
+; MIPS4-NEXT:    andi $2, $4, 255
+; MIPS4-NEXT:    sllv $4, $2, $1
+; MIPS4-NEXT:    andi $2, $5, 255
+; MIPS4-NEXT:    sllv $5, $2, $1
 ; MIPS4-NEXT:  .LBB12_1: # %entry
 ; MIPS4-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS4-NEXT:    ll $8, 0($2)
+; MIPS4-NEXT:    ll $8, 0($3)
 ; MIPS4-NEXT:    and $9, $8, $6
 ; MIPS4-NEXT:    bne $9, $4, .LBB12_3
 ; MIPS4-NEXT:    nop
@@ -4531,17 +4530,16 @@
 ; MIPS4-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; MIPS4-NEXT:    and $8, $8, $7
 ; MIPS4-NEXT:    or $8, $8, $5
-; MIPS4-NEXT:    sc $8, 0($2)
+; MIPS4-NEXT:    sc $8, 0($3)
 ; MIPS4-NEXT:    beqz $8, .LBB12_1
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  .LBB12_3: # %entry
-; MIPS4-NEXT:    srlv $1, $9, $3
-; MIPS4-NEXT:    sll $1, $1, 24
-; MIPS4-NEXT:    sra $1, $1, 24
+; MIPS4-NEXT:    srlv $2, $9, $1
+; MIPS4-NEXT:    sll $2, $2, 24
+; MIPS4-NEXT:    sra $2, $2, 24
 ; MIPS4-NEXT:  # %bb.4: # %entry
-; MIPS4-NEXT:    sll $1, $1, 24
 ; MIPS4-NEXT:    jr $ra
-; MIPS4-NEXT:    sra $2, $1, 24
+; MIPS4-NEXT:    nop
 ;
 ; MIPS64-LABEL: AtomicCmpSwap8:
 ; MIPS64:       # %bb.0: # %entry
@@ -4550,19 +4548,19 @@
 ; MIPS64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap8)))
 ; MIPS64-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64-NEXT:    daddiu $2, $zero, -4
-; MIPS64-NEXT:    and $2, $1, $2
+; MIPS64-NEXT:    and $3, $1, $2
 ; MIPS64-NEXT:    andi $1, $1, 3
-; MIPS64-NEXT:    sll $3, $1, 3
-; MIPS64-NEXT:    ori $1, $zero, 255
-; MIPS64-NEXT:    sllv $6, $1, $3
+; MIPS64-NEXT:    sll $1, $1, 3
+; MIPS64-NEXT:    ori $2, $zero, 255
+; MIPS64-NEXT:    sllv $6, $2, $1
 ; MIPS64-NEXT:    nor $7, $zero, $6
-; MIPS64-NEXT:    andi $1, $4, 255
-; MIPS64-NEXT:    sllv $4, $1, $3
-; MIPS64-NEXT:    andi $1, $5, 255
-; MIPS64-NEXT:    sllv $5, $1, $3
+; MIPS64-NEXT:    andi $2, $4, 255
+; MIPS64-NEXT:    sllv $4, $2, $1
+; MIPS64-NEXT:    andi $2, $5, 255
+; MIPS64-NEXT:    sllv $5, $2, $1
 ; MIPS64-NEXT:  .LBB12_1: # %entry
 ; MIPS64-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64-NEXT:    ll $8, 0($2)
+; MIPS64-NEXT:    ll $8, 0($3)
 ; MIPS64-NEXT:    and $9, $8, $6
 ; MIPS64-NEXT:    bne $9, $4, .LBB12_3
 ; MIPS64-NEXT:    nop
@@ -4570,17 +4568,16 @@
 ; MIPS64-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; MIPS64-NEXT:    and $8, $8, $7
 ; MIPS64-NEXT:    or $8, $8, $5
-; MIPS64-NEXT:    sc $8, 0($2)
+; MIPS64-NEXT:    sc $8, 0($3)
 ; MIPS64-NEXT:    beqz $8, .LBB12_1
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  .LBB12_3: # %entry
-; MIPS64-NEXT:    srlv $1, $9, $3
-; MIPS64-NEXT:    sll $1, $1, 24
-; MIPS64-NEXT:    sra $1, $1, 24
+; MIPS64-NEXT:    srlv $2, $9, $1
+; MIPS64-NEXT:    sll $2, $2, 24
+; MIPS64-NEXT:    sra $2, $2, 24
 ; MIPS64-NEXT:  # %bb.4: # %entry
-; MIPS64-NEXT:    sll $1, $1, 24
 ; MIPS64-NEXT:    jr $ra
-; MIPS64-NEXT:    sra $2, $1, 24
+; MIPS64-NEXT:    nop
 ;
 ; MIPS64R2-LABEL: AtomicCmpSwap8:
 ; MIPS64R2:       # %bb.0: # %entry
@@ -4737,19 +4734,19 @@
 ; O1-NEXT:    addu $1, $2, $25
 ; O1-NEXT:    lw $1, %got(y)($1)
 ; O1-NEXT:    addiu $2, $zero, -4
-; O1-NEXT:    and $2, $1, $2
+; O1-NEXT:    and $3, $1, $2
 ; O1-NEXT:    andi $1, $1, 3
-; O1-NEXT:    sll $3, $1, 3
-; O1-NEXT:    ori $1, $zero, 255
-; O1-NEXT:    sllv $6, $1, $3
+; O1-NEXT:    sll $1, $1, 3
+; O1-NEXT:    ori $2, $zero, 255
+; O1-NEXT:    sllv $6, $2, $1
 ; O1-NEXT:    nor $7, $zero, $6
-; O1-NEXT:    andi $1, $4, 255
-; O1-NEXT:    sllv $4, $1, $3
-; O1-NEXT:    andi $1, $5, 255
-; O1-NEXT:    sllv $5, $1, $3
+; O1-NEXT:    andi $2, $4, 255
+; O1-NEXT:    sllv $4, $2, $1
+; O1-NEXT:    andi $2, $5, 255
+; O1-NEXT:    sllv $5, $2, $1
 ; O1-NEXT:  $BB12_1: # %entry
 ; O1-NEXT:    # =>This Inner Loop Header: Depth=1
-; O1-NEXT:    ll $8, 0($2)
+; O1-NEXT:    ll $8, 0($3)
 ; O1-NEXT:    and $9, $8, $6
 ; O1-NEXT:    bne $9, $4, $BB12_3
 ; O1-NEXT:    nop
@@ -4757,17 +4754,16 @@
 ; O1-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; O1-NEXT:    and $8, $8, $7
 ; O1-NEXT:    or $8, $8, $5
-; O1-NEXT:    sc $8, 0($2)
+; O1-NEXT:    sc $8, 0($3)
 ; O1-NEXT:    beqz $8, $BB12_1
 ; O1-NEXT:    nop
 ; O1-NEXT:  $BB12_3: # %entry
-; O1-NEXT:    srlv $1, $9, $3
-; O1-NEXT:    sll $1, $1, 24
-; O1-NEXT:    sra $1, $1, 24
+; O1-NEXT:    srlv $2, $9, $1
+; O1-NEXT:    sll $2, $2, 24
+; O1-NEXT:    sra $2, $2, 24
 ; O1-NEXT:  # %bb.4: # %entry
-; O1-NEXT:    sll $1, $1, 24
 ; O1-NEXT:    jr $ra
-; O1-NEXT:    sra $2, $1, 24
+; O1-NEXT:    nop
 ;
 ; O2-LABEL: AtomicCmpSwap8:
 ; O2:       # %bb.0: # %entry
@@ -4776,19 +4772,19 @@
 ; O2-NEXT:    addu $1, $2, $25
 ; O2-NEXT:    lw $1, %got(y)($1)
 ; O2-NEXT:    addiu $2, $zero, -4
-; O2-NEXT:    and $2, $1, $2
+; O2-NEXT:    and $3, $1, $2
 ; O2-NEXT:    andi $1, $1, 3
-; O2-NEXT:    sll $3, $1, 3
-; O2-NEXT:    ori $1, $zero, 255
-; O2-NEXT:    sllv $6, $1, $3
+; O2-NEXT:    sll $1, $1, 3
+; O2-NEXT:    ori $2, $zero, 255
+; O2-NEXT:    sllv $6, $2, $1
 ; O2-NEXT:    nor $7, $zero, $6
-; O2-NEXT:    andi $1, $4, 255
-; O2-NEXT:    sllv $4, $1, $3
-; O2-NEXT:    andi $1, $5, 255
-; O2-NEXT:    sllv $5, $1, $3
+; O2-NEXT:    andi $2, $4, 255
+; O2-NEXT:    sllv $4, $2, $1
+; O2-NEXT:    andi $2, $5, 255
+; O2-NEXT:    sllv $5, $2, $1
 ; O2-NEXT:  $BB12_1: # %entry
 ; O2-NEXT:    # =>This Inner Loop Header: Depth=1
-; O2-NEXT:    ll $8, 0($2)
+; O2-NEXT:    ll $8, 0($3)
 ; O2-NEXT:    and $9, $8, $6
 ; O2-NEXT:    bne $9, $4, $BB12_3
 ; O2-NEXT:    nop
@@ -4796,17 +4792,16 @@
 ; O2-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; O2-NEXT:    and $8, $8, $7
 ; O2-NEXT:    or $8, $8, $5
-; O2-NEXT:    sc $8, 0($2)
+; O2-NEXT:    sc $8, 0($3)
 ; O2-NEXT:    beqz $8, $BB12_1
 ; O2-NEXT:    nop
 ; O2-NEXT:  $BB12_3: # %entry
-; O2-NEXT:    srlv $1, $9, $3
-; O2-NEXT:    sll $1, $1, 24
-; O2-NEXT:    sra $1, $1, 24
+; O2-NEXT:    srlv $2, $9, $1
+; O2-NEXT:    sll $2, $2, 24
+; O2-NEXT:    sra $2, $2, 24
 ; O2-NEXT:  # %bb.4: # %entry
-; O2-NEXT:    sll $1, $1, 24
 ; O2-NEXT:    jr $ra
-; O2-NEXT:    sra $2, $1, 24
+; O2-NEXT:    nop
 ;
 ; O3-LABEL: AtomicCmpSwap8:
 ; O3:       # %bb.0: # %entry
@@ -4815,19 +4810,19 @@
 ; O3-NEXT:    addu $1, $2, $25
 ; O3-NEXT:    addiu $2, $zero, -4
 ; O3-NEXT:    lw $1, %got(y)($1)
-; O3-NEXT:    and $2, $1, $2
+; O3-NEXT:    and $3, $1, $2
 ; O3-NEXT:    andi $1, $1, 3
-; O3-NEXT:    sll $3, $1, 3
-; O3-NEXT:    ori $1, $zero, 255
-; O3-NEXT:    sllv $6, $1, $3
-; O3-NEXT:    andi $1, $4, 255
-; O3-NEXT:    sllv $4, $1, $3
-; O3-NEXT:    andi $1, $5, 255
+; O3-NEXT:    ori $2, $zero, 255
+; O3-NEXT:    sll $1, $1, 3
+; O3-NEXT:    sllv $6, $2, $1
+; O3-NEXT:    andi $2, $4, 255
+; O3-NEXT:    sllv $4, $2, $1
+; O3-NEXT:    andi $2, $5, 255
 ; O3-NEXT:    nor $7, $zero, $6
-; O3-NEXT:    sllv $5, $1, $3
+; O3-NEXT:    sllv $5, $2, $1
 ; O3-NEXT:  $BB12_1: # %entry
 ; O3-NEXT:    # =>This Inner Loop Header: Depth=1
-; O3-NEXT:    ll $8, 0($2)
+; O3-NEXT:    ll $8, 0($3)
 ; O3-NEXT:    and $9, $8, $6
 ; O3-NEXT:    bne $9, $4, $BB12_3
 ; O3-NEXT:    nop
@@ -4835,17 +4830,16 @@
 ; O3-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; O3-NEXT:    and $8, $8, $7
 ; O3-NEXT:    or $8, $8, $5
-; O3-NEXT:    sc $8, 0($2)
+; O3-NEXT:    sc $8, 0($3)
 ; O3-NEXT:    beqz $8, $BB12_1
 ; O3-NEXT:    nop
 ; O3-NEXT:  $BB12_3: # %entry
-; O3-NEXT:    srlv $1, $9, $3
-; O3-NEXT:    sll $1, $1, 24
-; O3-NEXT:    sra $1, $1, 24
+; O3-NEXT:    srlv $2, $9, $1
+; O3-NEXT:    sll $2, $2, 24
+; O3-NEXT:    sra $2, $2, 24
 ; O3-NEXT:  # %bb.4: # %entry
-; O3-NEXT:    sll $1, $1, 24
 ; O3-NEXT:    jr $ra
-; O3-NEXT:    sra $2, $1, 24
+; O3-NEXT:    nop
 ;
 ; MIPS32EB-LABEL: AtomicCmpSwap8:
 ; MIPS32EB:       # %bb.0: # %entry
@@ -4854,20 +4848,20 @@
 ; MIPS32EB-NEXT:    addu $1, $2, $25
 ; MIPS32EB-NEXT:    lw $1, %got(y)($1)
 ; MIPS32EB-NEXT:    addiu $2, $zero, -4
-; MIPS32EB-NEXT:    and $2, $1, $2
+; MIPS32EB-NEXT:    and $3, $1, $2
 ; MIPS32EB-NEXT:    andi $1, $1, 3
 ; MIPS32EB-NEXT:    xori $1, $1, 3
-; MIPS32EB-NEXT:    sll $3, $1, 3
-; MIPS32EB-NEXT:    ori $1, $zero, 255
-; MIPS32EB-NEXT:    sllv $6, $1, $3
+; MIPS32EB-NEXT:    sll $1, $1, 3
+; MIPS32EB-NEXT:    ori $2, $zero, 255
+; MIPS32EB-NEXT:    sllv $6, $2, $1
 ; MIPS32EB-NEXT:    nor $7, $zero, $6
-; MIPS32EB-NEXT:    andi $1, $4, 255
-; MIPS32EB-NEXT:    sllv $4, $1, $3
-; MIPS32EB-NEXT:    andi $1, $5, 255
-; MIPS32EB-NEXT:    sllv $5, $1, $3
+; MIPS32EB-NEXT:    andi $2, $4, 255
+; MIPS32EB-NEXT:    sllv $4, $2, $1
+; MIPS32EB-NEXT:    andi $2, $5, 255
+; MIPS32EB-NEXT:    sllv $5, $2, $1
 ; MIPS32EB-NEXT:  $BB12_1: # %entry
 ; MIPS32EB-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32EB-NEXT:    ll $8, 0($2)
+; MIPS32EB-NEXT:    ll $8, 0($3)
 ; MIPS32EB-NEXT:    and $9, $8, $6
 ; MIPS32EB-NEXT:    bne $9, $4, $BB12_3
 ; MIPS32EB-NEXT:    nop
@@ -4875,17 +4869,16 @@
 ; MIPS32EB-NEXT:    # in Loop: Header=BB12_1 Depth=1
 ; MIPS32EB-NEXT:    and $8, $8, $7
 ; MIPS32EB-NEXT:    or $8, $8, $5
-; MIPS32EB-NEXT:    sc $8, 0($2)
+; MIPS32EB-NEXT:    sc $8, 0($3)
 ; MIPS32EB-NEXT:    beqz $8, $BB12_1
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  $BB12_3: # %entry
-; MIPS32EB-NEXT:    srlv $1, $9, $3
-; MIPS32EB-NEXT:    sll $1, $1, 24
-; MIPS32EB-NEXT:    sra $1, $1, 24
+; MIPS32EB-NEXT:    srlv $2, $9, $1
+; MIPS32EB-NEXT:    sll $2, $2, 24
+; MIPS32EB-NEXT:    sra $2, $2, 24
 ; MIPS32EB-NEXT:  # %bb.4: # %entry
-; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    jr $ra
-; MIPS32EB-NEXT:    sra $2, $1, 24
+; MIPS32EB-NEXT:    nop
 entry:
   %pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic
   %0 = extractvalue { i8, i1 } %pair0, 0
@@ -4924,9 +4917,7 @@
 ; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    sra $1, $1, 24
 ; MIPS32-NEXT:  # %bb.4: # %entry
-; MIPS32-NEXT:    sll $2, $5, 24
-; MIPS32-NEXT:    sra $2, $2, 24
-; MIPS32-NEXT:    xor $1, $1, $2
+; MIPS32-NEXT:    xor $1, $1, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    sltiu $2, $1, 1
 ;
@@ -5119,9 +5110,7 @@
 ; MIPS4-NEXT:    sll $1, $1, 24
 ; MIPS4-NEXT:    sra $1, $1, 24
 ; MIPS4-NEXT:  # %bb.4: # %entry
-; MIPS4-NEXT:    sll $2, $5, 24
-; MIPS4-NEXT:    sra $2, $2, 24
-; MIPS4-NEXT:    xor $1, $1, $2
+; MIPS4-NEXT:    xor $1, $1, $5
 ; MIPS4-NEXT:    jr $ra
 ; MIPS4-NEXT:    sltiu $2, $1, 1
 ;
@@ -5156,9 +5145,7 @@
 ; MIPS64-NEXT:    sll $1, $1, 24
 ; MIPS64-NEXT:    sra $1, $1, 24
 ; MIPS64-NEXT:  # %bb.4: # %entry
-; MIPS64-NEXT:    sll $2, $5, 24
-; MIPS64-NEXT:    sra $2, $2, 24
-; MIPS64-NEXT:    xor $1, $1, $2
+; MIPS64-NEXT:    xor $1, $1, $5
 ; MIPS64-NEXT:    jr $ra
 ; MIPS64-NEXT:    sltiu $2, $1, 1
 ;
@@ -5335,9 +5322,7 @@
 ; O1-NEXT:    sll $1, $1, 24
 ; O1-NEXT:    sra $1, $1, 24
 ; O1-NEXT:  # %bb.4: # %entry
-; O1-NEXT:    sll $2, $5, 24
-; O1-NEXT:    sra $2, $2, 24
-; O1-NEXT:    xor $1, $1, $2
+; O1-NEXT:    xor $1, $1, $5
 ; O1-NEXT:    jr $ra
 ; O1-NEXT:    sltiu $2, $1, 1
 ;
@@ -5372,9 +5357,7 @@
 ; O2-NEXT:    sll $1, $1, 24
 ; O2-NEXT:    sra $1, $1, 24
 ; O2-NEXT:  # %bb.4: # %entry
-; O2-NEXT:    sll $2, $5, 24
-; O2-NEXT:    sra $2, $2, 24
-; O2-NEXT:    xor $1, $1, $2
+; O2-NEXT:    xor $1, $1, $5
 ; O2-NEXT:    jr $ra
 ; O2-NEXT:    sltiu $2, $1, 1
 ;
@@ -5409,9 +5392,7 @@
 ; O3-NEXT:    sll $1, $1, 24
 ; O3-NEXT:    sra $1, $1, 24
 ; O3-NEXT:  # %bb.4: # %entry
-; O3-NEXT:    sll $2, $5, 24
-; O3-NEXT:    sra $2, $2, 24
-; O3-NEXT:    xor $1, $1, $2
+; O3-NEXT:    xor $1, $1, $5
 ; O3-NEXT:    jr $ra
 ; O3-NEXT:    sltiu $2, $1, 1
 ;
@@ -5447,9 +5428,7 @@
 ; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    sra $1, $1, 24
 ; MIPS32EB-NEXT:  # %bb.4: # %entry
-; MIPS32EB-NEXT:    sll $2, $5, 24
-; MIPS32EB-NEXT:    sra $2, $2, 24
-; MIPS32EB-NEXT:    xor $1, $1, $2
+; MIPS32EB-NEXT:    xor $1, $1, $5
 ; MIPS32EB-NEXT:    jr $ra
 ; MIPS32EB-NEXT:    sltiu $2, $1, 1
 entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
@@ -7,8 +7,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 0
   ret i8 %r
@@ -20,8 +18,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 2
   ret i8 %r
@@ -33,8 +29,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 %idx
   ret i8 %r
@@ -45,8 +39,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 0
   ret i8 %r
@@ -58,8 +50,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 2
   ret i8 %r
@@ -71,8 +61,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 %idx
   ret i8 %r
@@ -83,8 +71,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 0
   ret i8 %r
@@ -96,8 +82,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 2
   ret i8 %r
@@ -109,8 +93,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 %idx
   ret i8 %r
@@ -121,8 +103,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 0
   ret i8 %r
@@ -134,8 +114,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 2
   ret i8 %r
@@ -147,8 +125,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 %idx
   ret i8 %r
@@ -159,8 +135,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 0
   ret i8 %r
@@ -172,8 +146,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 2
   ret i8 %r
@@ -185,8 +157,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 %idx
   ret i8 %r
@@ -197,8 +167,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 0
   ret i8 %r
@@ -210,8 +178,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 2
   ret i8 %r
@@ -223,8 +189,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 %idx
   ret i8 %r
@@ -235,8 +199,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 0
   ret i8 %r
@@ -248,8 +210,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 2
   ret i8 %r
@@ -261,8 +221,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 24
-; CHECK-NEXT:    srai a0, a0, 24
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 %idx
   ret i8 %r
@@ -273,8 +231,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 0
   ret i16 %r
@@ -286,8 +242,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 2
   ret i16 %r
@@ -299,8 +253,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 %idx
   ret i16 %r
@@ -311,8 +263,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 0
   ret i16 %r
@@ -324,8 +274,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 2
   ret i16 %r
@@ -337,8 +285,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 %idx
   ret i16 %r
@@ -349,8 +295,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 0
   ret i16 %r
@@ -362,8 +306,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 2
   ret i16 %r
@@ -375,8 +317,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 %idx
   ret i16 %r
@@ -387,8 +327,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 0
   ret i16 %r
@@ -400,8 +338,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 2
   ret i16 %r
@@ -413,8 +349,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 %idx
   ret i16 %r
@@ -425,8 +359,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 0
   ret i16 %r
@@ -438,8 +370,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 2
   ret i16 %r
@@ -451,8 +381,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 %idx
   ret i16 %r
@@ -463,8 +391,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 0
   ret i16 %r
@@ -476,8 +402,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 2
   ret i16 %r
@@ -489,8 +413,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 16
-; CHECK-NEXT:    srai a0, a0, 16
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 %idx
   ret i16 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
@@ -7,8 +7,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 0
   ret i8 %r
@@ -20,8 +18,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 2
   ret i8 %r
@@ -33,8 +29,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 %idx
   ret i8 %r
@@ -45,8 +39,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 0
   ret i8 %r
@@ -58,8 +50,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 2
   ret i8 %r
@@ -71,8 +61,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 %idx
   ret i8 %r
@@ -83,8 +71,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 0
   ret i8 %r
@@ -96,8 +82,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 2
   ret i8 %r
@@ -109,8 +93,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 %idx
   ret i8 %r
@@ -121,8 +103,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 0
   ret i8 %r
@@ -134,8 +114,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 2
   ret i8 %r
@@ -147,8 +125,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 %idx
   ret i8 %r
@@ -159,8 +135,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 0
   ret i8 %r
@@ -172,8 +146,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 2
   ret i8 %r
@@ -185,8 +157,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 %idx
   ret i8 %r
@@ -197,8 +167,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 0
   ret i8 %r
@@ -210,8 +178,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 2
   ret i8 %r
@@ -223,8 +189,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 %idx
   ret i8 %r
@@ -235,8 +199,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 0
   ret i8 %r
@@ -248,8 +210,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 2
   ret i8 %r
@@ -261,8 +221,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 56
-; CHECK-NEXT:    srai a0, a0, 56
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 %idx
   ret i8 %r
@@ -273,8 +231,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 0
   ret i16 %r
@@ -286,8 +242,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 2
   ret i16 %r
@@ -299,8 +253,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 %idx
   ret i16 %r
@@ -311,8 +263,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 0
   ret i16 %r
@@ -324,8 +274,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 2
   ret i16 %r
@@ -337,8 +285,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 %idx
   ret i16 %r
@@ -349,8 +295,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 0
   ret i16 %r
@@ -362,8 +306,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 2
   ret i16 %r
@@ -375,8 +317,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 %idx
   ret i16 %r
@@ -387,8 +327,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 0
   ret i16 %r
@@ -400,8 +338,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 2
   ret i16 %r
@@ -413,8 +349,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 %idx
   ret i16 %r
@@ -425,8 +359,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 0
   ret i16 %r
@@ -438,8 +370,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 2
   ret i16 %r
@@ -451,8 +381,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 %idx
   ret i16 %r
@@ -463,8 +391,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 0
   ret i16 %r
@@ -476,8 +402,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 2
   ret i16 %r
@@ -489,8 +413,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 %idx
   ret i16 %r
@@ -501,7 +423,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 0
   ret i32 %r
@@ -513,7 +434,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 2
   ret i32 %r
@@ -525,7 +445,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 %idx
   ret i32 %r
@@ -536,7 +455,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 0
   ret i32 %r
@@ -548,7 +466,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 2
   ret i32 %r
@@ -560,7 +477,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v25
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 %idx
   ret i32 %r
@@ -571,7 +487,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 0
   ret i32 %r
@@ -583,7 +498,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 2
   ret i32 %r
@@ -595,7 +509,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v26
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 %idx
   ret i32 %r
@@ -606,7 +519,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 0
   ret i32 %r
@@ -618,7 +530,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 2
   ret i32 %r
@@ -630,7 +541,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v28
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 %idx
   ret i32 %r
@@ -641,7 +551,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 0
   ret i32 %r
@@ -653,7 +562,6 @@
 ; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 2
   ret i32 %r
@@ -665,7 +573,6 @@
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
 ; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    sext.w a0, a0
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 %idx
   ret i32 %r