diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -41,8 +41,8 @@
       : B(B), MF(B.getMF()), MRI(*B.getMRI()), Helper(Helper){};
 
   struct ClampI64ToI16MatchInfo {
-    int64_t Cmp1;
-    int64_t Cmp2;
+    int64_t Cmp1 = 0;
+    int64_t Cmp2 = 0;
     Register Origin;
   };
 
@@ -71,18 +71,24 @@
   Register Base;
 
   // Try to match a combination of min / max MIR opcodes.
-  if (mi_match(MI.getOperand(1).getReg(), MRI, m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) {
-    if (!mi_match(Base, MRI, m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) {
-      return false;
-    }
+  bool continueMatch =
+      mi_match(MI.getOperand(1).getReg(), MRI,
+               m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1))) &&
+      mi_match(Base, MRI,
+               m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)));
+
+  if (!continueMatch) {
+    continueMatch =
+        mi_match(MI.getOperand(1).getReg(), MRI,
+                 m_GSMax(m_Reg(Base), m_ICst(MatchInfo.Cmp1))) &&
+        mi_match(Base, MRI,
+                 m_GSMin(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)));
   }
 
-  if (mi_match(MI.getOperand(1).getReg(), MRI, m_GSMax(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) {
-    if (!mi_match(Base, MRI, m_GSMin(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) {
-      return false;
-    }
+  if (!continueMatch) {
+    return false;
   }
-   
+
   const auto Cmp1 = MatchInfo.Cmp1;
   const auto Cmp2 = MatchInfo.Cmp2;
   const auto Diff = std::abs(Cmp2 - Cmp1);