diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -438,8 +438,8 @@ defm "" : VPatBinarySDNode_VV_VX; // 12.11. Vector Integer Divide Instructions -defm "" : VPatBinarySDNode_VV_VX; -defm "" : VPatBinarySDNode_VV_VX; +defm "" : VPatBinarySDNode_VV_VX; +defm "" : VPatBinarySDNode_VV_VX; defm "" : VPatBinarySDNode_VV_VX; defm "" : VPatBinarySDNode_VV_VX; diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -70,7 +70,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -80,7 +80,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -121,7 +121,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -152,7 +152,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -162,7 +162,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -193,7 +193,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -203,7 +203,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -234,7 +234,7 @@ ; CHECK-LABEL: vdiv_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -244,7 +244,7 @@ ; CHECK-LABEL: vdiv_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -275,7 +275,7 @@ ; CHECK-LABEL: vdiv_vv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -285,7 +285,7 @@ ; CHECK-LABEL: vdiv_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -316,7 +316,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -326,7 +326,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -357,7 +357,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -367,7 +367,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -398,7 +398,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -408,7 +408,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -439,7 +439,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -449,7 +449,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -480,7 +480,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -490,7 +490,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -521,7 +521,7 @@ ; CHECK-LABEL: vdiv_vv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -531,7 +531,7 @@ ; CHECK-LABEL: vdiv_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -562,7 +562,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -572,7 +572,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -603,7 +603,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -613,7 +613,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -644,7 +644,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -654,7 +654,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -685,7 +685,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -695,7 +695,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -726,7 +726,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -736,7 +736,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -767,7 +767,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -784,7 +784,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vdivu.vv v8, v8, v25 +; CHECK-NEXT: vdiv.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -825,7 +825,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -842,7 +842,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vdivu.vv v8, v8, v26 +; CHECK-NEXT: vdiv.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -883,7 +883,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -900,7 +900,7 @@ ; CHECK-NEXT: vsll.vx v12, v12, a1 ; CHECK-NEXT: vsrl.vx v12, v12, a1 ; CHECK-NEXT: vor.vv v28, v12, v28 -; CHECK-NEXT: vdivu.vv v8, v8, v28 +; CHECK-NEXT: vdiv.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -941,7 +941,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -958,7 +958,7 @@ ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 ; CHECK-NEXT: vor.vv v16, v24, v16 -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -46,7 +46,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -56,7 +56,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -87,7 +87,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -97,7 +97,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -128,7 +128,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -138,7 +138,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -169,7 +169,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -179,7 +179,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -210,7 +210,7 @@ ; CHECK-LABEL: vdiv_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -220,7 +220,7 @@ ; CHECK-LABEL: vdiv_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +251,7 @@ ; CHECK-LABEL: vdiv_vv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -261,7 +261,7 @@ ; CHECK-LABEL: vdiv_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -292,7 +292,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -302,7 +302,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -333,7 +333,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -343,7 +343,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -374,7 +374,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -384,7 +384,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -415,7 +415,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -425,7 +425,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -456,7 +456,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -466,7 +466,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +497,7 @@ ; CHECK-LABEL: vdiv_vv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -507,7 +507,7 @@ ; CHECK-LABEL: vdiv_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -538,7 +538,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -548,7 +548,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -580,7 +580,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -590,7 +590,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -622,7 +622,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -632,7 +632,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -664,7 +664,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -674,7 +674,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -706,7 +706,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -716,7 +716,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -748,7 +748,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -758,7 +758,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -796,7 +796,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -806,7 +806,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -844,7 +844,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -854,7 +854,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -892,7 +892,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -902,7 +902,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -78,7 +78,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -107,7 +107,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -117,7 +117,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -146,7 +146,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -156,7 +156,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -185,7 +185,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -195,7 +195,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +224,7 @@ ; CHECK-LABEL: vdivu_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -234,7 +234,7 @@ ; CHECK-LABEL: vdivu_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -263,7 +263,7 @@ ; CHECK-LABEL: vdivu_vv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -273,7 +273,7 @@ ; CHECK-LABEL: vdivu_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -302,7 +302,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -312,7 +312,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -342,7 +342,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -352,7 +352,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -382,7 +382,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -392,7 +392,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -422,7 +422,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -432,7 +432,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +462,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -472,7 +472,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -502,7 +502,7 @@ ; CHECK-LABEL: vdivu_vv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -512,7 +512,7 @@ ; CHECK-LABEL: vdivu_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -542,7 +542,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -552,7 +552,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -582,7 +582,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -592,7 +592,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -622,7 +622,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -632,7 +632,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -662,7 +662,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -672,7 +672,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -702,7 +702,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -712,7 +712,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,7 +742,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -759,7 +759,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vdiv.vv v8, v8, v25 +; CHECK-NEXT: vdivu.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -796,7 +796,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -813,7 +813,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vdiv.vv v8, v8, v26 +; CHECK-NEXT: vdivu.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -850,7 +850,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -867,7 +867,7 @@ ; CHECK-NEXT: vsll.vx v12, v12, a1 ; CHECK-NEXT: vsrl.vx v12, v12, a1 ; CHECK-NEXT: vor.vv v28, v12, v28 -; CHECK-NEXT: vdiv.vv v8, v8, v28 +; CHECK-NEXT: vdivu.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -904,7 +904,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -921,7 +921,7 @@ ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 ; CHECK-NEXT: vor.vv v16, v24, v16 -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -44,7 +44,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -54,7 +54,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -83,7 +83,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -93,7 +93,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -122,7 +122,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -132,7 +132,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -161,7 +161,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -171,7 +171,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -200,7 +200,7 @@ ; CHECK-LABEL: vdivu_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -210,7 +210,7 @@ ; CHECK-LABEL: vdivu_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +239,7 @@ ; CHECK-LABEL: vdivu_vv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -249,7 +249,7 @@ ; CHECK-LABEL: vdivu_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -278,7 +278,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -288,7 +288,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -318,7 +318,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -328,7 +328,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -358,7 +358,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -368,7 +368,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -398,7 +398,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -408,7 +408,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -438,7 +438,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -448,7 +448,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -478,7 +478,7 @@ ; CHECK-LABEL: vdivu_vv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -488,7 +488,7 @@ ; CHECK-LABEL: vdivu_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -518,7 +518,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -528,7 +528,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -558,7 +558,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -568,7 +568,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -598,7 +598,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -608,7 +608,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +638,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -648,7 +648,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -678,7 +678,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -688,7 +688,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -718,7 +718,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -728,7 +728,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -760,7 +760,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -770,7 +770,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -802,7 +802,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -812,7 +812,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -844,7 +844,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -854,7 +854,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer