Index: llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -133,6 +133,15 @@
         continue;
       }
 
+      // Eliminate hints.
+      if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
+        Register DstReg = MI.getOperand(0).getReg();
+        Register SrcReg = MI.getOperand(1).getReg();
+        MI.eraseFromParent();
+        MRI.replaceRegWith(DstReg, SrcReg);
+        continue;
+      }
+
       if (!ISel->select(MI)) {
         // FIXME: It would be nice to dump all inserted instructions.  It's
         // not obvious how, esp. considering select() can insert after MI.
Index: llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+# Check that we remove G_ASSERT_ZEXT during selection.
+
+...
+---
+name:            assert_zext_gpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $w0, $w1
+
+    ; CHECK-LABEL: name: assert_zext_gpr
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK: %copy:gpr32all = COPY $w0
+    ; CHECK: $w1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:gpr(s32) = COPY $w0
+    %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16
+    $w1 = COPY %copy_assert_zext(s32)
+    RET_ReallyLR implicit $w1
+
+...
+---
+name:            assert_zext_fpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $s1
+
+    ; CHECK-LABEL: name: assert_zext_fpr
+    ; CHECK: liveins: $s0, $s1
+    ; CHECK: %copy:fpr32 = COPY $s0
+    ; CHECK: $s1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $s1
+    %copy:fpr(s32) = COPY $s0
+    %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+    $s1 = COPY %copy_assert_zext(s32)
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            assert_zext_in_between_cross_bank
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $w1
+
+    ; CHECK-LABEL: name: assert_zext_in_between_cross_bank
+    ; CHECK: liveins: $s0, $w1
+    ; CHECK: %copy:fpr32 = COPY $s0
+    ; CHECK: $w1 = COPY %copy
+    ; CHECK: RET_ReallyLR implicit $w1
+    %copy:fpr(s32) = COPY $s0
+    %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16
+    $w1 = COPY %copy_assert_zext(s32)
+    RET_ReallyLR implicit $w1