diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -8604,16 +8604,19 @@ // If it is a splat of a double, check if we can shrink it to a 32 bit // non-denormal float which when converted back to double gives us the same - // double. This is to exploit the XXSPLTIDP instruction.+ // If we lose precision, we use XXSPLTI32DX. + // double. This is to exploit the XXSPLTIDP instruction. + // If we lose precision, we use XXSPLTI32DX. if (BVNIsConstantSplat && (SplatBitSize == 64) && Subtarget.hasPrefixInstrs()) { - if (convertToNonDenormSingle(APSplatBits) && - (Op->getValueType(0) == MVT::v2f64)) { + // Check the type first to short-circuit so we don't modify APSplatBits if + // this block isn't executed. + if ((Op->getValueType(0) == MVT::v2f64) && + convertToNonDenormSingle(APSplatBits)) { SDValue SplatNode = DAG.getNode( PPCISD::XXSPLTI_SP_TO_DP, dl, MVT::v2f64, DAG.getTargetConstant(APSplatBits.getZExtValue(), dl, MVT::i32)); return DAG.getBitcast(Op.getValueType(), SplatNode); - } else if (APSplatBits.getBitWidth() == 64) { + } else { // We may lose precision, so we have to use XXSPLTI32DX. uint32_t Hi = diff --git a/llvm/test/CodeGen/PowerPC/p10-splatImm32.ll b/llvm/test/CodeGen/PowerPC/p10-splatImm32.ll --- a/llvm/test/CodeGen/PowerPC/p10-splatImm32.ll +++ b/llvm/test/CodeGen/PowerPC/p10-splatImm32.ll @@ -101,23 +101,11 @@ ret <8 x i16> } -define dso_local <16 x i8> @test_xxsplti32dx_10() { -; CHECK-LABEL: test_xxsplti32dx_10: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxlxor vs34, vs34, vs34 -; CHECK-NEXT: xxsplti32dx vs34, 0, 1207959552 -; CHECK-NEXT: blr -entry: - ret <16 x i8> -} - -; FIXME: It appears that there is something wrong with the computation -; of the 64-bit constant to splat so we cannot emit xxsplti32dx for -; this test case for now. define dso_local <16 x i8> @constSplatBug() { ; CHECK-LABEL: constSplatBug: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: plxv vs34, .LCPI10_0@PCREL(0), 1 +; CHECK-NEXT: xxlxor vs34, vs34, vs34 +; CHECK-NEXT: xxsplti32dx vs34, 0, 1191182336 ; CHECK-NEXT: blr entry: ret <16 x i8>