diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -8256,7 +8256,10 @@
 
         *Except the argument registers, the VGPR clobbered and the preserved
         registers are intermixed at regular intervals in order to
-        get a better occupancy.*
+        keep a similar ratio independent of the amount of available VGPRs.*
+
+      Lanes of VGPRs that are inactive for the call must be preserved for all
+      VGPRs.
 
       For the AMDGPU backend, an inter-procedural register allocation (IPRA)
       optimization may mark some of clobbered SGPR and VGPR registers as