diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -3579,10 +3579,10 @@
   let Inst{15-12} = Rd;
 }
 
-def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
+def MOVsr : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_reg:$src),
                 DPSoRegRegFrm, IIC_iMOVsr,
                 "mov", "\t$Rd, $src",
-                [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
+                [(set GPR:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
                 Sched<[WriteALU]> {
   bits<4> Rd;
   bits<12> src;
@@ -6327,16 +6327,16 @@
                         (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
-                        (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                        (ins GPR:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
                              cc_out:$s)>;
 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
-                        (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                        (ins GPR:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
                              cc_out:$s)>;
 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
-                        (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                        (ins GPR:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
                              cc_out:$s)>;
 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
-                        (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
+                        (ins GPR:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
                              cc_out:$s)>;
 }
 
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -843,7 +843,7 @@
     ; CHECK-LABEL: name: test_lshr_s32
     ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
-    ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 3, 14 /* CC::al */, $noreg, $noreg
+    ; CHECK: [[MOVsr:%[0-9]+]]:gpr = MOVsr [[COPY]], [[COPY1]], 3, 14 /* CC::al */, $noreg, $noreg
     ; CHECK: $r0 = COPY [[MOVsr]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
     %0(s32) = COPY $r0
@@ -872,7 +872,7 @@
     ; CHECK-LABEL: name: test_ashr_s32
     ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
-    ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+    ; CHECK: [[MOVsr:%[0-9]+]]:gpr = MOVsr [[COPY]], [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
     ; CHECK: $r0 = COPY [[MOVsr]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
     %0(s32) = COPY $r0
@@ -901,7 +901,7 @@
     ; CHECK-LABEL: name: test_shl_s32
     ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
-    ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 2, 14 /* CC::al */, $noreg, $noreg
+    ; CHECK: [[MOVsr:%[0-9]+]]:gpr = MOVsr [[COPY]], [[COPY1]], 2, 14 /* CC::al */, $noreg, $noreg
     ; CHECK: $r0 = COPY [[MOVsr]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
     %0(s32) = COPY $r0
diff --git a/llvm/test/MC/ARM/lsl-zero-errors.s b/llvm/test/MC/ARM/lsl-zero-errors.s
--- a/llvm/test/MC/ARM/lsl-zero-errors.s
+++ b/llvm/test/MC/ARM/lsl-zero-errors.s
@@ -153,3 +153,15 @@
 // CHECK-ARM: movs sp, sp               @ encoding: [0x0d,0xd0,0xb0,0xe1]
 // CHECK-ARM: movs r0, sp               @ encoding: [0x0d,0x00,0xb0,0xe1]
 // CHECK-ARM: movs sp, r0               @ encoding: [0x00,0xd0,0xb0,0xe1]
+
+        movs  pc, r1, lsl r2
+        lsrs  pc, r1, r2
+        asrs  pc, r1, r2
+        rors  pc, r1, r2
+        rrxs  pc, r1
+
+// CHECK-ARM: lsls pc, r1, r2 @ encoding: [0x11,0xf2,0xb0,0xe1]
+// CHECK-ARM: lsrs pc, r1, r2 @ encoding: [0x31,0xf2,0xb0,0xe1]
+// CHECK-ARM: asrs pc, r1, r2 @ encoding: [0x51,0xf2,0xb0,0xe1]
+// CHECK-ARM: rors pc, r1, r2 @ encoding: [0x71,0xf2,0xb0,0xe1]
+// CHECK-ARM: rrxs pc, r1     @ encoding: [0x61,0xf0,0xb0,0xe1]
diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
--- a/llvm/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
+++ b/llvm/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
@@ -9,5 +9,5 @@
 # A8.6.89 LSL (register)
 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 
-# CHECK: warning: potentially undefined instruction encoding
+# CHECK: lsl     pc, r2, r1
 0x12 0xf1 0xa0 0xe1