diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -6788,7 +6788,8 @@ // ENDBR instructions should not be scheduled around. unsigned Opcode = MI.getOpcode(); - if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32) + if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 || + Opcode == X86::PLDTILECFG) return true; return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF); diff --git a/llvm/test/CodeGen/X86/AMX/amx-sched.ll b/llvm/test/CodeGen/X86/AMX/amx-sched.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/AMX/amx-sched.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -mcpu=skx -verify-machineinstrs | FileCheck %s + +define <256 x i32> @test_shape_sched(i16 %m, i16 %n, i16 %k, <256 x i32> %c, <256 x i32> %a, <256 x i32> %b) nounwind { +; Just to make sure shape def is not scheduled across ldtilecfg. +; CHECK: ldtilecfg +; CHECK-NOT: movw + %c1 = bitcast <256 x i32> %c to x86_amx + %a1 = bitcast <256 x i32> %a to x86_amx + %b1 = bitcast <256 x i32> %b to x86_amx + %t = call x86_amx @llvm.x86.tdpbssd.internal(i16 %m, i16 %n, i16 %k, x86_amx %c1, x86_amx %a1, x86_amx %b1) + %res = bitcast x86_amx %t to <256 x i32> + ret <256 x i32> %res +} + + +declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)