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Differential D95551

[ARM] One-off identity shuffle
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Authored by dmgreen on Jan 27 2021, 11:16 AM.

Details

Reviewers
NickGuy
SjoerdMeijer
simon_tatham
efriedma
ostannard
Commits
rG0c7e044a7f62: [ARM] One-off identity shuffle
Summary

A One-Off Identity mask is a shuffle that is mostly an identity mask from as single source but contains a single element out-of-place, either from a different vector or from another position in the same vector. As opposed to lowering this via a ARMISD::BUILD_VECTOR we can generate an extract/insert pair directly. Under ARM with individually accessible lane elements this often becomes a simple lane move.

This also alters the LowerVECTOR_SHUFFLEUsingMovs code to use v4f32 (not v4i32), a more natural type for lane moves.

Diff Detail

Event Timeline

dmgreen created this revision.Jan 27 2021, 11:16 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptJan 27 2021, 11:16 AM
dmgreen requested review of this revision.Jan 27 2021, 11:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 27 2021, 11:16 AM
dmgreen added a parent revision: D95471: [ARM] VINS f16 pattern.Feb 2 2021, 1:00 AM
dmgreen added a child revision: D96065: [ARM] Single source VMOVNT.Feb 4 2021, 11:31 AM
dmgreen added a comment.Feb 8 2021, 12:58 AM

ping

SjoerdMeijer added inline comments.Feb 8 2021, 1:23 AM
llvm/lib/Target/ARM/ARMISelLowering.cpp
8197–8198

Why are we changing this into v4f32?

dmgreen added a comment.Feb 8 2021, 1:33 AM

Thanks for talking a look

llvm/lib/Target/ARM/ARMISelLowering.cpp
8197–8198

A v4f32 is a more natural type for lane moves, which is what this is essentially doing. We are moving s registers around, with are naturally f32's.

SjoerdMeijer added inline comments.Feb 8 2021, 7:09 AM
llvm/lib/Target/ARM/ARMISelLowering.cpp
8246

nit: shorter is:

for (int i = 0; i < Mask.size(); ++i)
8247

Do we have a test for this? Might have missed it, but didn't see one I think.

dmgreen added inline comments.Feb 8 2021, 7:59 AM
llvm/lib/Target/ARM/ARMISelLowering.cpp
8246

I believe this is how llvm specifies this should be. So we only evaluate Mask.size() once. Apparently I got it from here:
https://github.com/llvm/llvm-project/blob/73aa09704a4c85b097d5fab986ead27092ecc9f7/llvm/lib/IR/Instructions.cpp#L2131

8247

For undef elements? Yeah they will be tested as a part of the vld3 and shuffle3steptype tests I believe, but I'll make sure there are specific tests.

dmgreen updated this revision to Diff 322115.Feb 8 2021, 8:07 AM

Rebase and add some undef mask element tests.

SjoerdMeijer accepted this revision.Feb 8 2021, 8:23 AM

Thanks, LGTM

This revision is now accepted and ready to land.Feb 8 2021, 8:23 AM
Closed by commit rG0c7e044a7f62: [ARM] One-off identity shuffle (authored by dmgreen). · Explain WhyFeb 8 2021, 1:24 PM
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG0c7e044a7f62: [ARM] One-off identity shuffle.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
65 lines
test/
CodeGen/
Thumb2/
8 lines
419 lines
1083 lines
1243 lines
56 lines

Diff 322201

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,188 Lines • ▼ Show 20 Lines for (int Part = 0; Part < 4; ++Part) {
// Does this part look like a mov // Does this part look like a mov
int Elt = getMovIdx(ShuffleMask, Part * QuarterSize, QuarterSize); int Elt = getMovIdx(ShuffleMask, Part * QuarterSize, QuarterSize);
if (Elt != -1) { if (Elt != -1) {
SDValue Input = Op->getOperand(0); SDValue Input = Op->getOperand(0);
if (Elt >= 4) { if (Elt >= 4) {
Input = Op->getOperand(1); Input = Op->getOperand(1);
Elt -= 4; Elt -= 4;
} }
SDValue BitCast = DAG.getBitcast(MVT::v4i32, Input); SDValue BitCast = DAG.getBitcast(MVT::v4f32, Input);
Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, BitCast, Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, BitCast,
SjoerdMeijerUnsubmitted
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Why are we changing this into v4f32?

SjoerdMeijer: Why are we changing this into v4f32?
dmgreenAuthorUnsubmitted
Done
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A v4f32 is a more natural type for lane moves, which is what this is essentially doing. We are moving s registers around, with are naturally f32's.

dmgreen: A v4f32 is a more natural type for lane moves, which is what this is essentially doing. We are…
DAG.getConstant(Elt, dl, MVT::i32)); DAG.getConstant(Elt, dl, MVT::i32));
} }
} }
// Nothing interesting found, just return // Nothing interesting found, just return
if (!Parts[0] && !Parts[1] && !Parts[2] && !Parts[3]) if (!Parts[0] && !Parts[1] && !Parts[2] && !Parts[3])
return SDValue(); return SDValue();
// The other parts need to be built with the old shuffle vector, cast to a // The other parts need to be built with the old shuffle vector, cast to a
// v4i32 and extract_vector_elts // v4i32 and extract_vector_elts
if (!Parts[0] || !Parts[1] || !Parts[2] || !Parts[3]) { if (!Parts[0] || !Parts[1] || !Parts[2] || !Parts[3]) {
SmallVector<int, 16> NewShuffleMask; SmallVector<int, 16> NewShuffleMask;
for (int Part = 0; Part < 4; ++Part) for (int Part = 0; Part < 4; ++Part)
for (int i = 0; i < QuarterSize; i++) for (int i = 0; i < QuarterSize; i++)
NewShuffleMask.push_back( NewShuffleMask.push_back(
Parts[Part] ? -1 : ShuffleMask[Part * QuarterSize + i]); Parts[Part] ? -1 : ShuffleMask[Part * QuarterSize + i]);
SDValue NewShuffle = DAG.getVectorShuffle( SDValue NewShuffle = DAG.getVectorShuffle(
VT, dl, Op->getOperand(0), Op->getOperand(1), NewShuffleMask); VT, dl, Op->getOperand(0), Op->getOperand(1), NewShuffleMask);
SDValue BitCast = DAG.getBitcast(MVT::v4i32, NewShuffle); SDValue BitCast = DAG.getBitcast(MVT::v4f32, NewShuffle);
for (int Part = 0; Part < 4; ++Part) for (int Part = 0; Part < 4; ++Part)
if (!Parts[Part]) if (!Parts[Part])
Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32,
BitCast, DAG.getConstant(Part, dl, MVT::i32)); BitCast, DAG.getConstant(Part, dl, MVT::i32));
} }
// Build a vector out of the various parts and bitcast it back to the original // Build a vector out of the various parts and bitcast it back to the original
// type. // type.
SDValue NewVec = DAG.getBuildVector(MVT::v4i32, dl, Parts); SDValue NewVec = DAG.getNode(ARMISD::BUILD_VECTOR, dl, MVT::v4f32, Parts);
return DAG.getBitcast(VT, NewVec); return DAG.getBitcast(VT, NewVec);
} }
static SDValue LowerVECTOR_SHUFFLEUsingOneOff(SDValue Op,
ArrayRef<int> ShuffleMask,
SelectionDAG &DAG) {
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
EVT VT = Op.getValueType();
unsigned NumElts = VT.getVectorNumElements();
// An One-Off Identity mask is one that is mostly an identity mask from as
// single source but contains a single element out-of-place, either from a
// different vector or from another position in the same vector. As opposed to
// lowering this via a ARMISD::BUILD_VECTOR we can generate an extract/insert
// pair directly.
auto isOneOffIdentityMask = [](ArrayRef<int> Mask, EVT VT, int BaseOffset,
int &OffElement) {
OffElement = -1;
int NonUndef = 0;
SjoerdMeijerUnsubmitted
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nit: shorter is:

for (int i = 0; i < Mask.size(); ++i)
SjoerdMeijer: nit: shorter is: for (int i = 0; i < Mask.size(); ++i)
dmgreenAuthorUnsubmitted
Done
ReplyInline Actions

I believe this is how llvm specifies this should be. So we only evaluate Mask.size() once. Apparently I got it from here:
https://github.com/llvm/llvm-project/blob/73aa09704a4c85b097d5fab986ead27092ecc9f7/llvm/lib/IR/Instructions.cpp#L2131

dmgreen: I believe this is how llvm specifies this should be. So we only evaluate Mask.size() once.
for (int i = 0, NumMaskElts = Mask.size(); i < NumMaskElts; ++i) {
SjoerdMeijerUnsubmitted
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Do we have a test for this? Might have missed it, but didn't see one I think.

SjoerdMeijer: Do we have a test for this? Might have missed it, but didn't see one I think.
dmgreenAuthorUnsubmitted
Done
ReplyInline Actions

For undef elements? Yeah they will be tested as a part of the vld3 and shuffle3steptype tests I believe, but I'll make sure there are specific tests.

dmgreen: For undef elements? Yeah they will be tested as a part of the vld3 and shuffle3steptype tests I…
if (Mask[i] == -1)
continue;
NonUndef++;
if (Mask[i] != i + BaseOffset) {
if (OffElement == -1)
OffElement = i;
else
return false;
}
}
return NonUndef > 2 && OffElement != -1;
};
int OffElement;
SDValue VInput;
if (isOneOffIdentityMask(ShuffleMask, VT, 0, OffElement))
VInput = V1;
else if (isOneOffIdentityMask(ShuffleMask, VT, NumElts, OffElement))
VInput = V2;
else
return SDValue();
SDLoc dl(Op);
EVT SVT = VT.getScalarType() == MVT::i8 || VT.getScalarType() == MVT::i16
? MVT::i32
: VT.getScalarType();
SDValue Elt = DAG.getNode(
ISD::EXTRACT_VECTOR_ELT, dl, SVT,
ShuffleMask[OffElement] < (int)NumElts ? V1 : V2,
DAG.getVectorIdxConstant(ShuffleMask[OffElement] % NumElts, dl));
return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, VInput, Elt,
DAG.getVectorIdxConstant(OffElement % NumElts, dl));
}
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) { const ARMSubtarget *ST) {
SDValue V1 = Op.getOperand(0); SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1); SDValue V2 = Op.getOperand(1);
SDLoc dl(Op); SDLoc dl(Op);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
unsigned EltSize = VT.getScalarSizeInBits(); unsigned EltSize = VT.getScalarSizeInBits();
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) {
SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT), SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
SubV1, SubV2); SubV1, SubV2);
return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
Res.getValue(1)); Res.getValue(1));
} }
} }
} }
if (ST->hasMVEIntegerOps() && EltSize <= 32)
if (SDValue V = LowerVECTOR_SHUFFLEUsingOneOff(Op, ShuffleMask, DAG))
return V;
// If the shuffle is not directly supported and it has 4 elements, use // If the shuffle is not directly supported and it has 4 elements, use
// the PerfectShuffle-generated table to synthesize it from other shuffles. // the PerfectShuffle-generated table to synthesize it from other shuffles.
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
if (NumElts == 4) { if (NumElts == 4) {
unsigned PFIndexes[4]; unsigned PFIndexes[4];
for (unsigned i = 0; i != 4; ++i) { for (unsigned i = 0; i != 4; ++i) {
if (ShuffleMask[i] < 0) if (ShuffleMask[i] < 0)
PFIndexes[i] = 8; PFIndexes[i] = 8;
▲ Show 20 Lines • Show All 11,079 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-float16regloops.ll

Show First 20 Lines • Show All 1,475 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov r7, s4 ; CHECK-NEXT: vmov r7, s4
; CHECK-NEXT: vmov.16 q3[3], r7 ; CHECK-NEXT: vmov.16 q3[3], r7
; CHECK-NEXT: vstr.16 s28, [r5] ; CHECK-NEXT: vstr.16 s28, [r5]
; CHECK-NEXT: vfma.f16 q3, q5, r4 ; CHECK-NEXT: vfma.f16 q3, q5, r4
; CHECK-NEXT: vmov.u16 r4, q3[1] ; CHECK-NEXT: vmov.u16 r4, q3[1]
; CHECK-NEXT: vmovx.f16 s6, s12 ; CHECK-NEXT: vmovx.f16 s6, s12
; CHECK-NEXT: vfma.f16 q3, q6, r4 ; CHECK-NEXT: vfma.f16 q3, q6, r4
; CHECK-NEXT: vstr.16 s6, [r5, #2] ; CHECK-NEXT: vstr.16 s6, [r5, #2]
; CHECK-NEXT: vmov.f32 s12, s13
; CHECK-NEXT: vmovx.f16 s6, s13 ; CHECK-NEXT: vmovx.f16 s6, s13
; CHECK-NEXT: vmov q7, q3 ; CHECK-NEXT: vmov.f32 s12, s13
; CHECK-NEXT: vins.f16 s12, s6 ; CHECK-NEXT: vins.f16 s12, s6
; CHECK-NEXT: vmov.16 q7[2], r7
; CHECK-NEXT: adds r5, #4 ; CHECK-NEXT: adds r5, #4
; CHECK-NEXT: vmov.f32 s13, s29 ; CHECK-NEXT: vmov.16 q3[2], r7
; CHECK-NEXT: vmov.f32 s14, s30
; CHECK-NEXT: vmov.f32 s15, s31
; CHECK-NEXT: vmov q7, q3 ; CHECK-NEXT: vmov q7, q3
; CHECK-NEXT: le lr, .LBB17_5 ; CHECK-NEXT: le lr, .LBB17_5
; CHECK-NEXT: .LBB17_6: @ %while.end ; CHECK-NEXT: .LBB17_6: @ %while.end
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: beq .LBB17_1 ; CHECK-NEXT: beq .LBB17_1
; CHECK-NEXT: @ %bb.7: @ %if.then ; CHECK-NEXT: @ %bb.7: @ %if.then
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
▲ Show 20 Lines • Show All 131 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-shuffle.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
entry: entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 1, i32 1, i32 3> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 1, i32 1, i32 3>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <4 x i32> @oneoff12_i32(<4 x i32> %src1, <4 x i32> %src2) { define arm_aapcs_vfpcc <4 x i32> @oneoff12_i32(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: oneoff12_i32: ; CHECK-LABEL: oneoff12_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s5, s1 ; CHECK-NEXT: vmov.f32 s0, s4
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <4 x i32> @oneoff21_i32(<4 x i32> %src1, <4 x i32> %src2) { define arm_aapcs_vfpcc <4 x i32> @oneoff21_i32(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: oneoff21_i32: ; CHECK-LABEL: oneoff21_i32:
Show All 12 Lines
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov.f32 s2, s0 ; CHECK-NEXT: vmov.f32 s2, s0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 5, i32 4, i32 7> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 5, i32 4, i32 7>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <4 x i32> @oneoffundef_i32(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: oneoffundef_i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 4, i32 undef, i32 3>
ret <4 x i32> %out
}
define arm_aapcs_vfpcc <4 x i32> @shuffle2step_i32(<8 x i32> %src) { define arm_aapcs_vfpcc <4 x i32> @shuffle2step_i32(<8 x i32> %src) {
; CHECK-LABEL: shuffle2step_i32: ; CHECK-LABEL: shuffle2step_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f32 s9, s3 ; CHECK-NEXT: vmov.f32 s9, s3
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s10, s5 ; CHECK-NEXT: vmov.f32 s10, s5
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s11, s7 ; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vadd.i32 q0, q0, q2 ; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %s1 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s2 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %s2 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%r = add <4 x i32> %s1, %s2 %r = add <4 x i32> %s1, %s2
ret <4 x i32> %r ret <4 x i32> %r
} }
define arm_aapcs_vfpcc <4 x i32> @shuffle3step_i32(<16 x i32> %src) { define arm_aapcs_vfpcc <4 x i32> @shuffle3step_i32(<16 x i32> %src) {
; CHECK-LABEL: shuffle3step_i32: ; CHECK-LABEL: shuffle3step_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s12, s1 ; CHECK-NEXT: vmov.f32 s14, s8
; CHECK-NEXT: vmov.f32 s13, s4 ; CHECK-NEXT: vmov.f32 s15, s11
; CHECK-NEXT: vmov r0, s10 ; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov.f32 s14, s7 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s15, s19 ; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmov.f32 s16, s0 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s17, s3 ; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov r0, s9 ; CHECK-NEXT: vmov.f32 s19, s10
; CHECK-NEXT: vmov.f32 s18, s6 ; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vdup.32 q5, r0 ; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vadd.i32 q0, q0, q4
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vadd.i32 q0, q0, q3
; CHECK-NEXT: vmov.f32 s10, s8 ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: vadd.i32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vadd.i32 q0, q3, q1
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a = add <4 x i32> %s1, %s2 %a = add <4 x i32> %s1, %s2
%r = add <4 x i32> %a, %s3 %r = add <4 x i32> %a, %s3
ret <4 x i32> %r ret <4 x i32> %r
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Linesentry:
%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @oneoff11_i16(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @oneoff11_i16(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: oneoff11_i16: ; CHECK-LABEL: oneoff11_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q0[1] ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.16 q1[2], r0 ; CHECK-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.f32 s1, s5
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @oneoff12_i16(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @oneoff12_i16(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: oneoff12_i16: ; CHECK-LABEL: oneoff12_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmovnb.i32 q2, q1 ; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.f32 s9, s1
; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @oneoff21_i16(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @oneoff21_i16(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: oneoff21_i16: ; CHECK-LABEL: oneoff21_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vins.f16 s5, s0 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @oneoff22_i16(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @oneoff22_i16(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: oneoff22_i16: ; CHECK-LABEL: oneoff22_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov.u16 r0, q1[6] ; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[1]
; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov.f32 s1, s5
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @oneoffundef_i16(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: oneoffundef_i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 undef, i32 undef, i32 12, i32 3, i32 14, i32 15>
ret <8 x i16> %out
}
define arm_aapcs_vfpcc <8 x i16> @shuffle2step_i16(<16 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle2step_i16(<16 x i16> %src) {
; CHECK-LABEL: shuffle2step_i16: ; CHECK-LABEL: shuffle2step_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q0[1] ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.f32 s8, s0 ; CHECK-NEXT: vmov.f32 s8, s0
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[3] ; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vins.f16 s8, s1 ; CHECK-NEXT: vins.f16 s8, s1
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; CHECK-NEXT: vmov.16 q4[6], r0 ; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov.u16 r0, q2[5] ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q4[7], r0 ; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.16 q3[5], r0 ; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[4] ; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q0[2] ; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.16 q6[0], r0 ; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q6[1], r0 ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[0] ; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.16 q6[2], r0 ; CHECK-NEXT: vmov.16 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q2[7] ; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.f32 s26, s7 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s8 ; CHECK-NEXT: vmov.f32 s22, s8
; CHECK-NEXT: vmov.f32 s15, s19 ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov q4, q5 ; CHECK-NEXT: vmov q6, q5
; CHECK-NEXT: vmovnb.i32 q4, q6 ; CHECK-NEXT: vmovnb.i32 q6, q4
; CHECK-NEXT: vmov r1, s24 ; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov r0, s18 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov r0, s23
; CHECK-NEXT: vins.f16 s22, s8 ; CHECK-NEXT: vins.f16 s22, s8
; CHECK-NEXT: vmov r1, s25
; CHECK-NEXT: vmovx.f16 s23, s9 ; CHECK-NEXT: vmovx.f16 s23, s9
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
; CHECK-NEXT: vins.f16 s23, s11 ; CHECK-NEXT: vins.f16 s23, s11
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vins.f16 s8, s2 ; CHECK-NEXT: vins.f16 s8, s2
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmovx.f16 s9, s3 ; CHECK-NEXT: vmovx.f16 s9, s3
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vins.f16 s9, s5 ; CHECK-NEXT: vins.f16 s9, s5
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmovnb.i32 q0, q2 ; CHECK-NEXT: vmovnb.i32 q0, q2
; CHECK-NEXT: vmov r1, s8 ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov.f32 s11, s23
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-NEXT: vadd.i16 q0, q3, q2
; CHECK-NEXT: vmov r0, s23
; CHECK-NEXT: vmov r1, s9
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: vadd.i16 q0, q3, q0
; CHECK-NEXT: vadd.i16 q0, q0, q4 ; CHECK-NEXT: vadd.i16 q0, q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a = add <8 x i16> %s1, %s2 %a = add <8 x i16> %s1, %s2
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entry: entry:
%out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> %out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
ret <16 x i8> %out ret <16 x i8> %out
} }
define arm_aapcs_vfpcc <16 x i8> @oneoff11_i8(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @oneoff11_i8(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: oneoff11_i8: ; CHECK-LABEL: oneoff11_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.8 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1] ; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.8 q1[1], r0 ; CHECK-NEXT: vmov.8 q0[2], r0
; CHECK-NEXT: vmov.8 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.8 q1[3], r0
; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %out ret <16 x i8> %out
} }
define arm_aapcs_vfpcc <16 x i8> @oneoff12_i8(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @oneoff12_i8(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: oneoff12_i8: ; CHECK-LABEL: oneoff12_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q1[4] ; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.8 q1[0], r0 ; CHECK-NEXT: vmov.8 q0[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.8 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.8 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.8 q1[3], r0
; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 20, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 20, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %out ret <16 x i8> %out
} }
define arm_aapcs_vfpcc <16 x i8> @oneoff21_i8(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @oneoff21_i8(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: oneoff21_i8: ; CHECK-LABEL: oneoff21_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q1[0] ; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmov.8 q1[3], r0
; CHECK-NEXT: vmov.8 q0[0], r0 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov.u8 r0, q1[1]
; CHECK-NEXT: vmov.8 q0[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.8 q0[2], r0
; CHECK-NEXT: vmov.u8 r0, q2[0]
; CHECK-NEXT: vmov.8 q0[3], r0
; CHECK-NEXT: vmov.f32 s1, s5
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 0, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 0, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <16 x i8> %out ret <16 x i8> %out
} }
define arm_aapcs_vfpcc <16 x i8> @oneoff22_i8(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @oneoff22_i8(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: oneoff22_i8: ; CHECK-LABEL: oneoff22_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov.u8 r0, q1[8] ; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.8 q1[8], r0 ; CHECK-NEXT: vmov.8 q0[9], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.8 q1[9], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.8 q1[10], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.8 q1[11], r0
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 31, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 31, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <16 x i8> %out ret <16 x i8> %out
} }
define arm_aapcs_vfpcc <16 x i8> @oneoffundef_i8(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: oneoffundef_i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.8 q0[1], r0
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 undef, i32 2, i32 2, i32 3, i32 undef, i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 undef, i32 13, i32 14, i32 15>
ret <16 x i8> %out
}
define arm_aapcs_vfpcc <16 x i8> @shuffle2step_i8(<32 x i8> %src) { define arm_aapcs_vfpcc <16 x i8> @shuffle2step_i8(<32 x i8> %src) {
; CHECK-LABEL: shuffle2step_i8: ; CHECK-LABEL: shuffle2step_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q0[0] ; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.8 q2[0], r0 ; CHECK-NEXT: vmov.8 q2[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[2] ; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.8 q2[1], r0 ; CHECK-NEXT: vmov.8 q2[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[4] ; CHECK-NEXT: vmov.u8 r0, q0[4]
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ret <16 x i8> %r ret <16 x i8> %r
} }
define arm_aapcs_vfpcc <16 x i8> @shuffle3step_i8(<64 x i8> %src) { define arm_aapcs_vfpcc <16 x i8> @shuffle3step_i8(<64 x i8> %src) {
; CHECK-LABEL: shuffle3step_i8: ; CHECK-LABEL: shuffle3step_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vmov.u8 r1, q0[1] ; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.8 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vmov.8 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.8 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.8 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.8 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[0]
; CHECK-NEXT: vmov.8 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.8 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.8 q3[7], r0
; CHECK-NEXT: vmov.u8 r0, q1[9] ; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.8 q4[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[4]
; CHECK-NEXT: vmov.8 q4[1], r1
; CHECK-NEXT: vmov.u8 r1, q0[7]
; CHECK-NEXT: vmov.8 q4[2], r1
; CHECK-NEXT: vmov.u8 r1, q0[10]
; CHECK-NEXT: vmov.8 q4[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[13]
; CHECK-NEXT: vmov.8 q3[8], r0 ; CHECK-NEXT: vmov.8 q3[8], r0
; CHECK-NEXT: vmov.u8 r0, q1[12] ; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.8 q4[4], r1
; CHECK-NEXT: vmov.u8 r1, q1[0]
; CHECK-NEXT: vmov.8 q3[9], r0 ; CHECK-NEXT: vmov.8 q3[9], r0
; CHECK-NEXT: vmov.u8 r0, q1[15] ; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.8 q4[5], r1
; CHECK-NEXT: vmov.u8 r1, q1[3]
; CHECK-NEXT: vmov.8 q3[10], r0 ; CHECK-NEXT: vmov.8 q3[10], r0
; CHECK-NEXT: vmov.u8 r0, q2[2]
; CHECK-NEXT: vmov.8 q4[6], r1
; CHECK-NEXT: vmov.u8 r1, q1[6]
; CHECK-NEXT: vmov.8 q3[11], r0
; CHECK-NEXT: vmov.8 q4[7], r1
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov r1, s16
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u8 r0, q2[5] ; CHECK-NEXT: vmov.u8 r0, q2[5]
; CHECK-NEXT: vmov.8 q5[12], r0 ; CHECK-NEXT: vmov.8 q4[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[8] ; CHECK-NEXT: vmov.u8 r0, q2[8]
; CHECK-NEXT: vmov.8 q5[13], r0 ; CHECK-NEXT: vmov.8 q4[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[11] ; CHECK-NEXT: vmov.u8 r0, q2[11]
; CHECK-NEXT: vmov.8 q5[14], r0 ; CHECK-NEXT: vmov.8 q4[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[14] ; CHECK-NEXT: vmov.u8 r0, q2[14]
; CHECK-NEXT: vmov.8 q5[15], r0 ; CHECK-NEXT: vmov.8 q4[15], r0
; CHECK-NEXT: vmov r1, s17 ; CHECK-NEXT: vmov.u8 r0, q2[2]
; CHECK-NEXT: vmov r0, s23 ; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0 ; CHECK-NEXT: vmov.8 q5[11], r0
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.8 q4[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vmov.8 q4[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.8 q4[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.8 q4[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.8 q4[7], r0
; CHECK-NEXT: vmov.u8 r0, q1[8] ; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.8 q4[8], r0 ; CHECK-NEXT: vmov.8 q4[8], r0
; CHECK-NEXT: vmov.u8 r0, q1[11] ; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.8 q4[9], r0 ; CHECK-NEXT: vmov.8 q4[9], r0
; CHECK-NEXT: vmov.u8 r0, q1[14] ; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.8 q4[10], r0 ; CHECK-NEXT: vmov.8 q4[10], r0
; CHECK-NEXT: vmov.u8 r0, q2[1]
; CHECK-NEXT: vmov.8 q4[11], r0
; CHECK-NEXT: vmov.u8 r1, q0[0]
; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vmov.8 q4[0], r1
; CHECK-NEXT: vmov.u8 r1, q0[3]
; CHECK-NEXT: vmov.8 q4[1], r1
; CHECK-NEXT: vmov.u8 r1, q0[6]
; CHECK-NEXT: vmov.8 q4[2], r1
; CHECK-NEXT: vmov.u8 r1, q0[9]
; CHECK-NEXT: vmov.8 q4[3], r1
; CHECK-NEXT: vmov.u8 r1, q0[12]
; CHECK-NEXT: vmov.8 q4[4], r1
; CHECK-NEXT: vmov.u8 r1, q0[15]
; CHECK-NEXT: vmov.8 q4[5], r1
; CHECK-NEXT: vmov.u8 r1, q1[2]
; CHECK-NEXT: vmov.8 q4[6], r1
; CHECK-NEXT: vmov.u8 r1, q1[5]
; CHECK-NEXT: vmov.8 q4[7], r1
; CHECK-NEXT: vmov r1, s16
; CHECK-NEXT: vmov q5[2], q5[0], r1, r0
; CHECK-NEXT: vmov.u8 r0, q2[4] ; CHECK-NEXT: vmov.u8 r0, q2[4]
; CHECK-NEXT: vmov.8 q6[12], r0 ; CHECK-NEXT: vmov.8 q5[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[7] ; CHECK-NEXT: vmov.u8 r0, q2[7]
; CHECK-NEXT: vmov.8 q6[13], r0 ; CHECK-NEXT: vmov.8 q5[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[10] ; CHECK-NEXT: vmov.u8 r0, q2[10]
; CHECK-NEXT: vmov.8 q6[14], r0 ; CHECK-NEXT: vmov.8 q5[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[13] ; CHECK-NEXT: vmov.u8 r0, q2[13]
; CHECK-NEXT: vmov.8 q6[15], r0 ; CHECK-NEXT: vmov.8 q5[15], r0
; CHECK-NEXT: vmov r1, s17 ; CHECK-NEXT: vmov.u8 r0, q2[1]
; CHECK-NEXT: vmov r0, s27 ; CHECK-NEXT: vmov q6, q4
; CHECK-NEXT: vmov q5[3], q5[1], r1, r0 ; CHECK-NEXT: vmov.8 q6[11], r0
; CHECK-NEXT: vmov.u8 r0, q0[2] ; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vadd.i8 q3, q4, q3
; CHECK-NEXT: vmov.8 q4[0], r0 ; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[5] ; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.8 q4[1], r0 ; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[8] ; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmov.8 q4[2], r0 ; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11] ; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.8 q4[3], r0 ; CHECK-NEXT: vmov.8 q4[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[14] ; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.8 q4[4], r0 ; CHECK-NEXT: vmov.8 q4[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[1] ; CHECK-NEXT: vmov.u8 r0, q1[1]
; CHECK-NEXT: vmov.8 q4[5], r0 ; CHECK-NEXT: vmov.8 q4[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[4] ; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.8 q4[6], r0 ; CHECK-NEXT: vmov.8 q4[6], r0
; CHECK-NEXT: vmov.u8 r0, q2[6]
; CHECK-NEXT: vmov.8 q0[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[9]
; CHECK-NEXT: vmov.8 q0[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[12]
; CHECK-NEXT: vmov.8 q0[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[15]
; CHECK-NEXT: vmov.8 q0[15], r0
; CHECK-NEXT: vmov.u8 r0, q1[10] ; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.8 q0[8], r0 ; CHECK-NEXT: vmov.8 q5[8], r0
; CHECK-NEXT: vmov.u8 r0, q1[13] ; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.8 q0[9], r0 ; CHECK-NEXT: vmov.8 q5[9], r0
; CHECK-NEXT: vmov.u8 r0, q2[0] ; CHECK-NEXT: vmov.u8 r0, q2[0]
; CHECK-NEXT: vmov.8 q0[10], r0 ; CHECK-NEXT: vmov.8 q5[10], r0
; CHECK-NEXT: vmov.u8 r0, q2[3] ; CHECK-NEXT: vmov.u8 r0, q2[3]
; CHECK-NEXT: vmov.8 q0[11], r0 ; CHECK-NEXT: vmov.8 q5[11], r0
; CHECK-NEXT: vmov.u8 r0, q1[7] ; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.8 q4[7], r0 ; CHECK-NEXT: vmov.8 q4[7], r0
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov.f32 s18, s22
; CHECK-NEXT: vmov r1, s16 ; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vadd.i8 q3, q5, q3 ; CHECK-NEXT: vadd.i8 q0, q3, q4
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov.u8 r0, q2[6]
; CHECK-NEXT: vmov.8 q1[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[9]
; CHECK-NEXT: vmov.8 q1[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[12]
; CHECK-NEXT: vmov.8 q1[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[15]
; CHECK-NEXT: vmov.8 q1[15], r0
; CHECK-NEXT: vmov r1, s17
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: vadd.i8 q0, q3, q0
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <64 x i8> %src, <64 x i8> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a = add <16 x i8> %s1, %s2 %a = add <16 x i8> %s1, %s2
%r = add <16 x i8> %a, %s3 %r = add <16 x i8> %a, %s3
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entry: entry:
%out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 0, i32 1, i32 1, i32 3> %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 0, i32 1, i32 1, i32 3>
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <4 x float> @oneoff12_f32(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <4 x float> @oneoff12_f32(<4 x float> %src1, <4 x float> %src2) {
; CHECK-LABEL: oneoff12_f32: ; CHECK-LABEL: oneoff12_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s5, s1 ; CHECK-NEXT: vmov.f32 s0, s4
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3> %out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <4 x float> @oneoff21_f32(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <4 x float> @oneoff21_f32(<4 x float> %src1, <4 x float> %src2) {
; CHECK-LABEL: oneoff21_f32: ; CHECK-LABEL: oneoff21_f32:
Show All 36 Linesentry:
ret <4 x float> %r ret <4 x float> %r
} }
define arm_aapcs_vfpcc <4 x float> @shuffle3step_f32(<16 x float> %src) { define arm_aapcs_vfpcc <4 x float> @shuffle3step_f32(<16 x float> %src) {
; CHECKFP-LABEL: shuffle3step_f32: ; CHECKFP-LABEL: shuffle3step_f32:
; CHECKFP: @ %bb.0: @ %entry ; CHECKFP: @ %bb.0: @ %entry
; CHECKFP-NEXT: .vsave {d8, d9} ; CHECKFP-NEXT: .vsave {d8, d9}
; CHECKFP-NEXT: vpush {d8, d9} ; CHECKFP-NEXT: vpush {d8, d9}
; CHECKFP-NEXT: vmov.f32 s12, s1 ; CHECKFP-NEXT: vmov.f32 s14, s8
; CHECKFP-NEXT: vmov.f32 s16, s0 ; CHECKFP-NEXT: vmov.f32 s15, s11
; CHECKFP-NEXT: vmov.f32 s13, s4 ; CHECKFP-NEXT: vmov.f32 s16, s1
; CHECKFP-NEXT: vmov.f32 s17, s3 ; CHECKFP-NEXT: vmov.f32 s12, s2
; CHECKFP-NEXT: vmov.f32 s14, s7 ; CHECKFP-NEXT: vmov.f32 s17, s4
; CHECKFP-NEXT: vmov.f32 s18, s6 ; CHECKFP-NEXT: vmov.f32 s1, s3
; CHECKFP-NEXT: vmov.f32 s4, s2 ; CHECKFP-NEXT: vmov.f32 s18, s7
; CHECKFP-NEXT: vmov.f32 s15, s10 ; CHECKFP-NEXT: vmov.f32 s2, s6
; CHECKFP-NEXT: vmov.f32 s19, s9 ; CHECKFP-NEXT: vmov.f32 s19, s10
; CHECKFP-NEXT: vmov.f32 s10, s8 ; CHECKFP-NEXT: vmov.f32 s3, s9
; CHECKFP-NEXT: vadd.f32 q3, q4, q3 ; CHECKFP-NEXT: vmov.f32 s13, s5
; CHECKFP-NEXT: vmov.f32 s6, s8 ; CHECKFP-NEXT: vadd.f32 q0, q0, q4
; CHECKFP-NEXT: vmov.f32 s7, s11 ; CHECKFP-NEXT: vadd.f32 q0, q0, q3
; CHECKFP-NEXT: vadd.f32 q0, q3, q1
; CHECKFP-NEXT: vpop {d8, d9} ; CHECKFP-NEXT: vpop {d8, d9}
; CHECKFP-NEXT: bx lr ; CHECKFP-NEXT: bx lr
entry: entry:
%s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a = fadd <4 x float> %s1, %s2 %a = fadd <4 x float> %s1, %s2
%r = fadd <4 x float> %a, %s3 %r = fadd <4 x float> %a, %s3
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entry: entry:
%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @oneoff11_f16(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @oneoff11_f16(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: oneoff11_f16: ; CHECK-LABEL: oneoff11_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s1 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s1, s0 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vins.f16 s1, s4 ; CHECK-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @oneoff12_f16(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @oneoff12_f16(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: oneoff12_f16: ; CHECK-LABEL: oneoff12_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: oneoff21_f16: ; CHECK-LABEL: oneoff21_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vins.f16 s5, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15> %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @oneoff22_f16(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @oneoff22_f16(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: oneoff22_f16: ; CHECK-LABEL: oneoff22_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.f32 s0, s3 ; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle2step_f16(<16 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle2step_f16(<16 x half> %src) {
; CHECKFP-LABEL: shuffle2step_f16: ; CHECKFP-LABEL: shuffle2step_f16:
Show All 28 Linesentry:
%s2 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %s2 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%r = fadd <8 x half> %s1, %s2 %r = fadd <8 x half> %s1, %s2
ret <8 x half> %r ret <8 x half> %r
} }
define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
; CHECKFP-LABEL: shuffle3step_f16: ; CHECKFP-LABEL: shuffle3step_f16:
; CHECKFP: @ %bb.0: @ %entry ; CHECKFP: @ %bb.0: @ %entry
; CHECKFP-NEXT: .save {r4, lr}
; CHECKFP-NEXT: push {r4, lr}
; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECKFP-NEXT: vmovx.f16 s16, s2 ; CHECKFP-NEXT: vmovx.f16 s16, s2
; CHECKFP-NEXT: vmov.f32 s12, s1 ; CHECKFP-NEXT: vmov.f32 s12, s1
; CHECKFP-NEXT: vins.f16 s12, s16 ; CHECKFP-NEXT: vins.f16 s12, s16
; CHECKFP-NEXT: vmovx.f16 s16, s5 ; CHECKFP-NEXT: vmovx.f16 s16, s5
; CHECKFP-NEXT: vmov.f32 s13, s4 ; CHECKFP-NEXT: vmov.f32 s13, s4
; CHECKFP-NEXT: vmovx.f16 s20, s11 ; CHECKFP-NEXT: vmovx.f16 s20, s11
Show All 11 Lines
; CHECKFP-NEXT: vins.f16 s21, s24 ; CHECKFP-NEXT: vins.f16 s21, s24
; CHECKFP-NEXT: vmovx.f16 s24, s7 ; CHECKFP-NEXT: vmovx.f16 s24, s7
; CHECKFP-NEXT: vmov.f32 s22, s6 ; CHECKFP-NEXT: vmov.f32 s22, s6
; CHECKFP-NEXT: vins.f16 s22, s24 ; CHECKFP-NEXT: vins.f16 s22, s24
; CHECKFP-NEXT: vmovx.f16 s24, s0 ; CHECKFP-NEXT: vmovx.f16 s24, s0
; CHECKFP-NEXT: vins.f16 s24, s2 ; CHECKFP-NEXT: vins.f16 s24, s2
; CHECKFP-NEXT: vmov.f32 s18, s8 ; CHECKFP-NEXT: vmov.f32 s18, s8
; CHECKFP-NEXT: vmovx.f16 s25, s3 ; CHECKFP-NEXT: vmovx.f16 s25, s3
; CHECKFP-NEXT: vmovx.f16 s3, s9
; CHECKFP-NEXT: vins.f16 s3, s11
; CHECKFP-NEXT: vins.f16 s25, s5
; CHECKFP-NEXT: vmov r3, s3
; CHECKFP-NEXT: vmovx.f16 s0, s10 ; CHECKFP-NEXT: vmovx.f16 s0, s10
; CHECKFP-NEXT: vins.f16 s25, s5
; CHECKFP-NEXT: vmov.f32 s15, s19
; CHECKFP-NEXT: vmovx.f16 s27, s9
; CHECKFP-NEXT: vins.f16 s9, s0 ; CHECKFP-NEXT: vins.f16 s9, s0
; CHECKFP-NEXT: vmovx.f16 s2, s6 ; CHECKFP-NEXT: vins.f16 s27, s11
; CHECKFP-NEXT: vins.f16 s2, s8
; CHECKFP-NEXT: vmov r4, s24
; CHECKFP-NEXT: vmov r0, s2
; CHECKFP-NEXT: vmov r12, s14
; CHECKFP-NEXT: vmov q1[2], q1[0], r4, r0
; CHECKFP-NEXT: vmov lr, s25
; CHECKFP-NEXT: vmov r1, s12
; CHECKFP-NEXT: vmov q1[3], q1[1], lr, r3
; CHECKFP-NEXT: vmov.f32 s23, s9 ; CHECKFP-NEXT: vmov.f32 s23, s9
; CHECKFP-NEXT: vmov q0[2], q0[0], r1, r12 ; CHECKFP-NEXT: vmovx.f16 s26, s6
; CHECKFP-NEXT: vmov r1, s13 ; CHECKFP-NEXT: vins.f16 s26, s8
; CHECKFP-NEXT: vadd.f16 q1, q5, q1 ; CHECKFP-NEXT: vadd.f16 q0, q5, q6
; CHECKFP-NEXT: vmov r2, s19 ; CHECKFP-NEXT: vadd.f16 q0, q0, q3
; CHECKFP-NEXT: vmov q0[3], q0[1], r1, r2
; CHECKFP-NEXT: vadd.f16 q0, q1, q0
; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECKFP-NEXT: pop {r4, pc} ; CHECKFP-NEXT: bx lr
entry: entry:
%s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a = fadd <8 x half> %s1, %s2 %a = fadd <8 x half> %s1, %s2
%r = fadd <8 x half> %a, %s3 %r = fadd <8 x half> %a, %s3
ret <8 x half> %r ret <8 x half> %r
} }
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Linesentry:
ret <2 x double> %res ret <2 x double> %res
} }
define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) { define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) {
; CHECK-LABEL: scalar_to_vector_i32: ; CHECK-LABEL: scalar_to_vector_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #8 ; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: adr r1, .LCPI73_0 ; CHECK-NEXT: adr r2, .LCPI76_0
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vldrw.u32 q1, [r1] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: mov r1, sp
; CHECK-NEXT: vmov.32 q0[0], r0 ; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: mov r2, sp ; CHECK-NEXT: vstrh.32 q0, [r1]
; CHECK-NEXT: vmov.f32 s1, s5
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vstrh.32 q0, [r2]
; CHECK-NEXT: ldrd r0, r1, [sp], #8 ; CHECK-NEXT: ldrd r0, r1, [sp], #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI73_0: ; CHECK-NEXT: .LCPI76_0:
; CHECK-NEXT: .zero 4 ; CHECK-NEXT: .zero 4
; CHECK-NEXT: .long 7 @ 0x7 ; CHECK-NEXT: .long 7 @ 0x7
; CHECK-NEXT: .long 1 @ 0x1 ; CHECK-NEXT: .long 1 @ 0x1
; CHECK-NEXT: .long 9 @ 0x9 ; CHECK-NEXT: .long 9 @ 0x9
entry: entry:
%f = shufflevector <8 x i16> %v, <8 x i16> <i16 undef, i16 7, i16 1, i16 9, i16 undef, i16 undef, i16 undef, i16 undef>, <4 x i32> <i32 0, i32 9, i32 10, i32 11> %f = shufflevector <8 x i16> %v, <8 x i16> <i16 undef, i16 7, i16 1, i16 9, i16 undef, i16 undef, i16 undef, i16 undef>, <4 x i32> <i32 0, i32 9, i32 10, i32 11>
%0 = bitcast <4 x i16> %f to i64 %0 = bitcast <4 x i16> %f to i64
ret i64 %0 ret i64 %0
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llvm/test/CodeGen/Thumb2/mve-vld3.ll

Show All 28 Linesentry:
%a = add <2 x i32> %a1, %s3 %a = add <2 x i32> %a1, %s3
store <2 x i32> %a, <2 x i32> *%dst store <2 x i32> %a, <2 x i32> *%dst
ret void ret void
} }
define void @vld3_v4i32(<12 x i32> *%src, <4 x i32> *%dst) { define void @vld3_v4i32(<12 x i32> *%src, <4 x i32> *%dst) {
; CHECK-LABEL: vld3_v4i32: ; CHECK-LABEL: vld3_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f64 d3, d0
; CHECK-NEXT: vmov.f32 s13, s0 ; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov r0, s10 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s17, s12
; CHECK-NEXT: vmov.f32 s15, s19 ; CHECK-NEXT: vmov.f32 s9, s11
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov r0, s9 ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vdup.32 q5, r0 ; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vadd.i32 q0, q2, q4
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.i32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vadd.i32 q0, q3, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <12 x i32>, <12 x i32>* %src, align 4 %l1 = load <12 x i32>, <12 x i32>* %src, align 4
%s1 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = add <4 x i32> %s1, %s2 %a1 = add <4 x i32> %s1, %s2
%a = add <4 x i32> %a1, %s3 %a = add <4 x i32> %a1, %s3
store <4 x i32> %a, <4 x i32> *%dst store <4 x i32> %a, <4 x i32> *%dst
ret void ret void
} }
define void @vld3_v8i32(<24 x i32> *%src, <8 x i32> *%dst) { define void @vld3_v8i32(<24 x i32> *%src, <8 x i32> *%dst) {
; CHECK-LABEL: vld3_v8i32: ; CHECK-LABEL: vld3_v8i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q3, [r0, #64]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f64 d3, d0
; CHECK-NEXT: vmov.f32 s13, s0 ; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: vdup.32 q4, r2
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.i32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.i32 q0, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vdup.32 q5, r0
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s17, s12
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s9, s11
; CHECK-NEXT: vadd.i32 q4, q5, q4 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vadd.i32 q1, q4, q1 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vadd.i32 q0, q2, q4
; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vmov.f64 d5, d2
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s21, s16
; CHECK-NEXT: vmov.f32 s13, s15
; CHECK-NEXT: vmov.f32 s22, s19
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.f32 s23, s6
; CHECK-NEXT: vmov.f32 s15, s5
; CHECK-NEXT: vmov.f32 s9, s17
; CHECK-NEXT: vadd.i32 q1, q3, q5
; CHECK-NEXT: vadd.i32 q1, q1, q2
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x i32>, <24 x i32>* %src, align 4 %l1 = load <24 x i32>, <24 x i32>* %src, align 4
%s1 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = add <8 x i32> %s1, %s2 %a1 = add <8 x i32> %s1, %s2
%a = add <8 x i32> %a1, %s3 %a = add <8 x i32> %a1, %s3
store <8 x i32> %a, <8 x i32> *%dst store <8 x i32> %a, <8 x i32> *%dst
ret void ret void
} }
define void @vld3_v16i32(<48 x i32> *%src, <16 x i32> *%dst) { define void @vld3_v16i32(<48 x i32> *%src, <16 x i32> *%dst) {
; CHECK-LABEL: vld3_v16i32: ; CHECK-LABEL: vld3_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q3, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vmov.f64 d3, d0
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: vdup.32 q4, r2
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.i32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.i32 q0, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vldrw.u32 q0, [r0, #128]
; CHECK-NEXT: vmov r2, s14
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vdup.32 q6, r2
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vmov.f32 s17, s12
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s9, s11
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vadd.i32 q4, q5, q4 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vldrw.u32 q3, [r0, #144] ; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vadd.i32 q1, q4, q1 ; CHECK-NEXT: vadd.i32 q0, q2, q4
; CHECK-NEXT: vldrw.u32 q4, [r0, #176] ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vmov.f64 d5, d2
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s20, s13 ; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: vdup.32 q6, r2
; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov.f64 d12, d6
; CHECK-NEXT: vmov.f32 s25, s15
; CHECK-NEXT: vmov r2, s17
; CHECK-NEXT: vmov.f32 s26, s10
; CHECK-NEXT: vdup.32 q7, r2
; CHECK-NEXT: vmov.f32 s8, s14 ; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s27, s31 ; CHECK-NEXT: vmov.f32 s21, s16
; CHECK-NEXT: vmov.f32 s18, s16 ; CHECK-NEXT: vmov.f32 s13, s15
; CHECK-NEXT: vadd.i32 q5, q6, q5 ; CHECK-NEXT: vmov.f32 s22, s19
; CHECK-NEXT: vmov.f32 s10, s16 ; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.f32 s11, s19 ; CHECK-NEXT: vmov.f32 s23, s6
; CHECK-NEXT: vldrw.u32 q4, [r0, #96] ; CHECK-NEXT: vmov.f32 s15, s5
; CHECK-NEXT: vadd.i32 q2, q5, q2 ; CHECK-NEXT: vmov.f32 s9, s17
; CHECK-NEXT: vldrw.u32 q5, [r0, #112] ; CHECK-NEXT: vadd.i32 q1, q3, q5
; CHECK-NEXT: vadd.i32 q1, q1, q2
; CHECK-NEXT: vldrw.u32 q2, [r0, #176]
; CHECK-NEXT: vldrw.u32 q4, [r0, #144]
; CHECK-NEXT: vldrw.u32 q5, [r0, #160]
; CHECK-NEXT: vmov.f64 d7, d4
; CHECK-NEXT: vmov.f32 s15, s11
; CHECK-NEXT: vmov.f32 s24, s17 ; CHECK-NEXT: vmov.f32 s24, s17
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vmov.f32 s12, s18
; CHECK-NEXT: vmov.f32 s25, s20 ; CHECK-NEXT: vmov.f32 s25, s20
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vmov.f32 s17, s19
; CHECK-NEXT: vmov.f64 d6, d8
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.f32 s13, s19
; CHECK-NEXT: vdup.32 q7, r0
; CHECK-NEXT: vmov.f32 s26, s23 ; CHECK-NEXT: vmov.f32 s26, s23
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov.f32 s18, s22
; CHECK-NEXT: vmov.f32 s27, s31 ; CHECK-NEXT: vmov.f32 s27, s10
; CHECK-NEXT: vdup.32 q7, r0 ; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vmov.f32 s14, s22 ; CHECK-NEXT: vmov.f32 s13, s21
; CHECK-NEXT: vmov.f32 s20, s18 ; CHECK-NEXT: vadd.i32 q2, q4, q6
; CHECK-NEXT: vmov.f32 s15, s31 ; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vmov.f32 s2, s0 ; CHECK-NEXT: vldrw.u32 q3, [r0, #128]
; CHECK-NEXT: vadd.i32 q6, q3, q6 ; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vmov.f32 s22, s0 ; CHECK-NEXT: vldrw.u32 q6, [r0, #112]
; CHECK-NEXT: vmov.f32 s23, s3 ; CHECK-NEXT: vmov.f64 d9, d6
; CHECK-NEXT: vadd.i32 q0, q6, q5 ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s19, s15
; CHECK-NEXT: vmov.f32 s28, s21
; CHECK-NEXT: vmov.f32 s16, s22
; CHECK-NEXT: vmov.f32 s29, s24
; CHECK-NEXT: vmov.f32 s21, s23
; CHECK-NEXT: vmov.f32 s30, s27
; CHECK-NEXT: vmov.f32 s22, s26
; CHECK-NEXT: vmov.f32 s31, s14
; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s17, s25
; CHECK-NEXT: vadd.i32 q3, q5, q7
; CHECK-NEXT: vadd.i32 q3, q3, q4
; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x i32>, <48 x i32>* %src, align 4 %l1 = load <48 x i32>, <48 x i32>* %src, align 4
%s1 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = add <16 x i32> %s1, %s2 %a1 = add <16 x i32> %s1, %s2
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Linesentry:
%a = add <4 x i16> %a1, %s3 %a = add <4 x i16> %a1, %s3
store <4 x i16> %a, <4 x i16> *%dst store <4 x i16> %a, <4 x i16> *%dst
ret void ret void
} }
define void @vld3_v8i16(<24 x i16> *%src, <8 x i16> *%dst) { define void @vld3_v8i16(<24 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld3_v8i16: ; CHECK-LABEL: vld3_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.16 q4[0], r0 ; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[5] ; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.16 q4[1], r0 ; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[0] ; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[4] ; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q0[7] ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vmovnb.i32 q3, q4
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov q3[2], q3[0], r2, r0
; CHECK-NEXT: vmov r0, s23
; CHECK-NEXT: vmov r2, s17
; CHECK-NEXT: vmov q3[3], q3[1], r2, r0
; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vmov.16 q4[0], r0 ; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[3] ; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vmov.16 q4[1], r0 ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[6] ; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.f32 s2, s11
; CHECK-NEXT: vmov q6, q5
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vmov.16 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[1] ; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmovnb.i32 q6, q0
; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vmov.f32 s2, s26
; CHECK-NEXT: vmov.16 q4[4], r0 ; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmov.u16 r0, q0[2] ; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov.f32 s3, s23
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmov.16 q4[5], r0 ; CHECK-NEXT: vmov.16 q4[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmovx.f16 s20, s8 ; CHECK-NEXT: vmovx.f16 s20, s12
; CHECK-NEXT: vins.f16 s20, s10 ; CHECK-NEXT: vins.f16 s20, s14
; CHECK-NEXT: vmovx.f16 s21, s11 ; CHECK-NEXT: vmovx.f16 s21, s15
; CHECK-NEXT: vins.f16 s21, s5 ; CHECK-NEXT: vins.f16 s21, s9
; CHECK-NEXT: vins.f16 s6, s0 ; CHECK-NEXT: vins.f16 s10, s4
; CHECK-NEXT: vmovx.f16 s7, s1 ; CHECK-NEXT: vmovx.f16 s11, s5
; CHECK-NEXT: vmov.16 q5[4], r0 ; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vins.f16 s7, s3 ; CHECK-NEXT: vins.f16 s11, s7
; CHECK-NEXT: vmov r2, s20 ; CHECK-NEXT: vmov q1, q2
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmovnb.i32 q1, q5
; CHECK-NEXT: vmovnb.i32 q0, q5 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov.f32 s23, s11
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0 ; CHECK-NEXT: vadd.i16 q1, q4, q5
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vadd.i16 q0, q1, q0
; CHECK-NEXT: vmov r2, s21
; CHECK-NEXT: vmov q0[3], q0[1], r2, r0
; CHECK-NEXT: vadd.i16 q0, q4, q0
; CHECK-NEXT: vadd.i16 q0, q0, q3
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x i16>, <24 x i16>* %src, align 4 %l1 = load <24 x i16>, <24 x i16>* %src, align 4
%s1 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = add <8 x i16> %s1, %s2 %a1 = add <8 x i16> %s1, %s2
%a = add <8 x i16> %a1, %s3 %a = add <8 x i16> %a1, %s3
store <8 x i16> %a, <8 x i16> *%dst store <8 x i16> %a, <8 x i16> *%dst
ret void ret void
} }
define void @vld3_v16i16(<48 x i16> *%src, <16 x i16> *%dst) { define void @vld3_v16i16(<48 x i16> *%src, <16 x i16> *%dst) {
; CHECK-LABEL: vld3_v16i16: ; CHECK-LABEL: vld3_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q2, [r0, #48] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vldrw.u32 q3, [r0, #80] ; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
; CHECK-NEXT: vmov.u16 r2, q2[0] ; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[3] ; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov.16 q1[1], r2 ; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[6] ; CHECK-NEXT: vmov.u16 r2, q2[6]
; CHECK-NEXT: vmov.16 q1[2], r2 ; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov.u16 r2, q0[1] ; CHECK-NEXT: vmov.u16 r2, q1[1]
; CHECK-NEXT: vmov.16 q1[3], r2 ; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vmov.u16 r2, q0[4] ; CHECK-NEXT: vmov.u16 r2, q1[4]
; CHECK-NEXT: vmov.16 q1[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.u16 r2, q3[2] ; CHECK-NEXT: vmov.u16 r2, q3[2]
; CHECK-NEXT: vmov.16 q4[6], r2 ; CHECK-NEXT: vmov.16 q4[6], r2
; CHECK-NEXT: vmov.u16 r2, q3[5] ; CHECK-NEXT: vmov.u16 r2, q3[5]
; CHECK-NEXT: vmov.16 q4[7], r2 ; CHECK-NEXT: vmov.16 q4[7], r2
; CHECK-NEXT: vmov.u16 r2, q0[7] ; CHECK-NEXT: vmov.u16 r2, q1[7]
; CHECK-NEXT: vmov.16 q1[5], r2 ; CHECK-NEXT: vmov.16 q0[5], r2
; CHECK-NEXT: vmov.u16 r2, q3[4] ; CHECK-NEXT: vmov.u16 r2, q3[4]
; CHECK-NEXT: vmov.16 q5[6], r2 ; CHECK-NEXT: vmov.16 q5[6], r2
; CHECK-NEXT: vmov.u16 r2, q2[2] ; CHECK-NEXT: vmov.u16 r2, q2[2]
; CHECK-NEXT: vmov.16 q6[0], r2 ; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vmov.16 q4[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5] ; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.16 q6[1], r2 ; CHECK-NEXT: vmov.16 q4[1], r2
; CHECK-NEXT: vmov.u16 r2, q0[0] ; CHECK-NEXT: vmov.u16 r2, q1[0]
; CHECK-NEXT: vmov.16 q6[2], r2 ; CHECK-NEXT: vmov.16 q4[2], r2
; CHECK-NEXT: vmov.u16 r2, q0[3] ; CHECK-NEXT: vmov.u16 r2, q1[3]
; CHECK-NEXT: vmov.16 q6[3], r2 ; CHECK-NEXT: vmov.16 q4[3], r2
; CHECK-NEXT: vmov.u16 r2, q3[7] ; CHECK-NEXT: vmov.u16 r2, q3[7]
; CHECK-NEXT: vmov.16 q5[7], r2 ; CHECK-NEXT: vmov.16 q5[7], r2
; CHECK-NEXT: vmov.f32 s26, s3 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s12 ; CHECK-NEXT: vmov.f32 s22, s12
; CHECK-NEXT: vmov.f32 s7, s19 ; CHECK-NEXT: vmov.u16 r2, q1[5]
; CHECK-NEXT: vmov q4, q5 ; CHECK-NEXT: vmov q6, q5
; CHECK-NEXT: vmovnb.i32 q4, q6 ; CHECK-NEXT: vmovnb.i32 q6, q4
; CHECK-NEXT: vmov r3, s24 ; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov r2, s18 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov q4[2], q4[0], r3, r2
; CHECK-NEXT: vmov r2, s23
; CHECK-NEXT: vins.f16 s22, s12 ; CHECK-NEXT: vins.f16 s22, s12
; CHECK-NEXT: vmov r3, s25
; CHECK-NEXT: vmovx.f16 s23, s13 ; CHECK-NEXT: vmovx.f16 s23, s13
; CHECK-NEXT: vmov q4[3], q4[1], r3, r2
; CHECK-NEXT: vins.f16 s23, s15 ; CHECK-NEXT: vins.f16 s23, s15
; CHECK-NEXT: vmovx.f16 s12, s8 ; CHECK-NEXT: vmovx.f16 s12, s8
; CHECK-NEXT: vins.f16 s12, s10 ; CHECK-NEXT: vins.f16 s12, s10
; CHECK-NEXT: vmov.u16 r2, q0[5]
; CHECK-NEXT: vmovx.f16 s13, s11 ; CHECK-NEXT: vmovx.f16 s13, s11
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vins.f16 s13, s1 ; CHECK-NEXT: vins.f16 s13, s5
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q1, q5
; CHECK-NEXT: vmov.16 q3[4], r2 ; CHECK-NEXT: vmov.16 q3[4], r2
; CHECK-NEXT: vmovnb.i32 q0, q3 ; CHECK-NEXT: vmovnb.i32 q1, q3
; CHECK-NEXT: vmov r3, s12 ; CHECK-NEXT: vmov.f32 s14, s6
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmov.f32 s15, s23
; CHECK-NEXT: vmov q0[2], q0[0], r3, r2
; CHECK-NEXT: vmov r2, s23
; CHECK-NEXT: vmov r3, s13
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-NEXT: vadd.i16 q0, q0, q3
; CHECK-NEXT: vmov.u16 r2, q2[2] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vadd.i16 q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.16 q3[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.u16 r0, q5[4] ; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vmov.16 q3[1], r2 ; CHECK-NEXT: vadd.i16 q0, q0, q4
; CHECK-NEXT: vmov.u16 r2, q1[0] ; CHECK-NEXT: vmov.u16 r2, q3[2]
; CHECK-NEXT: vmov.16 q6[6], r0 ; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vmov.u16 r2, q3[5]
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vmov.u16 r0, q5[7] ; CHECK-NEXT: vmov.u16 r0, q5[7]
; CHECK-NEXT: vmov.16 q3[2], r2 ; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov.16 q6[7], r0 ; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov.u16 r2, q1[3]
; CHECK-NEXT: vmov.16 q3[3], r2
; CHECK-NEXT: vmov.f32 s26, s20
; CHECK-NEXT: vadd.i16 q0, q0, q4
; CHECK-NEXT: vmov.f32 s14, s7
; CHECK-NEXT: vmov q4, q6
; CHECK-NEXT: vmov.u16 r2, q2[0]
; CHECK-NEXT: vmovnb.i32 q4, q3
; CHECK-NEXT: vmov r3, s27
; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vmov.16 q4[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[3] ; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov.16 q4[1], r2 ; CHECK-NEXT: vmov.f32 s26, s20
; CHECK-NEXT: vmov.u16 r2, q2[6] ; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.16 q4[2], r2 ; CHECK-NEXT: vmov.f32 s6, s11
; CHECK-NEXT: vmov.u16 r2, q1[1] ; CHECK-NEXT: vmov q7, q6
; CHECK-NEXT: vmov.16 q4[3], r2 ; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov.u16 r2, q1[4] ; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.16 q4[4], r2 ; CHECK-NEXT: vmovnb.i32 q7, q1
; CHECK-NEXT: vmov.u16 r2, q5[2] ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov.16 q7[6], r2 ; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.u16 r2, q5[5] ; CHECK-NEXT: vmov.f32 s6, s30
; CHECK-NEXT: vmov.16 q7[7], r2 ; CHECK-NEXT: vmov.16 q4[2], r0
; CHECK-NEXT: vmov.u16 r2, q1[7] ; CHECK-NEXT: vmov.u16 r0, q2[1]
; CHECK-NEXT: vmov.16 q4[5], r2 ; CHECK-NEXT: vmov.f32 s7, s27
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vins.f16 s26, s20
; CHECK-NEXT: vmov q6[2], q6[0], r2, r0 ; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov r0, s13 ; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vins.f16 s14, s20 ; CHECK-NEXT: vmovx.f16 s27, s21
; CHECK-NEXT: vmov q6[3], q6[1], r0, r3 ; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmovx.f16 s15, s21 ; CHECK-NEXT: vmov.u16 r0, q5[2]
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s15, s23 ; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmovx.f16 s20, s8 ; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vins.f16 s20, s10 ; CHECK-NEXT: vins.f16 s27, s23
; CHECK-NEXT: vmov.f32 s19, s31 ; CHECK-NEXT: vmovx.f16 s20, s12
; CHECK-NEXT: vmovx.f16 s21, s11 ; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vins.f16 s21, s5 ; CHECK-NEXT: vins.f16 s20, s14
; CHECK-NEXT: vmov q1, q3 ; CHECK-NEXT: vmov.u16 r0, q2[7]
; CHECK-NEXT: vmovx.f16 s21, s15
; CHECK-NEXT: vmov.16 q4[5], r0
; CHECK-NEXT: vins.f16 s21, s9
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmov.16 q5[4], r0 ; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmovnb.i32 q1, q5 ; CHECK-NEXT: vmov q0, q6
; CHECK-NEXT: vmov r2, s20 ; CHECK-NEXT: vmovnb.i32 q0, q5
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov.f32 s22, s2
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0 ; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov r0, s15 ; CHECK-NEXT: vadd.i16 q0, q4, q5
; CHECK-NEXT: vmov r2, s21 ; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vmov q1[3], q1[1], r2, r0 ; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vadd.i16 q1, q4, q1 ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vadd.i16 q1, q1, q6 ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x i16>, <48 x i16>* %src, align 4 %l1 = load <48 x i16>, <48 x i16>* %src, align 4
%s1 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = add <16 x i16> %s1, %s2 %a1 = add <16 x i16> %s1, %s2
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Linesentry:
%a = add <8 x i8> %a1, %s3 %a = add <8 x i8> %a1, %s3
store <8 x i8> %a, <8 x i8> *%dst store <8 x i8> %a, <8 x i8> *%dst
ret void ret void
} }
define void @vld3_v16i8(<48 x i8> *%src, <16 x i8> *%dst) { define void @vld3_v16i8(<48 x i8> *%src, <16 x i8> *%dst) {
; CHECK-LABEL: vld3_v16i8: ; CHECK-LABEL: vld3_v16i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vmov.u8 r2, q0[0] ; CHECK-NEXT: vmov.u8 r2, q1[1]
; CHECK-NEXT: vmov.8 q3[0], r2 ; CHECK-NEXT: vmov.8 q3[0], r2
; CHECK-NEXT: vmov.u8 r2, q0[3] ; CHECK-NEXT: vmov.u8 r2, q1[4]
; CHECK-NEXT: vmov.8 q3[1], r2 ; CHECK-NEXT: vmov.8 q3[1], r2
; CHECK-NEXT: vmov.u8 r2, q0[6] ; CHECK-NEXT: vmov.u8 r2, q1[7]
; CHECK-NEXT: vmov.8 q3[2], r2 ; CHECK-NEXT: vmov.8 q3[2], r2
; CHECK-NEXT: vmov.u8 r2, q0[9] ; CHECK-NEXT: vmov.u8 r2, q1[10]
; CHECK-NEXT: vmov.8 q3[3], r2 ; CHECK-NEXT: vmov.8 q3[3], r2
; CHECK-NEXT: vmov.u8 r2, q0[12] ; CHECK-NEXT: vmov.u8 r2, q1[13]
; CHECK-NEXT: vmov.8 q3[4], r2 ; CHECK-NEXT: vmov.8 q3[4], r2
; CHECK-NEXT: vmov.u8 r2, q0[15] ; CHECK-NEXT: vmov.u8 r2, q0[0]
; CHECK-NEXT: vmov.8 q3[5], r2 ; CHECK-NEXT: vmov.8 q3[5], r2
; CHECK-NEXT: vmov.u8 r2, q2[2] ; CHECK-NEXT: vmov.u8 r2, q0[3]
; CHECK-NEXT: vmov.8 q3[6], r2 ; CHECK-NEXT: vmov.8 q3[6], r2
; CHECK-NEXT: vmov.u8 r2, q2[8] ; CHECK-NEXT: vmov.u8 r2, q0[6]
; CHECK-NEXT: vmov.8 q4[8], r2 ; CHECK-NEXT: vmov.8 q3[7], r2
; CHECK-NEXT: vmov.u8 r2, q2[11] ; CHECK-NEXT: vmov.u8 r2, q0[9]
; CHECK-NEXT: vmov.8 q4[9], r2
; CHECK-NEXT: vmov.u8 r2, q2[14]
; CHECK-NEXT: vmov.8 q4[10], r2
; CHECK-NEXT: vmov.u8 r0, q1[1]
; CHECK-NEXT: vmov.8 q4[11], r0
; CHECK-NEXT: vmov.u8 r0, q2[5] ; CHECK-NEXT: vmov.u8 r0, q2[5]
; CHECK-NEXT: vmov.8 q3[7], r0 ; CHECK-NEXT: vmov.8 q3[8], r2
; CHECK-NEXT: vmov r0, s18 ; CHECK-NEXT: vmov.u8 r2, q0[12]
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmov.8 q4[12], r0
; CHECK-NEXT: vmov q4[2], q4[0], r2, r0 ; CHECK-NEXT: vmov.u8 r0, q2[8]
; CHECK-NEXT: vmov.u8 r0, q2[9] ; CHECK-NEXT: vmov.8 q3[9], r2
; CHECK-NEXT: vmov.8 q5[8], r0 ; CHECK-NEXT: vmov.u8 r2, q0[15]
; CHECK-NEXT: vmov.u8 r0, q2[12] ; CHECK-NEXT: vmov.8 q4[13], r0
; CHECK-NEXT: vmov.8 q5[9], r0 ; CHECK-NEXT: vmov.u8 r0, q2[11]
; CHECK-NEXT: vmov.u8 r0, q2[15] ; CHECK-NEXT: vmov.8 q3[10], r2
; CHECK-NEXT: vmov.8 q5[10], r0 ; CHECK-NEXT: vmov.8 q4[14], r0
; CHECK-NEXT: vmov.u8 r0, q1[2] ; CHECK-NEXT: vmov.u8 r0, q2[14]
; CHECK-NEXT: vmov.8 q4[15], r0
; CHECK-NEXT: vmov.u8 r0, q2[2]
; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vmov.8 q5[11], r0 ; CHECK-NEXT: vmov.8 q5[11], r0
; CHECK-NEXT: vmov.u8 r2, q0[1]
; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: vmov.8 q5[0], r2
; CHECK-NEXT: vmov.u8 r2, q0[4]
; CHECK-NEXT: vmov.8 q5[1], r2
; CHECK-NEXT: vmov.u8 r2, q0[7]
; CHECK-NEXT: vmov.8 q5[2], r2
; CHECK-NEXT: vmov.u8 r2, q0[10]
; CHECK-NEXT: vmov.8 q5[3], r2
; CHECK-NEXT: vmov.u8 r2, q0[13]
; CHECK-NEXT: vmov.8 q5[4], r2
; CHECK-NEXT: vmov.u8 r2, q2[0]
; CHECK-NEXT: vmov.8 q5[5], r2
; CHECK-NEXT: vmov.u8 r2, q2[3]
; CHECK-NEXT: vmov.8 q5[6], r2
; CHECK-NEXT: vmov.u8 r2, q2[6]
; CHECK-NEXT: vmov.8 q5[7], r2
; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmov q6[2], q6[0], r2, r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.8 q7[12], r0
; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.8 q7[13], r0
; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.8 q7[14], r0
; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.8 q7[15], r0
; CHECK-NEXT: vmov r2, s21
; CHECK-NEXT: vmov r0, s31
; CHECK-NEXT: vmov q6[3], q6[1], r2, r0
; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.8 q5[12], r0
; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.8 q5[13], r0
; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.8 q5[14], r0
; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.8 q5[15], r0
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: vmov r0, s23
; CHECK-NEXT: vmov q4[3], q4[1], r2, r0
; CHECK-NEXT: vmov.u8 r0, q2[10]
; CHECK-NEXT: vadd.i8 q3, q4, q6
; CHECK-NEXT: vmov.8 q4[8], r0
; CHECK-NEXT: vmov.u8 r0, q2[13]
; CHECK-NEXT: vmov.u8 r2, q0[2]
; CHECK-NEXT: vmov.8 q4[9], r0
; CHECK-NEXT: vmov.u8 r0, q1[0] ; CHECK-NEXT: vmov.u8 r0, q1[0]
; CHECK-NEXT: vmov.8 q4[10], r0 ; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[3] ; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.8 q4[11], r0 ; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vmov.8 q4[0], r2
; CHECK-NEXT: vmov.u8 r2, q0[5]
; CHECK-NEXT: vmov.8 q4[1], r2
; CHECK-NEXT: vmov.u8 r2, q0[8]
; CHECK-NEXT: vmov.8 q4[2], r2
; CHECK-NEXT: vmov.u8 r2, q0[11]
; CHECK-NEXT: vmov.8 q4[3], r2
; CHECK-NEXT: vmov.u8 r2, q0[14]
; CHECK-NEXT: vmov.8 q4[4], r2
; CHECK-NEXT: vmov.u8 r2, q2[1]
; CHECK-NEXT: vmov.8 q4[5], r2
; CHECK-NEXT: vmov.u8 r2, q2[4]
; CHECK-NEXT: vmov.8 q4[6], r2
; CHECK-NEXT: vmov.u8 r2, q2[7]
; CHECK-NEXT: vmov.8 q4[7], r2
; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: vmov.u8 r0, q1[6] ; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.8 q2[12], r0 ; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[9] ; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.8 q2[13], r0 ; CHECK-NEXT: vmov.8 q4[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[12] ; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.8 q2[14], r0 ; CHECK-NEXT: vmov.8 q4[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[15] ; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.8 q2[15], r0 ; CHECK-NEXT: vmov.8 q4[5], r0
; CHECK-NEXT: vmov r2, s17 ; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vmov.8 q4[6], r0
; CHECK-NEXT: vmov q0[3], q0[1], r2, r0 ; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vadd.i8 q0, q3, q0 ; CHECK-NEXT: vmov.8 q4[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmov.8 q4[8], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.8 q4[9], r0
; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.8 q4[10], r0
; CHECK-NEXT: vmov.u8 r0, q2[4]
; CHECK-NEXT: vmov.8 q5[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[7]
; CHECK-NEXT: vmov.8 q5[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[10]
; CHECK-NEXT: vmov.8 q5[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[13]
; CHECK-NEXT: vmov.8 q5[15], r0
; CHECK-NEXT: vmov.u8 r0, q2[1]
; CHECK-NEXT: vmov q6, q4
; CHECK-NEXT: vmov.8 q6[11], r0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vadd.i8 q3, q4, q3
; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.8 q4[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.8 q4[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.8 q4[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vmov.8 q4[6], r0
; CHECK-NEXT: vmov.u8 r0, q2[6]
; CHECK-NEXT: vmov.8 q1[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[9]
; CHECK-NEXT: vmov.8 q1[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[12]
; CHECK-NEXT: vmov.8 q1[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[15]
; CHECK-NEXT: vmov.8 q1[15], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.8 q5[8], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.8 q5[9], r0
; CHECK-NEXT: vmov.u8 r0, q2[0]
; CHECK-NEXT: vmov.8 q5[10], r0
; CHECK-NEXT: vmov.u8 r0, q2[3]
; CHECK-NEXT: vmov.8 q5[11], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.8 q4[7], r0
; CHECK-NEXT: vmov.f32 s18, s22
; CHECK-NEXT: vmov.f32 s19, s7
; CHECK-NEXT: vadd.i8 q0, q3, q4
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x i8>, <48 x i8>* %src, align 4 %l1 = load <48 x i8>, <48 x i8>* %src, align 4
%s1 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x i8> %l1, <48 x i8> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = add <16 x i8> %s1, %s2 %a1 = add <16 x i8> %s1, %s2
%a = add <16 x i8> %a1, %s3 %a = add <16 x i8> %a1, %s3
▲ Show 20 Lines • Show All 183 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @vld3_v4f32(<12 x float> *%src, <4 x float> *%dst) { define void @vld3_v4f32(<12 x float> *%src, <4 x float> *%dst) {
; CHECK-LABEL: vld3_v4f32: ; CHECK-LABEL: vld3_v4f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f64 d3, d0
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov.f32 s13, s0 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s17, s12
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s9, s11
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmov.f32 s15, s10 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s19, s9 ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vmov.f32 s10, s8 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vadd.f32 q3, q4, q3 ; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vadd.f32 q0, q2, q4
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vadd.f32 q0, q3, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <12 x float>, <12 x float>* %src, align 4 %l1 = load <12 x float>, <12 x float>* %src, align 4
%s1 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = fadd <4 x float> %s1, %s2 %a1 = fadd <4 x float> %s1, %s2
%a = fadd <4 x float> %a1, %s3 %a = fadd <4 x float> %a1, %s3
store <4 x float> %a, <4 x float> *%dst store <4 x float> %a, <4 x float> *%dst
ret void ret void
} }
define void @vld3_v8f32(<24 x float> *%src, <8 x float> *%dst) { define void @vld3_v8f32(<24 x float> *%src, <8 x float> *%dst) {
; CHECK-LABEL: vld3_v8f32: ; CHECK-LABEL: vld3_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vldrw.u32 q3, [r0, #64]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f64 d3, d0
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s15, s10
; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.f32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.f32 q0, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s19, s14 ; CHECK-NEXT: vmov.f32 s17, s12
; CHECK-NEXT: vmov.f32 s23, s13 ; CHECK-NEXT: vmov.f32 s9, s11
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vadd.f32 q4, q5, q4 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vadd.f32 q1, q4, q1 ; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vadd.f32 q0, q2, q4
; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vmov.f64 d5, d2
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s21, s16
; CHECK-NEXT: vmov.f32 s13, s15
; CHECK-NEXT: vmov.f32 s22, s19
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.f32 s23, s6
; CHECK-NEXT: vmov.f32 s15, s5
; CHECK-NEXT: vmov.f32 s9, s17
; CHECK-NEXT: vadd.f32 q1, q3, q5
; CHECK-NEXT: vadd.f32 q1, q1, q2
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x float>, <24 x float>* %src, align 4 %l1 = load <24 x float>, <24 x float>* %src, align 4
%s1 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = fadd <8 x float> %s1, %s2 %a1 = fadd <8 x float> %s1, %s2
%a = fadd <8 x float> %a1, %s3 %a = fadd <8 x float> %a1, %s3
store <8 x float> %a, <8 x float> *%dst store <8 x float> %a, <8 x float> *%dst
ret void ret void
} }
define void @vld3_v16f32(<48 x float> *%src, <16 x float> *%dst) { define void @vld3_v16f32(<48 x float> *%src, <16 x float> *%dst) {
; CHECK-LABEL: vld3_v16f32: ; CHECK-LABEL: vld3_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vldrw.u32 q3, [r0, #64]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f64 d3, d0
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s15, s10
; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.f32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.f32 q0, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vmov.f32 s17, s12
; CHECK-NEXT: vmov.f32 s19, s14 ; CHECK-NEXT: vmov.f32 s9, s11
; CHECK-NEXT: vmov.f32 s23, s13 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vadd.f32 q4, q5, q4 ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vldrw.u32 q3, [r0, #144] ; CHECK-NEXT: vadd.f32 q0, q2, q4
; CHECK-NEXT: vadd.f32 q1, q4, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vldrw.u32 q4, [r0, #176] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vmov.f64 d5, d2
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s20, s13 ; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vmov.f64 d12, d6
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s25, s15
; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s26, s10
; CHECK-NEXT: vmov.f32 s8, s14 ; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vldrw.u32 q3, [r0, #112] ; CHECK-NEXT: vmov.f32 s21, s16
; CHECK-NEXT: vmov.f32 s23, s18 ; CHECK-NEXT: vmov.f32 s13, s15
; CHECK-NEXT: vmov.f32 s27, s17 ; CHECK-NEXT: vmov.f32 s22, s19
; CHECK-NEXT: vmov.f32 s18, s16 ; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vadd.f32 q5, q6, q5 ; CHECK-NEXT: vmov.f32 s23, s6
; CHECK-NEXT: vmov.f32 s10, s16 ; CHECK-NEXT: vmov.f32 s15, s5
; CHECK-NEXT: vmov.f32 s11, s19 ; CHECK-NEXT: vmov.f32 s9, s17
; CHECK-NEXT: vldrw.u32 q4, [r0, #96] ; CHECK-NEXT: vadd.f32 q1, q3, q5
; CHECK-NEXT: vadd.f32 q2, q5, q2 ; CHECK-NEXT: vadd.f32 q1, q1, q2
; CHECK-NEXT: vldrw.u32 q5, [r0, #128] ; CHECK-NEXT: vldrw.u32 q2, [r0, #176]
; CHECK-NEXT: vldrw.u32 q4, [r0, #144]
; CHECK-NEXT: vldrw.u32 q5, [r0, #160]
; CHECK-NEXT: vmov.f64 d7, d4
; CHECK-NEXT: vmov.f32 s15, s11
; CHECK-NEXT: vmov.f32 s24, s17 ; CHECK-NEXT: vmov.f32 s24, s17
; CHECK-NEXT: vmov.f32 s12, s18
; CHECK-NEXT: vmov.f32 s25, s20
; CHECK-NEXT: vmov.f32 s17, s19
; CHECK-NEXT: vmov.f32 s26, s23
; CHECK-NEXT: vmov.f32 s18, s22
; CHECK-NEXT: vmov.f32 s27, s10
; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vmov.f32 s13, s21
; CHECK-NEXT: vadd.f32 q2, q4, q6
; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vldrw.u32 q3, [r0, #128]
; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vldrw.u32 q6, [r0, #112]
; CHECK-NEXT: vmov.f64 d9, d6
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f64 d14, d8
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s25, s12 ; CHECK-NEXT: vmov.f32 s19, s15
; CHECK-NEXT: vmov.f32 s29, s19 ; CHECK-NEXT: vmov.f32 s28, s21
; CHECK-NEXT: vmov.f32 s26, s15 ; CHECK-NEXT: vmov.f32 s16, s22
; CHECK-NEXT: vmov.f32 s30, s14 ; CHECK-NEXT: vmov.f32 s29, s24
; CHECK-NEXT: vmov.f32 s12, s18 ; CHECK-NEXT: vmov.f32 s21, s23
; CHECK-NEXT: vmov.f32 s27, s22 ; CHECK-NEXT: vmov.f32 s30, s27
; CHECK-NEXT: vmov.f32 s31, s21 ; CHECK-NEXT: vmov.f32 s22, s26
; CHECK-NEXT: vmov.f32 s22, s20 ; CHECK-NEXT: vmov.f32 s31, s14
; CHECK-NEXT: vadd.f32 q6, q7, q6 ; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s14, s20 ; CHECK-NEXT: vmov.f32 s17, s25
; CHECK-NEXT: vmov.f32 s15, s23 ; CHECK-NEXT: vadd.f32 q3, q5, q7
; CHECK-NEXT: vadd.f32 q3, q6, q3 ; CHECK-NEXT: vadd.f32 q3, q3, q4
; CHECK-NEXT: vstrw.32 q3, [r1, #32] ; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x float>, <48 x float>* %src, align 4 %l1 = load <48 x float>, <48 x float>* %src, align 4
%s1 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesentry:
%a = fadd <4 x half> %a1, %s3 %a = fadd <4 x half> %a1, %s3
store <4 x half> %a, <4 x half> *%dst store <4 x half> %a, <4 x half> *%dst
ret void ret void
} }
define void @vld3_v8f16(<24 x half> *%src, <8 x half> *%dst) { define void @vld3_v8f16(<24 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld3_v8f16: ; CHECK-LABEL: vld3_v8f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q3, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmovx.f16 s4, s14 ; CHECK-NEXT: vmovx.f16 s4, s14
; CHECK-NEXT: vmov.f32 s0, s13 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vins.f16 s0, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
Show All 13 Lines
; CHECK-NEXT: vmovx.f16 s24, s4 ; CHECK-NEXT: vmovx.f16 s24, s4
; CHECK-NEXT: vmov.f32 s21, s15 ; CHECK-NEXT: vmov.f32 s21, s15
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: vmovx.f16 s24, s7 ; CHECK-NEXT: vmovx.f16 s24, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vins.f16 s22, s24 ; CHECK-NEXT: vins.f16 s22, s24
; CHECK-NEXT: vmovx.f16 s24, s12 ; CHECK-NEXT: vmovx.f16 s24, s12
; CHECK-NEXT: vins.f16 s24, s14 ; CHECK-NEXT: vins.f16 s24, s14
; CHECK-NEXT: vmov r12, s2 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vmovx.f16 s25, s15 ; CHECK-NEXT: vmovx.f16 s25, s15
; CHECK-NEXT: vmovx.f16 s15, s17
; CHECK-NEXT: vins.f16 s15, s19
; CHECK-NEXT: vins.f16 s25, s5
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmovx.f16 s12, s18 ; CHECK-NEXT: vmovx.f16 s12, s18
; CHECK-NEXT: vmovx.f16 s6, s6 ; CHECK-NEXT: vins.f16 s25, s5
; CHECK-NEXT: vmovx.f16 s27, s17
; CHECK-NEXT: vins.f16 s17, s12 ; CHECK-NEXT: vins.f16 s17, s12
; CHECK-NEXT: vins.f16 s6, s16 ; CHECK-NEXT: vins.f16 s27, s19
; CHECK-NEXT: vmov r5, s24
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov q1[2], q1[0], r4, r12
; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: vmov lr, s25
; CHECK-NEXT: vmov q0[2], q0[0], r5, r2
; CHECK-NEXT: vmov r3, s11
; CHECK-NEXT: vmov q0[3], q0[1], lr, r0
; CHECK-NEXT: vmov.f32 s23, s17 ; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vmov q1[3], q1[1], r4, r3 ; CHECK-NEXT: vmovx.f16 s26, s6
; CHECK-NEXT: vadd.f16 q0, q5, q0 ; CHECK-NEXT: vins.f16 s26, s16
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q1, q5, q6
; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x half>, <24 x half>* %src, align 4 %l1 = load <24 x half>, <24 x half>* %src, align 4
%s1 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = fadd <8 x half> %s1, %s2 %a1 = fadd <8 x half> %s1, %s2
%a = fadd <8 x half> %a1, %s3 %a = fadd <8 x half> %a1, %s3
store <8 x half> %a, <8 x half> *%dst store <8 x half> %a, <8 x half> *%dst
ret void ret void
} }
define void @vld3_v16f16(<48 x half> *%src, <16 x half> *%dst) { define void @vld3_v16f16(<48 x half> *%src, <16 x half> *%dst) {
; CHECK-LABEL: vld3_v16f16: ; CHECK-LABEL: vld3_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q3, [r0, #48] ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #80] ; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
; CHECK-NEXT: vmovx.f16 s4, s14 ; CHECK-NEXT: vmovx.f16 s4, s14
; CHECK-NEXT: vmov.f32 s0, s13 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vins.f16 s0, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #64] ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
Show All 13 Lines
; CHECK-NEXT: vmovx.f16 s24, s4 ; CHECK-NEXT: vmovx.f16 s24, s4
; CHECK-NEXT: vmov.f32 s21, s15 ; CHECK-NEXT: vmov.f32 s21, s15
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: vmovx.f16 s24, s7 ; CHECK-NEXT: vmovx.f16 s24, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vins.f16 s22, s24 ; CHECK-NEXT: vins.f16 s22, s24
; CHECK-NEXT: vmovx.f16 s24, s12 ; CHECK-NEXT: vmovx.f16 s24, s12
; CHECK-NEXT: vins.f16 s24, s14 ; CHECK-NEXT: vins.f16 s24, s14
; CHECK-NEXT: vmov r12, s2 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vmovx.f16 s25, s15 ; CHECK-NEXT: vmovx.f16 s25, s15
; CHECK-NEXT: vmovx.f16 s15, s17 ; CHECK-NEXT: vmovx.f16 s12, s18
; CHECK-NEXT: vins.f16 s25, s5 ; CHECK-NEXT: vins.f16 s25, s5
; CHECK-NEXT: vmov r6, s24 ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov lr, s25 ; CHECK-NEXT: vmovx.f16 s27, s17
; CHECK-NEXT: vmovx.f16 s24, s18 ; CHECK-NEXT: vins.f16 s17, s12
; CHECK-NEXT: vmovx.f16 s6, s6 ; CHECK-NEXT: vins.f16 s27, s19
; CHECK-NEXT: vins.f16 s17, s24
; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vins.f16 s15, s19
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov r5, s0
; CHECK-NEXT: vmov q1[2], q1[0], r5, r12
; CHECK-NEXT: vmov r5, s1
; CHECK-NEXT: vmov r4, s15
; CHECK-NEXT: vmov q0[2], q0[0], r6, r3
; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: vmov q0[3], q0[1], lr, r4
; CHECK-NEXT: vmov.f32 s23, s17 ; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vmovx.f16 s26, s6
; CHECK-NEXT: vins.f16 s26, s16
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vmov q1[3], q1[1], r5, r2 ; CHECK-NEXT: vadd.f16 q1, q5, q6
; CHECK-NEXT: vadd.f16 q0, q5, q0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vadd.f16 q1, q0, q1 ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmovx.f16 s12, s18 ; CHECK-NEXT: vmovx.f16 s12, s18
; CHECK-NEXT: vmov.f32 s4, s17 ; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: vins.f16 s4, s12 ; CHECK-NEXT: vmovx.f16 s20, s7
; CHECK-NEXT: vins.f16 s0, s12
; CHECK-NEXT: vmovx.f16 s12, s9 ; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vmov.f32 s5, s8 ; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmovx.f16 s20, s3
; CHECK-NEXT: vins.f16 s5, s12
; CHECK-NEXT: vmov.f32 s15, s2
; CHECK-NEXT: vins.f16 s15, s20
; CHECK-NEXT: vmov.f32 s6, s11
; CHECK-NEXT: vmovx.f16 s20, s0
; CHECK-NEXT: vmovx.f16 s24, s17 ; CHECK-NEXT: vmovx.f16 s24, s17
; CHECK-NEXT: vins.f16 s6, s20 ; CHECK-NEXT: vins.f16 s1, s12
; CHECK-NEXT: vmov.f32 s15, s6
; CHECK-NEXT: vins.f16 s15, s20
; CHECK-NEXT: vmov.f32 s2, s11
; CHECK-NEXT: vmovx.f16 s20, s4
; CHECK-NEXT: vmov.f32 s14, s4
; CHECK-NEXT: vins.f16 s2, s20
; CHECK-NEXT: vmov.f64 d10, d8 ; CHECK-NEXT: vmov.f64 d10, d8
; CHECK-NEXT: vins.f16 s20, s24 ; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmovx.f16 s24, s8 ; CHECK-NEXT: vmovx.f16 s24, s8
; CHECK-NEXT: vmov.f32 s21, s19 ; CHECK-NEXT: vmov.f32 s21, s19
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vins.f16 s21, s24
; CHECK-NEXT: vmovx.f16 s24, s11 ; CHECK-NEXT: vmovx.f16 s24, s11
; CHECK-NEXT: vmov.f32 s22, s10 ; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vins.f16 s22, s24 ; CHECK-NEXT: vins.f16 s22, s24
; CHECK-NEXT: vmovx.f16 s24, s16 ; CHECK-NEXT: vmovx.f16 s24, s16
; CHECK-NEXT: vins.f16 s24, s18 ; CHECK-NEXT: vins.f16 s24, s18
; CHECK-NEXT: vmov.f32 s14, s0 ; CHECK-NEXT: vmov.f32 s3, s15
; CHECK-NEXT: vmovx.f16 s25, s19 ; CHECK-NEXT: vmovx.f16 s25, s19
; CHECK-NEXT: vmovx.f16 s19, s1 ; CHECK-NEXT: vmovx.f16 s16, s6
; CHECK-NEXT: vins.f16 s25, s9 ; CHECK-NEXT: vins.f16 s25, s9
; CHECK-NEXT: vmov r3, s24 ; CHECK-NEXT: vmovx.f16 s27, s5
; CHECK-NEXT: vmov r2, s25 ; CHECK-NEXT: vins.f16 s5, s16
; CHECK-NEXT: vmovx.f16 s24, s2 ; CHECK-NEXT: vins.f16 s27, s7
; CHECK-NEXT: vmovx.f16 s10, s10 ; CHECK-NEXT: vmov.f32 s23, s5
; CHECK-NEXT: vins.f16 s1, s24 ; CHECK-NEXT: vmovx.f16 s26, s10
; CHECK-NEXT: vins.f16 s10, s0 ; CHECK-NEXT: vins.f16 s26, s4
; CHECK-NEXT: vins.f16 s19, s3 ; CHECK-NEXT: vadd.f16 q1, q5, q6
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov r6, s10
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vmov.f32 s23, s1
; CHECK-NEXT: vmov q0[2], q0[0], r4, r0
; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vmov q1[2], q1[0], r3, r6
; CHECK-NEXT: vmov r5, s19
; CHECK-NEXT: vmov q1[3], q1[1], r2, r5
; CHECK-NEXT: vmov r4, s15
; CHECK-NEXT: vmov q0[3], q0[1], r0, r4
; CHECK-NEXT: vadd.f16 q1, q5, q1
; CHECK-NEXT: vadd.f16 q0, q1, q0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x half>, <48 x half>* %src, align 4 %l1 = load <48 x half>, <48 x half>* %src, align 4
%s1 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = fadd <16 x half> %s1, %s2 %a1 = fadd <16 x half> %s1, %s2
%a = fadd <16 x half> %a1, %s3 %a = fadd <16 x half> %a1, %s3
store <16 x half> %a, <16 x half> *%dst store <16 x half> %a, <16 x half> *%dst
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vst3.ll

Show All 36 Linesentry:
%s = shufflevector <4 x i32> %t1, <4 x i32> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> %s = shufflevector <4 x i32> %t1, <4 x i32> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
store <6 x i32> %s, <6 x i32> *%dst store <6 x i32> %s, <6 x i32> *%dst
ret void ret void
} }
define void @vst3_v4i32(<4 x i32> *%src, <12 x i32> *%dst) { define void @vst3_v4i32(<4 x i32> *%src, <12 x i32> *%dst) {
; CHECK-LABEL: vst3_v4i32: ; CHECK-LABEL: vst3_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmov.f32 s4, s9 ; CHECK-NEXT: vmov.f64 d8, d6
; CHECK-NEXT: vmov.f64 d6, d8 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov.f32 s8, s5
; CHECK-NEXT: vmov.f32 s5, s1 ; CHECK-NEXT: vmov.f32 s19, s13
; CHECK-NEXT: vdup.32 q5, r0 ; CHECK-NEXT: vmov.f32 s9, s1
; CHECK-NEXT: vmov.f32 s13, s8 ; CHECK-NEXT: vmov.f32 s18, s0
; CHECK-NEXT: vmov.f32 s0, s2 ; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f32 s7, s10 ; CHECK-NEXT: vmov.f32 s11, s6
; CHECK-NEXT: vdup.32 q2, r0 ; CHECK-NEXT: vmov.f32 s1, s15
; CHECK-NEXT: vmov.f32 s15, s17 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s1, s19 ; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vmov.f32 s6, s18 ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vstrw.32 q3, [r1]
; CHECK-NEXT: vstrw.32 q0, [r1, #32] ; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0 %s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0
%l1 = load <4 x i32>, <4 x i32>* %s1, align 4 %l1 = load <4 x i32>, <4 x i32>* %s1, align 4
%s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1 %s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1
%l2 = load <4 x i32>, <4 x i32>* %s2, align 4 %l2 = load <4 x i32>, <4 x i32>* %s2, align 4
%s3 = getelementptr <4 x i32>, <4 x i32>* %src, i32 2 %s3 = getelementptr <4 x i32>, <4 x i32>* %src, i32 2
%l3 = load <4 x i32>, <4 x i32>* %s3, align 4 %l3 = load <4 x i32>, <4 x i32>* %s3, align 4
%t1 = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x i32> %l3, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x i32> %l3, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x i32> %t1, <8 x i32> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x i32> %t1, <8 x i32> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x i32> %s, <12 x i32> *%dst store <12 x i32> %s, <12 x i32> *%dst
ret void ret void
} }
define void @vst3_v8i32(<8 x i32> *%src, <24 x i32> *%dst) { define void @vst3_v8i32(<8 x i32> *%src, <24 x i32> *%dst) {
; CHECK-LABEL: vst3_v8i32: ; CHECK-LABEL: vst3_v8i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #48 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #48 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q5, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vmov.f64 d6, d1 ; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vldrw.u32 q6, [r0, #32] ; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
; CHECK-NEXT: vldrw.u32 q7, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vstrw.32 q4, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov.f64 d10, d8
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vstrw.32 q6, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s13, s23 ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vmov r2, s7 ; CHECK-NEXT: vmov.f32 s21, s28
; CHECK-NEXT: vmov.f32 s15, s3 ; CHECK-NEXT: vmov.f64 d14, d12
; CHECK-NEXT: vdup.32 q2, r2 ; CHECK-NEXT: vmov.f64 d4, d1
; CHECK-NEXT: vmov.f32 s14, s10 ; CHECK-NEXT: vmov.f32 s29, s12
; CHECK-NEXT: vmov.f64 d4, d8 ; CHECK-NEXT: vmov.f32 s9, s27
; CHECK-NEXT: vstrw.32 q3, [r1, #80] ; CHECK-NEXT: vmov.f32 s31, s25
; CHECK-NEXT: vmov.f32 s9, s24 ; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s30, s0
; CHECK-NEXT: vmov q4, q5 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vmov.f32 s21, s4 ; CHECK-NEXT: vstrw.32 q7, [r1, #48]
; CHECK-NEXT: vmov r0, s28 ; CHECK-NEXT: vmov.f32 s3, s14
; CHECK-NEXT: vmov.f32 s23, s17 ; CHECK-NEXT: vmov.f32 s2, s26
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vldrw.u32 q6, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vldrw.u32 q4, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s22, s26
; CHECK-NEXT: vldrw.u32 q6, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vstrw.32 q5, [r1, #48]
; CHECK-NEXT: vmov.f32 s4, s17
; CHECK-NEXT: vstrw.32 q0, [r1, #64] ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s5, s29 ; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q2, [r1, #80]
; CHECK-NEXT: vmov.f32 s28, s30 ; CHECK-NEXT: vmov.f32 s12, s25
; CHECK-NEXT: vmov r0, s19 ; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vmov.f32 s7, s18 ; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vmov.f32 s29, s27 ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f32 s6, s26 ; CHECK-NEXT: vmov.f32 s15, s26
; CHECK-NEXT: vmov.f32 s30, s18 ; CHECK-NEXT: vmov.f32 s5, s19
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vstrw.32 q7, [r1, #32] ; CHECK-NEXT: vmov.f32 s6, s27
; CHECK-NEXT: add sp, #48 ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i32>, <8 x i32>* %src, i32 0 %s1 = getelementptr <8 x i32>, <8 x i32>* %src, i32 0
%l1 = load <8 x i32>, <8 x i32>* %s1, align 4 %l1 = load <8 x i32>, <8 x i32>* %s1, align 4
%s2 = getelementptr <8 x i32>, <8 x i32>* %src, i32 1 %s2 = getelementptr <8 x i32>, <8 x i32>* %src, i32 1
%l2 = load <8 x i32>, <8 x i32>* %s2, align 4 %l2 = load <8 x i32>, <8 x i32>* %s2, align 4
%s3 = getelementptr <8 x i32>, <8 x i32>* %src, i32 2 %s3 = getelementptr <8 x i32>, <8 x i32>* %src, i32 2
%l3 = load <8 x i32>, <8 x i32>* %s3, align 4 %l3 = load <8 x i32>, <8 x i32>* %s3, align 4
%t1 = shufflevector <8 x i32> %l1, <8 x i32> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x i32> %l1, <8 x i32> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x i32> %l3, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x i32> %l3, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x i32> %t1, <16 x i32> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x i32> %t1, <16 x i32> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x i32> %s, <24 x i32> *%dst store <24 x i32> %s, <24 x i32> *%dst
ret void ret void
} }
define void @vst3_v16i32(<16 x i32> *%src, <48 x i32> *%dst) { define void @vst3_v16i32(<16 x i32> *%src, <48 x i32> *%dst) {
; CHECK-LABEL: vst3_v16i32: ; CHECK-LABEL: vst3_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #160 ; CHECK-NEXT: .pad #160
; CHECK-NEXT: sub sp, #160 ; CHECK-NEXT: sub sp, #160
; CHECK-NEXT: vldrw.u32 q1, [r0, #144] ; CHECK-NEXT: vldrw.u32 q7, [r0, #96]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q3, [r0, #128] ; CHECK-NEXT: vldrw.u32 q2, [r0, #128]
; CHECK-NEXT: vldrw.u32 q5, [r0] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #80] ; CHECK-NEXT: vldrw.u32 q7, [r0, #80]
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vldrw.u32 q4, [r0, #176] ; CHECK-NEXT: vldrw.u32 q3, [r0, #160]
; CHECK-NEXT: vstrw.32 q1, [sp, #144] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s9, s13
; CHECK-NEXT: vldrw.u32 q6, [r0, #112]
; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #160]
; CHECK-NEXT: vmov.f32 s11, s2
; CHECK-NEXT: vldrw.u32 q7, [r0, #48] ; CHECK-NEXT: vldrw.u32 q7, [r0, #48]
; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s17, s9
; CHECK-NEXT: vldrw.u32 q1, [r0, #96] ; CHECK-NEXT: vstrw.32 q3, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s10, s22 ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vstrw.32 q2, [r1, #16] ; CHECK-NEXT: vldrw.u32 q5, [r0, #144]
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q1, [r0, #176]
; CHECK-NEXT: vmov.f64 d2, d7 ; CHECK-NEXT: vstrw.32 q7, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vdup.32 q2, r0 ; CHECK-NEXT: vldrw.u32 q7, [r0, #16]
; CHECK-NEXT: vmov.f32 s5, s23 ; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vstrw.32 q4, [r1, #16]
; CHECK-NEXT: vmov.f64 d8, d5
; CHECK-NEXT: vstrw.32 q7, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s27
; CHECK-NEXT: vmov.f32 s19, s11
; CHECK-NEXT: vmov.f32 s18, s3
; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: vmov.f64 d8, d3
; CHECK-NEXT: vmov.f32 s17, s31
; CHECK-NEXT: vmov.f32 s19, s7
; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vstrw.32 q4, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d8, d12
; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov.f32 s19, s25
; CHECK-NEXT: vmov.f32 s18, s8
; CHECK-NEXT: vmov q2, q7
; CHECK-NEXT: vmov.f64 d0, d4
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s4, s13
; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s7, s14
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s10 ; CHECK-NEXT: vmov.f32 s6, s10
; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vmov.f64 d2, d9
; CHECK-NEXT: vmov.f32 s5, s31
; CHECK-NEXT: vmov.f32 s7, s19
; CHECK-NEXT: vmov r0, s27
; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vdup.32 q1, r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.f64 d2, d10
; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s5, s0
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.f32 s7, s21
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f64 d0, d14
; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s24
; CHECK-NEXT: vmov.f32 s3, s29
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.f32 s16, s25
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s19, s26 ; CHECK-NEXT: vmov.f64 d4, d1
; CHECK-NEXT: vldrw.u32 q6, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vmov q3, q1
; CHECK-NEXT: vmov.f32 s18, s30 ; CHECK-NEXT: vmov.f32 s16, s5
; CHECK-NEXT: vmov q2, q1 ; CHECK-NEXT: vmov.f32 s17, s1
; CHECK-NEXT: vmov.f32 s28, s5 ; CHECK-NEXT: vmov.f32 s19, s6
; CHECK-NEXT: vstrw.32 q4, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s29, s1 ; CHECK-NEXT: vmov.f64 d12, d11
; CHECK-NEXT: vmov.f32 s31, s6 ; CHECK-NEXT: vmov q7, q1
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f64 d8, d1 ; CHECK-NEXT: vmov.f32 s18, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov q0, q7
; CHECK-NEXT: vmov.f32 s25, s7
; CHECK-NEXT: vstrw.32 q4, [r1, #112]
; CHECK-NEXT: vmov.f32 s27, s23
; CHECK-NEXT: vldrw.u32 q5, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vldrw.u32 q3, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s29, s20
; CHECK-NEXT: vmov q5, q1 ; CHECK-NEXT: vmov q5, q1
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vmov.f32 s31, s1
; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov.f32 s30, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d6, d5
; CHECK-NEXT: vstrw.32 q7, [r1, #112]
; CHECK-NEXT: vmov.f32 s13, s7
; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov r0, s27
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.f32 s15, s11
; CHECK-NEXT: vstrw.32 q4, [r1, #128]
; CHECK-NEXT: vmov.f32 s14, s2
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vmov.f32 s21, s4
; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s23, s1
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.f32 s22, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [r1, #96] ; CHECK-NEXT: vmov.f32 s26, s15
; CHECK-NEXT: vmov.f64 d2, d0 ; CHECK-NEXT: vstrw.32 q2, [r1, #128]
; CHECK-NEXT: vmov.f32 s5, s24 ; CHECK-NEXT: vmov.f32 s30, s0
; CHECK-NEXT: vmov q6, q0 ; CHECK-NEXT: vstrw.32 q6, [r1, #80]
; CHECK-NEXT: vmov.f32 s7, s1 ; CHECK-NEXT: vmov.f64 d0, d2
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vstrw.32 q7, [r1, #96]
; CHECK-NEXT: vmov.f32 s6, s2 ; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q3, [sp] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [r1, #48] ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s11, s2 ; CHECK-NEXT: vmov.f32 s2, s12
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q0, [r1, #48]
; CHECK-NEXT: vmov.f32 s10, s26 ; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vstrw.32 q0, [r1, #144] ; CHECK-NEXT: vstrw.32 q0, [r1, #144]
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q2, [r1, #64] ; CHECK-NEXT: vmov.f32 s15, s6
; CHECK-NEXT: vstrw.32 q0, [r1, #160] ; CHECK-NEXT: vstrw.32 q0, [r1, #160]
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vstrw.32 q0, [r1, #176] ; CHECK-NEXT: vstrw.32 q0, [r1, #176]
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q3, [r1, #64]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #160 ; CHECK-NEXT: add sp, #160
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x i32>, <16 x i32>* %src, i32 0 %s1 = getelementptr <16 x i32>, <16 x i32>* %src, i32 0
%l1 = load <16 x i32>, <16 x i32>* %s1, align 4 %l1 = load <16 x i32>, <16 x i32>* %s1, align 4
%s2 = getelementptr <16 x i32>, <16 x i32>* %src, i32 1 %s2 = getelementptr <16 x i32>, <16 x i32>* %src, i32 1
Show All 21 Lines
; CHECK-NEXT: ldrh r3, [r0, #2] ; CHECK-NEXT: ldrh r3, [r0, #2]
; CHECK-NEXT: vmov q1[2], q1[0], lr, r2 ; CHECK-NEXT: vmov q1[2], q1[0], lr, r2
; CHECK-NEXT: ldrh r4, [r0] ; CHECK-NEXT: ldrh r4, [r0]
; CHECK-NEXT: ldrh r0, [r0, #10] ; CHECK-NEXT: ldrh r0, [r0, #10]
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov q0[2], q0[0], r4, r3 ; CHECK-NEXT: vmov q0[2], q0[0], r4, r3
; CHECK-NEXT: vmov.f32 s1, s4 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vdup.32 q1, r12
; CHECK-NEXT: vmov.f32 s3, s2 ; CHECK-NEXT: vmov.f32 s3, s2
; CHECK-NEXT: vmov.f32 s2, s6 ; CHECK-NEXT: vmov.32 q0[2], r12
; CHECK-NEXT: vstrh.32 q0, [r1] ; CHECK-NEXT: vstrh.32 q0, [r1]
; CHECK-NEXT: str r0, [r1, #8] ; CHECK-NEXT: str r0, [r1, #8]
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
entry: entry:
%s1 = getelementptr <2 x i16>, <2 x i16>* %src, i32 0 %s1 = getelementptr <2 x i16>, <2 x i16>* %src, i32 0
%l1 = load <2 x i16>, <2 x i16>* %s1, align 4 %l1 = load <2 x i16>, <2 x i16>* %s1, align 4
%s2 = getelementptr <2 x i16>, <2 x i16>* %src, i32 1 %s2 = getelementptr <2 x i16>, <2 x i16>* %src, i32 1
%l2 = load <2 x i16>, <2 x i16>* %s2, align 4 %l2 = load <2 x i16>, <2 x i16>* %s2, align 4
%s3 = getelementptr <2 x i16>, <2 x i16>* %src, i32 2 %s3 = getelementptr <2 x i16>, <2 x i16>* %src, i32 2
%l3 = load <2 x i16>, <2 x i16>* %s3, align 4 %l3 = load <2 x i16>, <2 x i16>* %s3, align 4
%t1 = shufflevector <2 x i16> %l1, <2 x i16> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t1 = shufflevector <2 x i16> %l1, <2 x i16> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%t2 = shufflevector <2 x i16> %l3, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %t2 = shufflevector <2 x i16> %l3, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%s = shufflevector <4 x i16> %t1, <4 x i16> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> %s = shufflevector <4 x i16> %t1, <4 x i16> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
store <6 x i16> %s, <6 x i16> *%dst store <6 x i16> %s, <6 x i16> *%dst
ret void ret void
} }
define void @vst3_v4i16(<4 x i16> *%src, <12 x i16> *%dst) { define void @vst3_v4i16(<4 x i16> *%src, <12 x i16> *%dst) {
; CHECK-LABEL: vst3_v4i16: ; CHECK-LABEL: vst3_v4i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrh.u32 q2, [r0, #16]
; CHECK-NEXT: vldrh.u32 q1, [r0] ; CHECK-NEXT: vldrh.u32 q1, [r0]
; CHECK-NEXT: vldrh.u32 q3, [r0, #8] ; CHECK-NEXT: vldrh.u32 q3, [r0, #8]
; CHECK-NEXT: vmov.f64 d0, d5 ; CHECK-NEXT: vldrh.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.f32 s1, s7
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vmov.16 q4[0], r0 ; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vstrh.32 q0, [r1, #16]
; CHECK-NEXT: vmov.16 q4[1], r0 ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vmov.16 q4[2], r0
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov r0, s13 ; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov.f64 d0, d5
; CHECK-NEXT: vmov.16 q4[4], r0 ; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmov r0, s9 ; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: vmov.f32 s1, s7
; CHECK-NEXT: vmov.16 q4[5], r0 ; CHECK-NEXT: vmov.16 q4[5], r0
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vmov.16 q4[6], r0 ; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov r0, s14 ; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.f32 s2, s15
; CHECK-NEXT: vmov.16 q4[7], r0 ; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vstrh.32 q0, [r1, #16]
; CHECK-NEXT: vstrw.32 q4, [r1] ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x i16>, <4 x i16>* %src, i32 0 %s1 = getelementptr <4 x i16>, <4 x i16>* %src, i32 0
%l1 = load <4 x i16>, <4 x i16>* %s1, align 4 %l1 = load <4 x i16>, <4 x i16>* %s1, align 4
%s2 = getelementptr <4 x i16>, <4 x i16>* %src, i32 1 %s2 = getelementptr <4 x i16>, <4 x i16>* %src, i32 1
%l2 = load <4 x i16>, <4 x i16>* %s2, align 4 %l2 = load <4 x i16>, <4 x i16>* %s2, align 4
%s3 = getelementptr <4 x i16>, <4 x i16>* %src, i32 2 %s3 = getelementptr <4 x i16>, <4 x i16>* %src, i32 2
%l3 = load <4 x i16>, <4 x i16>* %s3, align 4 %l3 = load <4 x i16>, <4 x i16>* %s3, align 4
%t1 = shufflevector <4 x i16> %l1, <4 x i16> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x i16> %l1, <4 x i16> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x i16> %l3, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x i16> %l3, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x i16> %t1, <8 x i16> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x i16> %t1, <8 x i16> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x i16> %s, <12 x i16> *%dst store <12 x i16> %s, <12 x i16> *%dst
ret void ret void
} }
define void @vst3_v8i16(<8 x i16> *%src, <24 x i16> *%dst) { define void @vst3_v8i16(<8 x i16> *%src, <24 x i16> *%dst) {
; CHECK-LABEL: vst3_v8i16: ; CHECK-LABEL: vst3_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vmov.f64 d0, d4
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.u16 r2, q1[1]
; CHECK-NEXT: vmov.u16 r0, q3[2] ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmov.f32 s17, s12
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-NEXT: vmov.f32 s18, s12
; CHECK-NEXT: vmov.u16 r0, q3[4] ; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vins.f16 s3, s5
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.16 q5[3], r2
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vins.f16 s16, s8 ; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.u16 r0, q2[1] ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmov.f32 s1, s21
; CHECK-NEXT: vmov.16 q4[4], r0 ; CHECK-NEXT: vins.f16 s17, s7
; CHECK-NEXT: vins.f16 s5, s9 ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.f32 s19, s5 ; CHECK-NEXT: vmov.f32 s2, s22
; CHECK-NEXT: vdup.32 q5, r2 ; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmov.u16 r2, q5[2] ; CHECK-NEXT: vmov.u16 r2, q5[2]
; CHECK-NEXT: vmov.16 q6[2], r2
; CHECK-NEXT: vmov.u16 r0, q4[3] ; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov.16 q6[2], r2
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4] ; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q5[5] ; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vmov.16 q6[5], r0 ; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[5] ; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.16 q5[0], r0 ; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[5] ; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vmov.16 q5[1], r0 ; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov.u16 r0, q2[7] ; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vins.f16 s21, s11
; CHECK-NEXT: vmov.f32 s17, s25
; CHECK-NEXT: vmov.16 q5[6], r0 ; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[7] ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: vmov.16 q5[7], r0 ; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov.f32 s18, s26 ; CHECK-NEXT: vrev32.16 q1, q1
; CHECK-NEXT: vdup.32 q6, r2 ; CHECK-NEXT: vmov.f32 s21, s13
; CHECK-NEXT: vmov.f32 s22, s15 ; CHECK-NEXT: vmov.u16 r2, q1[2]
; CHECK-NEXT: vmov.u16 r2, q6[2] ; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vmov.u16 r0, q5[3] ; CHECK-NEXT: vmov.u16 r0, q5[3]
; CHECK-NEXT: vmov.16 q7[2], r2 ; CHECK-NEXT: vmov.f32 s17, s25
; CHECK-NEXT: vmov.f32 s1, s13 ; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.16 q7[3], r0
; CHECK-NEXT: vmov.u16 r0, q5[4] ; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vrev32.16 q2, q2 ; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.16 q7[4], r0 ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.u16 r0, q6[5]
; CHECK-NEXT: vmov.u16 r2, q2[2]
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.16 q7[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vmov.u16 r2, q0[4]
; CHECK-NEXT: vmov.16 q2[4], r2
; CHECK-NEXT: vmov.f32 s21, s29
; CHECK-NEXT: vmov.16 q2[5], r0 ; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.f32 s22, s30 ; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.f32 s1, s9 ; CHECK-NEXT: vmov.f32 s21, s9
; CHECK-NEXT: vstrw.32 q5, [r1, #32] ; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: vmov.f32 s2, s10 ; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vstrw.32 q4, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q5, [r1, #16]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0 %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
%l1 = load <8 x i16>, <8 x i16>* %s1, align 4 %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
%s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1 %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
%l2 = load <8 x i16>, <8 x i16>* %s2, align 4 %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
%s3 = getelementptr <8 x i16>, <8 x i16>* %src, i32 2 %s3 = getelementptr <8 x i16>, <8 x i16>* %src, i32 2
%l3 = load <8 x i16>, <8 x i16>* %s3, align 4 %l3 = load <8 x i16>, <8 x i16>* %s3, align 4
%t1 = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x i16> %l3, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x i16> %l3, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x i16> %t1, <16 x i16> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x i16> %t1, <16 x i16> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x i16> %s, <24 x i16> *%dst store <24 x i16> %s, <24 x i16> *%dst
ret void ret void
} }
define void @vst3_v16i16(<16 x i16> *%src, <48 x i16> *%dst) { define void @vst3_v16i16(<16 x i16> *%src, <48 x i16> *%dst) {
; CHECK-LABEL: vst3_v16i16: ; CHECK-LABEL: vst3_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #160 ; CHECK-NEXT: .pad #112
; CHECK-NEXT: sub sp, #160 ; CHECK-NEXT: sub sp, #112
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vmov.f64 d4, d2 ; CHECK-NEXT: vldrw.u32 q7, [r0, #64]
; CHECK-NEXT: vmov.f64 d12, d2
; CHECK-NEXT: vmov.u16 r2, q0[1] ; CHECK-NEXT: vmov.u16 r2, q0[1]
; CHECK-NEXT: vmov q6, q0 ; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q6, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s8, s0 ; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[4], r2 ; CHECK-NEXT: vins.f16 s24, s0
; CHECK-NEXT: vmov.f32 s11, s5 ; CHECK-NEXT: vmov.16 q6[4], r2
; CHECK-NEXT: vins.f16 s11, s1 ; CHECK-NEXT: vmov.f32 s27, s5
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q1, [r0, #80]
; CHECK-NEXT: vmov.f32 s9, s4 ; CHECK-NEXT: vins.f16 s27, s1
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov.f32 s13, s4
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vstrw.32 q1, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: vmov.f32 s14, s4
; CHECK-NEXT: vmov.u16 r2, q2[3] ; CHECK-NEXT: vmov.f32 s25, s8
; CHECK-NEXT: vmov.u16 r3, q0[2] ; CHECK-NEXT: vmov.u16 r3, q3[2]
; CHECK-NEXT: vmov q3, q2 ; CHECK-NEXT: vstrw.32 q3, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vmov.u16 r2, q6[3]
; CHECK-NEXT: vmov.16 q2[2], r3 ; CHECK-NEXT: vmov.16 q3[2], r3
; CHECK-NEXT: vmov.16 q2[3], r2 ; CHECK-NEXT: vmov.16 q3[3], r2
; CHECK-NEXT: vmov.u16 r2, q3[4] ; CHECK-NEXT: vmov.u16 r2, q6[4]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vmov.16 q3[4], r2
; CHECK-NEXT: vmov.16 q2[4], r2
; CHECK-NEXT: vmov.u16 r2, q0[5] ; CHECK-NEXT: vmov.u16 r2, q0[5]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vmov.16 q2[5], r2
; CHECK-NEXT: vmov.u16 r2, q3[5]
; CHECK-NEXT: vmov.16 q5[0], r2 ; CHECK-NEXT: vmov.16 q5[0], r2
; CHECK-NEXT: vmov.u16 r2, q0[5] ; CHECK-NEXT: vmov.u16 r2, q1[5]
; CHECK-NEXT: vmov.16 q5[1], r2 ; CHECK-NEXT: vmov.16 q5[1], r2
; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vins.f16 s21, s15
; CHECK-NEXT: vmov.u16 r2, q3[7]
; CHECK-NEXT: vstrw.32 q0, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q5[6], r2
; CHECK-NEXT: vmov.u16 r2, q0[7] ; CHECK-NEXT: vmov.u16 r2, q0[7]
; CHECK-NEXT: vins.f16 s21, s3
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vmov.f32 s9, s3
; CHECK-NEXT: vmov.16 q5[6], r2
; CHECK-NEXT: vmov.u16 r2, q1[7]
; CHECK-NEXT: vmov.f32 s10, s3
; CHECK-NEXT: vmov.16 q5[7], r2 ; CHECK-NEXT: vmov.16 q5[7], r2
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vmov.u16 r3, q2[2]
; CHECK-NEXT: vmov.f32 s22, s3 ; CHECK-NEXT: vmov.f32 s22, s7
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vmov.16 q1[2], r3
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.u16 r2, q5[3] ; CHECK-NEXT: vmov.u16 r2, q5[3]
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmov.u16 r0, q5[4] ; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov.16 q4[3], r2 ; CHECK-NEXT: vmov.u16 r2, q5[4]
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov.16 q4[4], r0 ; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov.u16 r2, q0[1]
; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vmov.f64 d8, d4
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s16, s0
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.16 q4[4], r2
; CHECK-NEXT: vstrw.32 q5, [r1, #80]
; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vins.f16 s19, s1
; CHECK-NEXT: vmov.f32 s17, s8
; CHECK-NEXT: vmov.f32 s9, s28
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov.f32 s10, s28
; CHECK-NEXT: vmov.u16 r2, q2[2]
; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vldrw.u32 q2, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.f32 s17, s5
; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmov.f32 s18, s6
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov.16 q4[5], r0 ; CHECK-NEXT: vmov.u16 r0, q7[5]
; CHECK-NEXT: vmov.f64 d14, d0 ; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[1] ; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vins.f16 s9, s3
; CHECK-NEXT: vmov q4, q1 ; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q4, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vins.f16 s28, s12 ; CHECK-NEXT: vmov.u16 r0, q7[7]
; CHECK-NEXT: vmov.16 q7[4], r0 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s31, s1 ; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vins.f16 s31, s13 ; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: vrev32.16 q3, q3 ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f32 s29, s0 ; CHECK-NEXT: vmov.f32 s10, s31
; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vmov.u16 r2, q1[2]
; CHECK-NEXT: vmov.u16 r0, q7[3] ; CHECK-NEXT: vmov.u16 r0, q2[3]
; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill ; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vdup.32 q0, r2 ; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vmov.u16 r2, q0[2] ; CHECK-NEXT: vmov.f32 s25, s13
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.16 q2[3], r0 ; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q7, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s26, s14
; CHECK-NEXT: vldrw.u32 q3, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vrev32.16 q1, q1
; CHECK-NEXT: vmov.u16 r0, q7[2]
; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.f32 s9, s1
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u16 r0, q7[4] ; CHECK-NEXT: vmov.u16 r0, q7[4]
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.16 q2[5], r0 ; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov.u16 r0, q6[5] ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s5, s29
; CHECK-NEXT: vldrw.u32 q7, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vstrw.32 q2, [r1, #32]
; CHECK-NEXT: vmov.u16 r2, q7[2]
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.16 q3[2], r2
; CHECK-NEXT: vstrw.32 q6, [r1, #48]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u16 r0, q7[5]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vldrw.u32 q7, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vldrw.u32 q3, [sp] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [r1, #64]
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q7[3]
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov.u16 r0, q6[7] ; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vins.f16 s1, s27
; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q7[5]
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vmov.f32 s2, s19 ; CHECK-NEXT: vmov.f32 s1, s13
; CHECK-NEXT: vmov r2, s7 ; CHECK-NEXT: vldrw.u32 q3, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s30
; CHECK-NEXT: vrev32.16 q3, q3
; CHECK-NEXT: vmov.u16 r0, q0[3] ; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vdup.32 q6, r2 ; CHECK-NEXT: vmov.u16 r2, q3[2]
; CHECK-NEXT: vmov.u16 r2, q6[2] ; CHECK-NEXT: vmov.16 q7[2], r2
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vmov.16 q7[3], r0
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q0[4] ; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vmov.16 q7[4], r0
; CHECK-NEXT: vmov.u16 r0, q6[5] ; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.16 q2[5], r0 ; CHECK-NEXT: vmov.16 q7[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[2] ; CHECK-NEXT: vmov.f32 s1, s29
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.f32 s2, s30
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: add sp, #112
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vldrw.u32 q6, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q4, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vrev32.16 q6, q6
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vstrw.32 q6, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q6[0], r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov.f32 s1, s9
; CHECK-NEXT: vmov.16 q6[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vldrw.u32 q1, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.f32 s29, s5
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov.f32 s30, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1, #80]
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.u16 r2, q0[2]
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [r1, #32]
; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s25, s5
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s26, s18
; CHECK-NEXT: vstrw.32 q7, [r1]
; CHECK-NEXT: vmov.u16 r2, q6[3]
; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vmov.u16 r2, q6[4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.f32 s25, s1
; CHECK-NEXT: vmov.f32 s26, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s6
; CHECK-NEXT: vstrw.32 q6, [r1, #16]
; CHECK-NEXT: vmov.u16 r2, q0[2]
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q0[2], r2
; CHECK-NEXT: vmov.u16 r2, q3[3]
; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vmov.u16 r2, q3[4]
; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov.f32 s13, s1
; CHECK-NEXT: vmov.f32 s14, s2
; CHECK-NEXT: vstrw.32 q3, [r1, #64]
; CHECK-NEXT: add sp, #160
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x i16>, <16 x i16>* %src, i32 0 %s1 = getelementptr <16 x i16>, <16 x i16>* %src, i32 0
%l1 = load <16 x i16>, <16 x i16>* %s1, align 4 %l1 = load <16 x i16>, <16 x i16>* %s1, align 4
%s2 = getelementptr <16 x i16>, <16 x i16>* %src, i32 1 %s2 = getelementptr <16 x i16>, <16 x i16>* %src, i32 1
%l2 = load <16 x i16>, <16 x i16>* %s2, align 4 %l2 = load <16 x i16>, <16 x i16>* %s2, align 4
%s3 = getelementptr <16 x i16>, <16 x i16>* %src, i32 2 %s3 = getelementptr <16 x i16>, <16 x i16>* %src, i32 2
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vldrb.u16 q2, [r0, #16] ; CHECK-NEXT: vldrb.u16 q2, [r0, #16]
; CHECK-NEXT: vldrb.u16 q3, [r0] ; CHECK-NEXT: vldrb.u16 q3, [r0]
; CHECK-NEXT: vmov.u16 r2, q1[5] ; CHECK-NEXT: vmov.u16 r2, q1[5]
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5] ; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov.u16 r2, q1[7] ; CHECK-NEXT: vmov.u16 r2, q1[7]
; CHECK-NEXT: vins.f16 s1, s7 ; CHECK-NEXT: vins.f16 s1, s7
; CHECK-NEXT: vmov r0, s15 ; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vmov.16 q0[6], r2 ; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: vmov.u16 r2, q2[7] ; CHECK-NEXT: vmov.u16 r2, q2[7]
; CHECK-NEXT: vmov.16 q0[7], r2 ; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmov.f32 s2, s11 ; CHECK-NEXT: vmov.f32 s2, s11
; CHECK-NEXT: vmov.u16 r0, q4[2] ; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov.16 q5[2], r0 ; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r2, q0[3] ; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.16 q5[3], r2 ; CHECK-NEXT: vmov.16 q5[3], r2
; CHECK-NEXT: vmov.u16 r0, q0[4] ; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.16 q5[4], r0 ; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.u16 r0, q4[5] ; CHECK-NEXT: vmov.u16 r0, q4[5]
▲ Show 20 Lines • Show All 385 Lines • ▼ Show 20 Lines
} }
define void @vst3_v4f32(<4 x float> *%src, <12 x float> *%dst) { define void @vst3_v4f32(<4 x float> *%src, <12 x float> *%dst) {
; CHECK-LABEL: vst3_v4f32: ; CHECK-LABEL: vst3_v4f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q3, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmov.f64 d8, d6 ; CHECK-NEXT: vmov.f64 d8, d6
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f32 s19, s13 ; CHECK-NEXT: vmov.f32 s19, s13
; CHECK-NEXT: vmov.f32 s9, s1 ; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov.f32 s18, s0 ; CHECK-NEXT: vmov.f32 s18, s4
; CHECK-NEXT: vmov.f32 s0, s2 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vstrw.32 q4, [r1] ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f32 s11, s6 ; CHECK-NEXT: vmov.f32 s11, s2
; CHECK-NEXT: vmov.f32 s1, s15 ; CHECK-NEXT: vmov.f32 s5, s15
; CHECK-NEXT: vmov.f32 s10, s14 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s2, s7 ; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: vstrw.32 q2, [r1, #16] ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vstrw.32 q0, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0 %s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0
%l1 = load <4 x float>, <4 x float>* %s1, align 4 %l1 = load <4 x float>, <4 x float>* %s1, align 4
%s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1 %s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1
%l2 = load <4 x float>, <4 x float>* %s2, align 4 %l2 = load <4 x float>, <4 x float>* %s2, align 4
%s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2 %s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2
%l3 = load <4 x float>, <4 x float>* %s3, align 4 %l3 = load <4 x float>, <4 x float>* %s3, align 4
%t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x float> %l3, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x float> %l3, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x float> %t1, <8 x float> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x float> %t1, <8 x float> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x float> %s, <12 x float> *%dst store <12 x float> %s, <12 x float> *%dst
ret void ret void
} }
define void @vst3_v8f32(<8 x float> *%src, <24 x float> *%dst) { define void @vst3_v8f32(<8 x float> *%src, <24 x float> *%dst) {
; CHECK-LABEL: vst3_v8f32: ; CHECK-LABEL: vst3_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q7, [r0, #32] ; CHECK-NEXT: vldrw.u32 q6, [r0, #32]
; CHECK-NEXT: vldrw.u32 q6, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vmov.f64 d10, d8 ; CHECK-NEXT: vmov.f64 d10, d8
; CHECK-NEXT: vldrw.u32 q3, [r0, #48] ; CHECK-NEXT: vldrw.u32 q7, [r0, #48]
; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q6, [sp] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #64] ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vmov.f32 s21, s28 ; CHECK-NEXT: vmov.f32 s21, s24
; CHECK-NEXT: vmov.f64 d14, d12 ; CHECK-NEXT: vmov.f64 d12, d4
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f64 d6, d1
; CHECK-NEXT: vmov.f32 s29, s12 ; CHECK-NEXT: vmov.f32 s25, s28
; CHECK-NEXT: vmov.f32 s9, s27 ; CHECK-NEXT: vmov.f32 s13, s11
; CHECK-NEXT: vmov.f32 s31, s25 ; CHECK-NEXT: vmov.f32 s27, s9
; CHECK-NEXT: vmov.f32 s11, s3 ; CHECK-NEXT: vmov.f32 s15, s3
; CHECK-NEXT: vmov.f32 s30, s0 ; CHECK-NEXT: vmov.f32 s26, s0
; CHECK-NEXT: vmov.f32 s0, s13 ; CHECK-NEXT: vmov.f32 s0, s29
; CHECK-NEXT: vstrw.32 q7, [r1, #48] ; CHECK-NEXT: vstrw.32 q6, [r1, #48]
; CHECK-NEXT: vmov.f32 s3, s14 ; CHECK-NEXT: vmov.f32 s3, s30
; CHECK-NEXT: vmov.f32 s2, s26 ; CHECK-NEXT: vmov.f32 s14, s31
; CHECK-NEXT: vldrw.u32 q6, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s23, s17 ; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vstrw.32 q2, [r1, #80] ; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s12, s25 ; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vmov.f32 s13, s5 ; CHECK-NEXT: vmov.f32 s8, s29
; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov.f32 s22, s4 ; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vmov.f32 s4, s6 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vstrw.32 q5, [r1] ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f32 s15, s26 ; CHECK-NEXT: vmov.f32 s11, s30
; CHECK-NEXT: vmov.f32 s5, s19 ; CHECK-NEXT: vmov.f32 s5, s19
; CHECK-NEXT: vmov.f32 s14, s18 ; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vmov.f32 s6, s27 ; CHECK-NEXT: vmov.f32 s6, s31
; CHECK-NEXT: vstrw.32 q3, [r1, #16] ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x float>, <8 x float>* %src, i32 0 %s1 = getelementptr <8 x float>, <8 x float>* %src, i32 0
%l1 = load <8 x float>, <8 x float>* %s1, align 4 %l1 = load <8 x float>, <8 x float>* %s1, align 4
%s2 = getelementptr <8 x float>, <8 x float>* %src, i32 1 %s2 = getelementptr <8 x float>, <8 x float>* %src, i32 1
Show All 9 Lines
define void @vst3_v16f32(<16 x float> *%src, <48 x float> *%dst) { define void @vst3_v16f32(<16 x float> *%src, <48 x float> *%dst) {
; CHECK-LABEL: vst3_v16f32: ; CHECK-LABEL: vst3_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #160 ; CHECK-NEXT: .pad #160
; CHECK-NEXT: sub sp, #160 ; CHECK-NEXT: sub sp, #160
; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0, #128] ; CHECK-NEXT: vldrw.u32 q5, [r0, #112]
; CHECK-NEXT: vldrw.u32 q2, [r0, #128]
; CHECK-NEXT: vldrw.u32 q6, [r0] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vstrw.32 q5, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vmov.f32 s13, s9
; CHECK-NEXT: vmov.f32 s15, s2
; CHECK-NEXT: vldrw.u32 q4, [r0, #160]
; CHECK-NEXT: vstrw.32 q5, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q5, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q5, [r0, #80] ; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vmov.f32 s16, s1 ; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0, #160] ; CHECK-NEXT: vmov.f32 s14, s26
; CHECK-NEXT: vstrw.32 q5, [sp, #144] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q4, [r0, #144]
; CHECK-NEXT: vstrw.32 q5, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q7, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #176]
; CHECK-NEXT: vldrw.u32 q5, [r0, #48] ; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vmov.f32 s17, s5 ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vstrw.32 q3, [sp, #128] @ 16-byte Spill ; CHECK-NEXT: vmov.f64 d6, d5
; CHECK-NEXT: vmov.f32 s19, s2 ; CHECK-NEXT: vstrw.32 q7, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q5, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q7, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vstrw.32 q4, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s18, s26 ; CHECK-NEXT: vmov.f32 s13, s27
; CHECK-NEXT: vldrw.u32 q7, [r0, #144] ; CHECK-NEXT: vmov.f32 s15, s11
; CHECK-NEXT: vldrw.u32 q2, [r0, #176] ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vstrw.32 q5, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vldrw.u32 q5, [r0, #16] ; CHECK-NEXT: vmov.f64 d6, d3
; CHECK-NEXT: vldrw.u32 q3, [r0, #112] ; CHECK-NEXT: vmov.f32 s13, s23
; CHECK-NEXT: vstrw.32 q4, [r1, #16] ; CHECK-NEXT: vmov.f32 s15, s7
; CHECK-NEXT: vmov.f64 d8, d3 ; CHECK-NEXT: vmov.f32 s14, s31
; CHECK-NEXT: vstrw.32 q5, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q5, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vmov.f64 d6, d12
; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s17, s27 ; CHECK-NEXT: vmov.f32 s15, s25
; CHECK-NEXT: vmov.f32 s19, s7 ; CHECK-NEXT: vmov.f32 s14, s8
; CHECK-NEXT: vmov.f32 s18, s3 ; CHECK-NEXT: vmov q2, q7
; CHECK-NEXT: vstrw.32 q4, [r1, #32] ; CHECK-NEXT: vmov.f64 d0, d10
; CHECK-NEXT: vmov.f64 d8, d5 ; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s23 ; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.f32 s19, s11 ; CHECK-NEXT: vmov.f32 s3, s21
; CHECK-NEXT: vmov.f32 s18, s15 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vstrw.32 q4, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s4, s9
; CHECK-NEXT: vmov.f64 d8, d12 ; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s0 ; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: vmov.f32 s19, s25
; CHECK-NEXT: vmov.f32 s18, s4
; CHECK-NEXT: vmov q1, q5
; CHECK-NEXT: vmov.f64 d0, d2
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s8, s13
; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s11, s14
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s6 ; CHECK-NEXT: vmov.f32 s6, s22
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov.f64 d4, d1
; CHECK-NEXT: vmov.f64 d8, d1 ; CHECK-NEXT: vmov q3, q1
; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmov.f32 s20, s5 ; CHECK-NEXT: vmov.f32 s20, s5
; CHECK-NEXT: vmov.f32 s21, s1 ; CHECK-NEXT: vmov.f32 s21, s1
; CHECK-NEXT: vmov.f32 s23, s6 ; CHECK-NEXT: vmov.f32 s23, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d6, d15 ; CHECK-NEXT: vmov.f64 d12, d9
; CHECK-NEXT: vmov q6, q1 ; CHECK-NEXT: vmov q7, q1
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s19, s3 ; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov q0, q6 ; CHECK-NEXT: vmov q0, q7
; CHECK-NEXT: vmov.f32 s13, s7 ; CHECK-NEXT: vmov.f32 s25, s7
; CHECK-NEXT: vstrw.32 q5, [r1, #112] ; CHECK-NEXT: vstrw.32 q5, [r1, #112]
; CHECK-NEXT: vmov.f32 s15, s31 ; CHECK-NEXT: vmov.f32 s27, s19
; CHECK-NEXT: vldrw.u32 q7, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s11 ; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vldrw.u32 q2, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q3, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s25, s28 ; CHECK-NEXT: vmov.f32 s29, s16
; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s27, s1 ; CHECK-NEXT: vmov.f32 s31, s1
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s11 ; CHECK-NEXT: vmov.f32 s26, s15
; CHECK-NEXT: vstrw.32 q4, [r1, #128] ; CHECK-NEXT: vstrw.32 q2, [r1, #128]
; CHECK-NEXT: vmov.f32 s26, s0 ; CHECK-NEXT: vmov.f32 s30, s0
; CHECK-NEXT: vstrw.32 q3, [r1, #80] ; CHECK-NEXT: vstrw.32 q6, [r1, #80]
; CHECK-NEXT: vmov.f64 d0, d2 ; CHECK-NEXT: vmov.f64 d0, d2
; CHECK-NEXT: vstrw.32 q6, [r1, #96] ; CHECK-NEXT: vstrw.32 q7, [r1, #96]
; CHECK-NEXT: vmov.f32 s1, s8 ; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s28 ; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vstrw.32 q0, [r1, #48] ; CHECK-NEXT: vstrw.32 q0, [r1, #48]
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s28, s5 ; CHECK-NEXT: vmov.f32 s16, s13
; CHECK-NEXT: vstrw.32 q0, [r1, #144] ; CHECK-NEXT: vstrw.32 q0, [r1, #144]
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s31, s6 ; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vstrw.32 q0, [r1, #160] ; CHECK-NEXT: vstrw.32 q0, [r1, #160]
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s10 ; CHECK-NEXT: vmov.f32 s18, s6
; CHECK-NEXT: vstrw.32 q0, [r1, #176] ; CHECK-NEXT: vstrw.32 q0, [r1, #176]
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q7, [r1, #64] ; CHECK-NEXT: vstrw.32 q4, [r1, #64]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #160 ; CHECK-NEXT: add sp, #160
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0 %s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0
%l1 = load <16 x float>, <16 x float>* %s1, align 4 %l1 = load <16 x float>, <16 x float>* %s1, align 4
%s2 = getelementptr <16 x float>, <16 x float>* %src, i32 1 %s2 = getelementptr <16 x float>, <16 x float>* %src, i32 1
Show All 40 Linesentry:
%s = shufflevector <4 x half> %t1, <4 x half> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> %s = shufflevector <4 x half> %t1, <4 x half> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
store <6 x half> %s, <6 x half> *%dst store <6 x half> %s, <6 x half> *%dst
ret void ret void
} }
define void @vst3_v4f16(<4 x half> *%src, <12 x half> *%dst) { define void @vst3_v4f16(<4 x half> *%src, <12 x half> *%dst) {
; CHECK-LABEL: vst3_v4f16: ; CHECK-LABEL: vst3_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrd lr, r12, [r0] ; CHECK-NEXT: ldrd r2, r12, [r0]
; CHECK-NEXT: ldrd r3, r2, [r0, #8] ; CHECK-NEXT: ldrd r3, lr, [r0, #8]
; CHECK-NEXT: ldrd r4, r0, [r0, #16] ; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov q0[2], q0[0], lr, r3 ; CHECK-NEXT: ldrd r2, r0, [r0, #16]
; CHECK-NEXT: vmov.32 q1[0], r4 ; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: vmov q0[3], q0[1], r12, r2 ; CHECK-NEXT: vmov.32 q0[1], r12
; CHECK-NEXT: vmov.32 q1[1], lr
; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov.32 q1[1], r0 ; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vins.f16 s0, s2 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vmov.f32 s9, s4 ; CHECK-NEXT: vmov.f32 s9, s4
; CHECK-NEXT: vmovx.f16 s10, s2 ; CHECK-NEXT: vmovx.f16 s10, s2
; CHECK-NEXT: vins.f16 s10, s12 ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmovx.f16 s12, s1 ; CHECK-NEXT: vmovx.f16 s12, s1
; CHECK-NEXT: vins.f16 s1, s3 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vmov.f32 s11, s1 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vmovx.f16 s1, s3
; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q2, [r1]
; CHECK-NEXT: vmovx.f16 s8, s5 ; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vins.f16 s5, s12 ; CHECK-NEXT: vins.f16 s5, s12
; CHECK-NEXT: vmov.f32 s4, s5 ; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vmovx.f16 s5, s3 ; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vins.f16 s5, s8 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: strd r2, r0, [r1, #16] ; CHECK-NEXT: strd r2, r0, [r1, #16]
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0 %s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
%l1 = load <4 x half>, <4 x half>* %s1, align 4 %l1 = load <4 x half>, <4 x half>* %s1, align 4
%s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1 %s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1
%l2 = load <4 x half>, <4 x half>* %s2, align 4 %l2 = load <4 x half>, <4 x half>* %s2, align 4
%s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2 %s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2
%l3 = load <4 x half>, <4 x half>* %s3, align 4 %l3 = load <4 x half>, <4 x half>* %s3, align 4
%t1 = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
Show All 12 Lines
; CHECK-NEXT: vldrw.u32 q3, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmovx.f16 s0, s8 ; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vmovx.f16 s20, s12 ; CHECK-NEXT: vmovx.f16 s20, s12
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s24, s6 ; CHECK-NEXT: vmovx.f16 s24, s6
; CHECK-NEXT: vmov.f64 d0, d6 ; CHECK-NEXT: vmov.f64 d0, d6
; CHECK-NEXT: vins.f16 s0, s8 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vmov.f32 s18, s4
; CHECK-NEXT: vmov.f32 s3, s13 ; CHECK-NEXT: vmov.f32 s3, s13
; CHECK-NEXT: vins.f16 s17, s20 ; CHECK-NEXT: vins.f16 s17, s20
; CHECK-NEXT: vins.f16 s3, s9 ; CHECK-NEXT: vins.f16 s3, s9
; CHECK-NEXT: vmovx.f16 s20, s18 ; CHECK-NEXT: vmovx.f16 s20, s18
; CHECK-NEXT: vmov.f32 s1, s12 ; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vins.f16 s2, s20 ; CHECK-NEXT: vins.f16 s2, s20
; CHECK-NEXT: vmovx.f16 s20, s10 ; CHECK-NEXT: vmovx.f16 s20, s10
; CHECK-NEXT: vins.f16 s20, s24 ; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: vmov.16 q5[3], r0 ; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmovx.f16 s24, s7 ; CHECK-NEXT: vmovx.f16 s24, s7
; CHECK-NEXT: vmovx.f16 s23, s11 ; CHECK-NEXT: vmovx.f16 s23, s11
; CHECK-NEXT: vmov r0, s15 ; CHECK-NEXT: vrev32.16 q2, q2
; CHECK-NEXT: vins.f16 s23, s24 ; CHECK-NEXT: vins.f16 s23, s24
; CHECK-NEXT: vdup.32 q6, r0 ; CHECK-NEXT: vmov.f32 s25, s15
; CHECK-NEXT: vmov.f32 s22, s7 ; CHECK-NEXT: vmov.f32 s22, s7
; CHECK-NEXT: vmovx.f16 s28, s21 ; CHECK-NEXT: vmovx.f16 s28, s21
; CHECK-NEXT: vmov.f32 s26, s15
; CHECK-NEXT: vins.f16 s25, s28 ; CHECK-NEXT: vins.f16 s25, s28
; CHECK-NEXT: vmovx.f16 s28, s26 ; CHECK-NEXT: vmovx.f16 s28, s26
; CHECK-NEXT: vins.f16 s22, s28 ; CHECK-NEXT: vins.f16 s22, s28
; CHECK-NEXT: vmovx.f16 s28, s13 ; CHECK-NEXT: vmovx.f16 s28, s13
; CHECK-NEXT: vmov.f32 s4, s5 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vrev32.16 q2, q2
; CHECK-NEXT: vins.f16 s4, s28 ; CHECK-NEXT: vins.f16 s4, s28
; CHECK-NEXT: vmovx.f16 s28, s14 ; CHECK-NEXT: vmovx.f16 s28, s14
; CHECK-NEXT: vins.f16 s6, s28 ; CHECK-NEXT: vins.f16 s6, s28
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s7, s6 ; CHECK-NEXT: vmov.f32 s7, s6
; CHECK-NEXT: vmov.f32 s6, s14 ; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vmovx.f16 s12, s5 ; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vins.f16 s9, s12 ; CHECK-NEXT: vins.f16 s9, s12
Show All 28 Lines
define void @vst3_v16f16(<16 x half> *%src, <48 x half> *%dst) { define void @vst3_v16f16(<16 x half> *%src, <48 x half> *%dst) {
; CHECK-LABEL: vst3_v16f16: ; CHECK-LABEL: vst3_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #144 ; CHECK-NEXT: .pad #144
; CHECK-NEXT: sub sp, #144 ; CHECK-NEXT: sub sp, #144
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vmovx.f16 s0, s12 ; CHECK-NEXT: vldrw.u32 q7, [r0, #16]
; CHECK-NEXT: vmov q6, q2 ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmovx.f16 s0, s22
; CHECK-NEXT: vmovx.f16 s4, s10
; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmovx.f16 s0, s23
; CHECK-NEXT: vmovx.f16 s7, s11
; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vmov.f32 s9, s31
; CHECK-NEXT: vmov.f32 s6, s23
; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vmov.f32 s10, s31
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vins.f16 s9, s0
; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vins.f16 s6, s0
; CHECK-NEXT: vmovx.f16 s0, s16
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q6, [r0, #64]
; CHECK-NEXT: vmov.f64 d0, d4 ; CHECK-NEXT: vmov.f64 d0, d6
; CHECK-NEXT: vmovx.f16 s20, s14 ; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vins.f16 s0, s16
; CHECK-NEXT: vins.f16 s0, s12 ; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.f32 s3, s9 ; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vins.f16 s3, s13 ; CHECK-NEXT: vmov.f32 s3, s13
; CHECK-NEXT: vmov.f32 s9, s24
; CHECK-NEXT: vins.f16 s3, s17
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s0, s8 ; CHECK-NEXT: vmovx.f16 s0, s12
; CHECK-NEXT: vmov.f32 s5, s8 ; CHECK-NEXT: vmov.f32 s10, s24
; CHECK-NEXT: vldrw.u32 q2, [r0, #64] ; CHECK-NEXT: vins.f16 s9, s0
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vdup.32 q4, r2 ; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vmov r2, s15
; CHECK-NEXT: vins.f16 s17, s0
; CHECK-NEXT: vmovx.f16 s0, s18
; CHECK-NEXT: vins.f16 s6, s0 ; CHECK-NEXT: vins.f16 s6, s0
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s9, s20
; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vmov.f32 s10, s20
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.f64 d0, d14
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov.f32 s20, s21
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov.f32 s3, s29
; CHECK-NEXT: vins.f16 s3, s5
; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s0, s28
; CHECK-NEXT: vins.f16 s9, s0
; CHECK-NEXT: vmov.f32 s5, s28
; CHECK-NEXT: vmovx.f16 s0, s10 ; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vins.f16 s20, s0 ; CHECK-NEXT: vins.f16 s6, s0
; CHECK-NEXT: vmovx.f16 s0, s11 ; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.16 q5[3], r2 ; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov r2, s27 ; CHECK-NEXT: vmov q1, q4
; CHECK-NEXT: vmovx.f16 s23, s15 ; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s18, s6 ; CHECK-NEXT: vmovx.f16 s16, s26
; CHECK-NEXT: vins.f16 s23, s0 ; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vins.f16 s8, s16
; CHECK-NEXT: vmov.f32 s22, s11 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmovx.f16 s0, s21 ; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vdup.32 q1, r2
; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vins.f16 s22, s0
; CHECK-NEXT: vmovx.f16 s0, s12
; CHECK-NEXT: vmov.f32 s6, s22
; CHECK-NEXT: vldrw.u32 q6, [r0, #80]
; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vstrw.32 q4, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d14, d2
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s0, s4 ; CHECK-NEXT: vmovx.f16 s11, s7
; CHECK-NEXT: vins.f16 s28, s12 ; CHECK-NEXT: vmovx.f16 s16, s27
; CHECK-NEXT: vmov r0, s24 ; CHECK-NEXT: vmov q1, q3
; CHECK-NEXT: vmov.16 q7[4], r2 ; CHECK-NEXT: vins.f16 s11, s16
; CHECK-NEXT: vmov.f32 s8, s9 ; CHECK-NEXT: vmov.f32 s1, s7
; CHECK-NEXT: vmov.f32 s31, s5 ; CHECK-NEXT: vmov.f32 s10, s27
; CHECK-NEXT: vins.f16 s31, s13 ; CHECK-NEXT: vmovx.f16 s16, s9
; CHECK-NEXT: vmov.f32 s29, s4 ; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vins.f16 s1, s16
; CHECK-NEXT: vins.f16 s5, s0 ; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vmovx.f16 s0, s6 ; CHECK-NEXT: vins.f16 s10, s16
; CHECK-NEXT: vins.f16 s30, s0 ; CHECK-NEXT: vmovx.f16 s16, s29
; CHECK-NEXT: vmov q0, q3 ; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vmov.f32 s6, s30 ; CHECK-NEXT: vins.f16 s20, s16
; CHECK-NEXT: vmovx.f16 s12, s26 ; CHECK-NEXT: vmovx.f16 s16, s30
; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vins.f16 s4, s12
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s7, s3 ; CHECK-NEXT: vins.f16 s22, s16
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmovx.f16 s12, s27 ; CHECK-NEXT: vmov.f32 s23, s22
; CHECK-NEXT: vins.f16 s7, s12 ; CHECK-NEXT: vmov.f32 s22, s30
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vrev32.16 q3, q0
; CHECK-NEXT: vmov.f32 s6, s27 ; CHECK-NEXT: vmovx.f16 s16, s21
; CHECK-NEXT: vmovx.f16 s16, s5
; CHECK-NEXT: vdup.32 q3, r0
; CHECK-NEXT: vmov.f32 s24, s25 ; CHECK-NEXT: vmov.f32 s24, s25
; CHECK-NEXT: vins.f16 s13, s16 ; CHECK-NEXT: vins.f16 s13, s16
; CHECK-NEXT: vmovx.f16 s16, s14 ; CHECK-NEXT: vmovx.f16 s16, s14
; CHECK-NEXT: vins.f16 s6, s16 ; CHECK-NEXT: vins.f16 s22, s16
; CHECK-NEXT: vmovx.f16 s16, s1 ; CHECK-NEXT: vmovx.f16 s16, s5
; CHECK-NEXT: vins.f16 s24, s16 ; CHECK-NEXT: vins.f16 s24, s16
; CHECK-NEXT: vmovx.f16 s16, s2 ; CHECK-NEXT: vmovx.f16 s16, s6
; CHECK-NEXT: vins.f16 s26, s16 ; CHECK-NEXT: vins.f16 s26, s16
; CHECK-NEXT: vmov.f32 s14, s6 ; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s27, s26 ; CHECK-NEXT: vmov.f32 s27, s26
; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s26, s6
; CHECK-NEXT: vmov.f32 s26, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmovx.f16 s16, s25
; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vrev32.16 q0, q0
; CHECK-NEXT: vins.f16 s1, s16
; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vins.f16 s26, s16
; CHECK-NEXT: vmovx.f16 s16, s13
; CHECK-NEXT: vmov.f32 s2, s26
; CHECK-NEXT: vins.f16 s8, s16
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmovx.f16 s16, s14
; CHECK-NEXT: vins.f16 s10, s16
; CHECK-NEXT: vrev32.16 q4, q0 ; CHECK-NEXT: vrev32.16 q4, q0
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vmovx.f16 s4, s25
; CHECK-NEXT: vmov.f32 s11, s10 ; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s14 ; CHECK-NEXT: vins.f16 s17, s4
; CHECK-NEXT: vmovx.f16 s12, s9 ; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s5, s1 ; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vins.f16 s17, s12 ; CHECK-NEXT: vmovx.f16 s28, s18
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vins.f16 s26, s28
; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q7, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s29, s5
; CHECK-NEXT: vmov.f32 s30, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vstrw.32 q7, [r1]
; CHECK-NEXT: vmov.f32 s6, s2 ; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmovx.f16 s12, s18
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vldrw.u32 q3, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vmov.f32 s13, s1
; CHECK-NEXT: vstrw.32 q1, [r1, #80]
; CHECK-NEXT: vmov.f32 s14, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s9, s17
; CHECK-NEXT: vstrw.32 q3, [r1]
; CHECK-NEXT: vmov.f32 s21, s1
; CHECK-NEXT: vmov.f32 s22, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [r1, #32]
; CHECK-NEXT: vmov.f32 s29, s1
; CHECK-NEXT: vmov.f32 s30, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s18 ; CHECK-NEXT: vmov.f32 s21, s13
; CHECK-NEXT: vstrw.32 q7, [r1, #48] ; CHECK-NEXT: vstrw.32 q1, [r1, #48]
; CHECK-NEXT: vmov.f32 s25, s1 ; CHECK-NEXT: vmov.f32 s9, s1
; CHECK-NEXT: vstrw.32 q2, [r1, #16] ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s26, s2 ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q6, [r1, #64] ; CHECK-NEXT: vmov.f32 s25, s17
; CHECK-NEXT: vstrw.32 q2, [r1, #32]
; CHECK-NEXT: vmov.f32 s22, s14
; CHECK-NEXT: vstrw.32 q0, [r1, #80]
; CHECK-NEXT: vmov.f32 s26, s18
; CHECK-NEXT: vstrw.32 q5, [r1, #64]
; CHECK-NEXT: vstrw.32 q6, [r1, #16]
; CHECK-NEXT: add sp, #144 ; CHECK-NEXT: add sp, #144
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0 %s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0
%l1 = load <16 x half>, <16 x half>* %s1, align 4 %l1 = load <16 x half>, <16 x half>* %s1, align 4
%s2 = getelementptr <16 x half>, <16 x half>* %src, i32 1 %s2 = getelementptr <16 x half>, <16 x half>* %src, i32 1
%l2 = load <16 x half>, <16 x half>* %s2, align 4 %l2 = load <16 x half>, <16 x half>* %s2, align 4
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llvm/test/CodeGen/Thumb2/mve-vst4.ll

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} }
; f16 ; f16
define void @vst4_v2f16(<2 x half> *%src, <8 x half> *%dst) { define void @vst4_v2f16(<2 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vst4_v2f16: ; CHECK-LABEL: vst4_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldmia r0, {s4, s5} ; CHECK-NEXT: vldmia r0, {s4, s5}
; CHECK-NEXT: vmovx.f16 s12, s5 ; CHECK-NEXT: vldr s0, [r0, #8]
; CHECK-NEXT: ldr r0, [r0, #8] ; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmov.f64 d0, d2 ; CHECK-NEXT: vins.f16 s4, s5
; CHECK-NEXT: vdup.32 q2, r0 ; CHECK-NEXT: vmov.f32 s1, s0
; CHECK-NEXT: vins.f16 s0, s5 ; CHECK-NEXT: vmovx.f16 s14, s0
; CHECK-NEXT: vmov.f32 s1, s8 ; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vins.f16 s1, s9 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmovx.f16 s2, s4 ; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vmovx.f16 s4, s9 ; CHECK-NEXT: vmov.f32 s9, s0
; CHECK-NEXT: vins.f16 s2, s12 ; CHECK-NEXT: vins.f16 s12, s4
; CHECK-NEXT: vmovx.f16 s3, s8 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vmov.f32 s10, s12
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-NEXT: vins.f16 s14, s0
; CHECK-NEXT: vmov.f32 s11, s14
; CHECK-NEXT: vstrh.16 q2, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0 %s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0
%l1 = load <2 x half>, <2 x half>* %s1, align 4 %l1 = load <2 x half>, <2 x half>* %s1, align 4
%s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1 %s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1
%l2 = load <2 x half>, <2 x half>* %s2, align 4 %l2 = load <2 x half>, <2 x half>* %s2, align 4
%s3 = getelementptr <2 x half>, <2 x half>* %src, i32 2 %s3 = getelementptr <2 x half>, <2 x half>* %src, i32 2
%l3 = load <2 x half>, <2 x half>* %s3, align 4 %l3 = load <2 x half>, <2 x half>* %s3, align 4
%s4 = getelementptr <2 x half>, <2 x half>* %src, i32 3 %s4 = getelementptr <2 x half>, <2 x half>* %src, i32 3
%l4 = load <2 x half>, <2 x half>* %s3, align 4 %l4 = load <2 x half>, <2 x half>* %s3, align 4
%t1 = shufflevector <2 x half> %l1, <2 x half> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t1 = shufflevector <2 x half> %l1, <2 x half> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%t2 = shufflevector <2 x half> %l3, <2 x half> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t2 = shufflevector <2 x half> %l3, <2 x half> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%s = shufflevector <4 x half> %t1, <4 x half> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> %s = shufflevector <4 x half> %t1, <4 x half> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
store <8 x half> %s, <8 x half> *%dst, align 2 store <8 x half> %s, <8 x half> *%dst, align 2
ret void ret void
} }
define void @vst4_v4f16(<4 x half> *%src, <16 x half> *%dst) { define void @vst4_v4f16(<4 x half> *%src, <16 x half> *%dst) {
; CHECK-LABEL: vst4_v4f16: ; CHECK-LABEL: vst4_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: ldrd lr, r12, [r0] ; CHECK-NEXT: ldrd lr, r12, [r0]
; CHECK-NEXT: ldrd r3, r2, [r0, #8] ; CHECK-NEXT: ldrd r3, r2, [r0, #8]
; CHECK-NEXT: ldrd r4, r0, [r0, #16] ; CHECK-NEXT: vmov.32 q0[0], lr
; CHECK-NEXT: vmov q0[2], q0[0], lr, r3 ; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: vmov q0[3], q0[1], r12, r2 ; CHECK-NEXT: vmov.32 q0[1], r12
; CHECK-NEXT: vmov q1[2], q1[0], r4, r4 ; CHECK-NEXT: vmov.32 q1[1], r2
; CHECK-NEXT: ldrd r2, r0, [r0, #16]
; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov q1[3], q1[1], r0, r0
; CHECK-NEXT: vins.f16 s8, s3
; CHECK-NEXT: vmovx.f16 s12, s3 ; CHECK-NEXT: vmovx.f16 s12, s3
; CHECK-NEXT: vins.f16 s8, s5
; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmov.f32 s6, s4
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov.f32 s9, s5 ; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vins.f16 s9, s7 ; CHECK-NEXT: vins.f16 s9, s5
; CHECK-NEXT: vmovx.f16 s10, s1 ; CHECK-NEXT: vmovx.f16 s10, s1
; CHECK-NEXT: vins.f16 s10, s12 ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmovx.f16 s12, s7 ; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vmovx.f16 s11, s5 ; CHECK-NEXT: vmovx.f16 s11, s5
; CHECK-NEXT: vins.f16 s11, s12 ; CHECK-NEXT: vins.f16 s11, s12
; CHECK-NEXT: vstrh.16 q2, [r1, #16] ; CHECK-NEXT: vstrh.16 q2, [r1, #16]
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vins.f16 s0, s2 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmovx.f16 s3, s4 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vins.f16 s4, s6 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov.f32 s1, s4 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmovx.f16 s10, s2 ; CHECK-NEXT: vmovx.f16 s10, s2
; CHECK-NEXT: vins.f16 s8, s10 ; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vmovx.f16 s4, s6 ; CHECK-NEXT: vmovx.f16 s4, s6
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0 %s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
%l1 = load <4 x half>, <4 x half>* %s1, align 4 %l1 = load <4 x half>, <4 x half>* %s1, align 4
%s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1 %s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1
%l2 = load <4 x half>, <4 x half>* %s2, align 4 %l2 = load <4 x half>, <4 x half>* %s2, align 4
%s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2 %s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2
%l3 = load <4 x half>, <4 x half>* %s3, align 4 %l3 = load <4 x half>, <4 x half>* %s3, align 4
%s4 = getelementptr <4 x half>, <4 x half>* %src, i32 3 %s4 = getelementptr <4 x half>, <4 x half>* %src, i32 3
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