Index: llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
+++ llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
@@ -16,6 +16,7 @@
 #include "AMDGPU.h"
 #include "GCNSubtarget.h"
 #include "SIMachineFunctionInfo.h"
+#include "SIInstrInfo.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/LiveRegMatrix.h"
@@ -68,6 +69,8 @@
 
   const SIRegisterInfo *TRI;
 
+  const SIInstrInfo *TII;
+
   VirtRegMap *VRM;
 
   LiveRegMatrix *LRM;
@@ -192,7 +195,8 @@
 
       const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
 
-      if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
+      if (Def && ((Def->isCopy() && Def->getOperand(1).getReg() == PhysReg) ||
+                  TII->isSpill(*Def)))
         return NSA_Status::FIXED;
 
       for (auto U : MRI->use_nodbg_operands(Reg)) {
@@ -223,6 +227,7 @@
 
   MRI = &MF.getRegInfo();
   TRI = ST->getRegisterInfo();
+  TII = ST->getInstrInfo();
   VRM = &getAnalysis<VirtRegMap>();
   LRM = &getAnalysis<LiveRegMatrix>();
   LIS = &getAnalysis<LiveIntervals>();
Index: llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
+++ llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
@@ -33,6 +33,7 @@
 #include "AMDGPU.h"
 #include "GCNSubtarget.h"
 #include "SIMachineFunctionInfo.h"
+#include "SIInstrInfo.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/LiveIntervals.h"
@@ -154,6 +155,8 @@
 
   const SIRegisterInfo *TRI;
 
+  const SIInstrInfo *TII;
+
   MachineLoopInfo *MLI;
 
   VirtRegMap *VRM;
@@ -475,7 +478,8 @@
 
   Register PhysReg = VRM->getPhys(Reg);
 
-  if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
+  if (Def && ((Def->isCopy() && Def->getOperand(1).getReg() == PhysReg) ||
+              TII->isSpill(*Def)))
     return false;
 
   for (auto U : MRI->use_nodbg_operands(Reg)) {
@@ -800,6 +804,7 @@
 
   MRI = &MF.getRegInfo();
   TRI = ST->getRegisterInfo();
+  TII = ST->getInstrInfo();
   MLI = &getAnalysis<MachineLoopInfo>();
   VRM = &getAnalysis<VirtRegMap>();
   LRM = &getAnalysis<LiveRegMatrix>();
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -570,6 +570,16 @@
     return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
   }
 
+  static bool isSpill(const MachineInstr &MI) {
+    return MI.getDesc().TSFlags &
+           (SIInstrFlags::VGPRSpill | SIInstrFlags::SGPRSpill);
+  }
+
+  bool isSpill(uint16_t Opcode) const {
+    return get(Opcode).TSFlags &
+           (SIInstrFlags::VGPRSpill | SIInstrFlags::SGPRSpill);
+  }
+
   static bool isDPP(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & SIInstrFlags::DPP;
   }
Index: llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
@@ -0,0 +1,59 @@
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass greedy,amdgpu-nsa-reassign,virtregrewriter -o - %s | FileCheck -check-prefix=GCN %s
+
+# GCN-LABEL: name: nsa_reassign
+# GCN: IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10 killed renamable $vgpr0, killed renamable $vgpr1, killed renamable $vgpr2, killed renamable $vgpr3, killed renamable $vgpr4,
+---
+name:            nsa_reassign
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sgpr_256, preferred-register: '$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7' }
+  - { id: 1, class: sgpr_128, preferred-register: '$sgpr8_sgpr9_sgpr10_sgpr11' }
+  - { id: 2, class: vgpr_32, preferred-register: '$vgpr2' }
+  - { id: 3, class: vgpr_32, preferred-register: '$vgpr4' }
+  - { id: 4, class: vgpr_32, preferred-register: '$vgpr6' }
+  - { id: 5, class: vgpr_32, preferred-register: '$vgpr8' }
+  - { id: 6, class: vgpr_32, preferred-register: '$vgpr10' }
+  - { id: 7, class: vgpr_32, preferred-register: '$vgpr0' }
+body:             |
+  bb.0:
+    %0 = IMPLICIT_DEF
+    %1 = IMPLICIT_DEF
+    %2 = IMPLICIT_DEF
+    %3 = IMPLICIT_DEF
+    %4 = IMPLICIT_DEF
+    %5 = IMPLICIT_DEF
+    %6 = IMPLICIT_DEF
+    %7:vgpr_32 = IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10 %2, %3, %4, %5, %6, %0, %1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "ImageResource")
+    S_ENDPGM 0, implicit %7
+...
+
+# GCN-LABEL: do_not_reassign_spill
+# GCN: IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10 killed renamable $vgpr2, killed renamable $vgpr4, killed renamable $vgpr6, killed renamable $vgpr8, killed renamable $vgpr10,
+---
+name:            do_not_reassign_spill
+tracksRegLiveness: true
+machineFunctionInfo:
+  stackPtrOffsetReg:  $sgpr32
+stack:
+  - { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
+registers:
+  - { id: 0, class: sgpr_256, preferred-register: '$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7' }
+  - { id: 1, class: sgpr_128, preferred-register: '$sgpr8_sgpr9_sgpr10_sgpr11' }
+  - { id: 2, class: vgpr_32, preferred-register: '$vgpr2' }
+  - { id: 3, class: vgpr_32, preferred-register: '$vgpr4' }
+  - { id: 4, class: vgpr_32, preferred-register: '$vgpr6' }
+  - { id: 5, class: vgpr_32, preferred-register: '$vgpr8' }
+  - { id: 6, class: vgpr_32, preferred-register: '$vgpr10' }
+  - { id: 7, class: vgpr_32, preferred-register: '$vgpr0' }
+body:             |
+  bb.0:
+    %0 = IMPLICIT_DEF
+    %1 = IMPLICIT_DEF
+    %2 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec
+    %3 = IMPLICIT_DEF
+    %4 = IMPLICIT_DEF
+    %5 = IMPLICIT_DEF
+    %6 = IMPLICIT_DEF
+    %7:vgpr_32 = IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10 %2, %3, %4, %5, %6, %0, %1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "ImageResource")
+    S_ENDPGM 0, implicit %7
+...
Index: llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
+++ llvm/test/CodeGen/AMDGPU/regbank-reassign.mir
@@ -572,3 +572,23 @@
     %4 = V_ADD_F64_e64 0, %0.sub0_sub1:vreg_128, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec
     S_ENDPGM 0
 ...
+# GCN-LABEL: do_not_reassign_spill{{$}}
+# GCN: V_AND_B32_e32 killed $vgpr5, killed $vgpr1,
+---
+name:            do_not_reassign_spill
+tracksRegLiveness: true
+machineFunctionInfo:
+  stackPtrOffsetReg:  $sgpr32
+stack:
+  - { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '$vgpr1' }
+  - { id: 1, class: vgpr_32, preferred-register: '$vgpr5' }
+  - { id: 2, class: vgpr_32 }
+body: |
+  bb.0:
+    %0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec
+    %1 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec
+    %2 = V_AND_B32_e32 %1, %0, implicit $exec
+    S_ENDPGM 0
+...