Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -1890,8 +1890,13 @@
   def : Pat<(insertelt (v4f32 MQPR:$src1), (f32 SPR:$src2), imm:$lane),
             (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), SPR:$src2, (SSubReg_f32_reg imm:$lane))>;
 
-  def : Pat<(insertelt (v8f16 MQPR:$src1), (f16 HPR:$src2), imm:$lane),
+  def : Pat<(insertelt (v8f16 MQPR:$src1), (f16 HPR:$src2), imm_even:$lane),
             (MVE_VMOV_to_lane_16 MQPR:$src1, (COPY_TO_REGCLASS (f16 HPR:$src2), rGPR), imm:$lane)>;
+  def : Pat<(insertelt (v8f16 MQPR:$src1), (f16 HPR:$src2), imm_odd:$lane),
+            (COPY_TO_REGCLASS (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)),
+                                (VINSH (EXTRACT_SUBREG MQPR:$src1, (SSubReg_f16_reg imm_odd:$lane)),
+                                       (COPY_TO_REGCLASS HPR:$src2, SPR)),
+                                (SSubReg_f16_reg imm_odd:$lane)), MQPR)>;
   def : Pat<(extractelt (v8f16 MQPR:$src), imm_even:$lane),
             (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_even:$lane))>;
   def : Pat<(extractelt (v8f16 MQPR:$src), imm_odd:$lane),
Index: llvm/test/CodeGen/Thumb2/mve-masked-load.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-masked-load.ll
+++ llvm/test/CodeGen/Thumb2/mve-masked-load.ll
@@ -1500,8 +1500,7 @@
 ; CHECK-LE-NEXT:    ldrh r2, [r0, #2]
 ; CHECK-LE-NEXT:    strh.w r2, [sp, #24]
 ; CHECK-LE-NEXT:    vldr.16 s4, [sp, #24]
-; CHECK-LE-NEXT:    vmov r2, s4
-; CHECK-LE-NEXT:    vmov.16 q0[1], r2
+; CHECK-LE-NEXT:    vins.f16 s0, s4
 ; CHECK-LE-NEXT:    lsls r2, r1, #29
 ; CHECK-LE-NEXT:    bpl .LBB45_3
 ; CHECK-LE-NEXT:  .LBB45_11: @ %cond.load4
@@ -1516,8 +1515,7 @@
 ; CHECK-LE-NEXT:    ldrh r2, [r0, #6]
 ; CHECK-LE-NEXT:    strh.w r2, [sp, #16]
 ; CHECK-LE-NEXT:    vldr.16 s4, [sp, #16]
-; CHECK-LE-NEXT:    vmov r2, s4
-; CHECK-LE-NEXT:    vmov.16 q0[3], r2
+; CHECK-LE-NEXT:    vins.f16 s1, s4
 ; CHECK-LE-NEXT:    lsls r2, r1, #27
 ; CHECK-LE-NEXT:    bpl .LBB45_5
 ; CHECK-LE-NEXT:  .LBB45_13: @ %cond.load10
@@ -1532,8 +1530,7 @@
 ; CHECK-LE-NEXT:    ldrh r2, [r0, #10]
 ; CHECK-LE-NEXT:    strh.w r2, [sp, #8]
 ; CHECK-LE-NEXT:    vldr.16 s4, [sp, #8]
-; CHECK-LE-NEXT:    vmov r2, s4
-; CHECK-LE-NEXT:    vmov.16 q0[5], r2
+; CHECK-LE-NEXT:    vins.f16 s2, s4
 ; CHECK-LE-NEXT:    lsls r2, r1, #25
 ; CHECK-LE-NEXT:    bpl .LBB45_7
 ; CHECK-LE-NEXT:  .LBB45_15: @ %cond.load16
@@ -1548,8 +1545,7 @@
 ; CHECK-LE-NEXT:    ldrh r0, [r0, #14]
 ; CHECK-LE-NEXT:    strh.w r0, [sp]
 ; CHECK-LE-NEXT:    vldr.16 s4, [sp]
-; CHECK-LE-NEXT:    vmov r0, s4
-; CHECK-LE-NEXT:    vmov.16 q0[7], r0
+; CHECK-LE-NEXT:    vins.f16 s3, s4
 ; CHECK-LE-NEXT:    add sp, #40
 ; CHECK-LE-NEXT:    bx lr
 ;
@@ -1614,8 +1610,7 @@
 ; CHECK-BE-NEXT:    ldrh r0, [r0, #14]
 ; CHECK-BE-NEXT:    strh.w r0, [sp]
 ; CHECK-BE-NEXT:    vldr.16 s0, [sp]
-; CHECK-BE-NEXT:    vmov r0, s0
-; CHECK-BE-NEXT:    vmov.16 q1[7], r0
+; CHECK-BE-NEXT:    vins.f16 s7, s0
 ; CHECK-BE-NEXT:  .LBB45_9: @ %else20
 ; CHECK-BE-NEXT:    vrev64.16 q0, q1
 ; CHECK-BE-NEXT:    add sp, #40
@@ -1630,8 +1625,7 @@
 ; CHECK-BE-NEXT:    ldrh r2, [r0, #2]
 ; CHECK-BE-NEXT:    strh.w r2, [sp, #24]
 ; CHECK-BE-NEXT:    vldr.16 s0, [sp, #24]
-; CHECK-BE-NEXT:    vmov r2, s0
-; CHECK-BE-NEXT:    vmov.16 q1[1], r2
+; CHECK-BE-NEXT:    vins.f16 s4, s0
 ; CHECK-BE-NEXT:    lsls r2, r1, #29
 ; CHECK-BE-NEXT:    bpl .LBB45_3
 ; CHECK-BE-NEXT:  .LBB45_12: @ %cond.load4
@@ -1646,8 +1640,7 @@
 ; CHECK-BE-NEXT:    ldrh r2, [r0, #6]
 ; CHECK-BE-NEXT:    strh.w r2, [sp, #16]
 ; CHECK-BE-NEXT:    vldr.16 s0, [sp, #16]
-; CHECK-BE-NEXT:    vmov r2, s0
-; CHECK-BE-NEXT:    vmov.16 q1[3], r2
+; CHECK-BE-NEXT:    vins.f16 s5, s0
 ; CHECK-BE-NEXT:    lsls r2, r1, #27
 ; CHECK-BE-NEXT:    bpl .LBB45_5
 ; CHECK-BE-NEXT:  .LBB45_14: @ %cond.load10
@@ -1662,8 +1655,7 @@
 ; CHECK-BE-NEXT:    ldrh r2, [r0, #10]
 ; CHECK-BE-NEXT:    strh.w r2, [sp, #8]
 ; CHECK-BE-NEXT:    vldr.16 s0, [sp, #8]
-; CHECK-BE-NEXT:    vmov r2, s0
-; CHECK-BE-NEXT:    vmov.16 q1[5], r2
+; CHECK-BE-NEXT:    vins.f16 s6, s0
 ; CHECK-BE-NEXT:    lsls r2, r1, #25
 ; CHECK-BE-NEXT:    bpl .LBB45_7
 ; CHECK-BE-NEXT:  .LBB45_16: @ %cond.load16
Index: llvm/test/CodeGen/Thumb2/mve-shuffle.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-shuffle.ll
+++ llvm/test/CodeGen/Thumb2/mve-shuffle.ll
@@ -1309,8 +1309,7 @@
 define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) {
 ; CHECK-LABEL: oneoff21_f16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov r0, s0
-; CHECK-NEXT:    vmov.16 q1[3], r0
+; CHECK-NEXT:    vins.f16 s5, s0
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
Index: llvm/test/CodeGen/Thumb2/mve-vst3.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-vst3.ll
+++ llvm/test/CodeGen/Thumb2/mve-vst3.ll
@@ -1461,9 +1461,9 @@
 ; CHECK-NEXT:    vins.f16 s2, s20
 ; CHECK-NEXT:    vmovx.f16 s20, s10
 ; CHECK-NEXT:    vins.f16 s20, s24
-; CHECK-NEXT:    vmov r0, s11
-; CHECK-NEXT:    vmov.16 q5[3], r0
 ; CHECK-NEXT:    vmovx.f16 s24, s7
+; CHECK-NEXT:    vins.f16 s21, s11
+; CHECK-NEXT:    vmov.f32 s18, s2
 ; CHECK-NEXT:    vmovx.f16 s23, s11
 ; CHECK-NEXT:    vrev32.16 q2, q2
 ; CHECK-NEXT:    vins.f16 s23, s24
@@ -1479,23 +1479,22 @@
 ; CHECK-NEXT:    vins.f16 s4, s28
 ; CHECK-NEXT:    vmovx.f16 s28, s14
 ; CHECK-NEXT:    vins.f16 s6, s28
-; CHECK-NEXT:    vmov.f32 s18, s2
+; CHECK-NEXT:    vmov.f32 s26, s22
 ; CHECK-NEXT:    vmov.f32 s7, s6
 ; CHECK-NEXT:    vmov.f32 s6, s14
 ; CHECK-NEXT:    vmovx.f16 s12, s5
 ; CHECK-NEXT:    vins.f16 s9, s12
 ; CHECK-NEXT:    vmovx.f16 s12, s10
 ; CHECK-NEXT:    vins.f16 s6, s12
-; CHECK-NEXT:    vmov.f32 s26, s22
-; CHECK-NEXT:    vmov.f32 s10, s6
 ; CHECK-NEXT:    vmov.f32 s1, s17
+; CHECK-NEXT:    vmov.f32 s10, s6
 ; CHECK-NEXT:    vmov.f32 s21, s25
 ; CHECK-NEXT:    vmov.f32 s5, s9
 ; CHECK-NEXT:    vmov.f32 s2, s18
-; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    vmov.f32 s22, s26
-; CHECK-NEXT:    vmov.f32 s6, s10
+; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    vstrw.32 q5, [r1, #32]
+; CHECK-NEXT:    vmov.f32 s6, s10
 ; CHECK-NEXT:    vstrw.32 q1, [r1, #16]
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14}
 ; CHECK-NEXT:    bx lr
@@ -1518,146 +1517,147 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT:    .pad #144
-; CHECK-NEXT:    sub sp, #144
-; CHECK-NEXT:    vldrw.u32 q2, [r0, #48]
-; CHECK-NEXT:    vldrw.u32 q5, [r0, #80]
-; CHECK-NEXT:    vldrw.u32 q7, [r0, #16]
-; CHECK-NEXT:    vldrw.u32 q4, [r0, #32]
-; CHECK-NEXT:    vmovx.f16 s0, s22
-; CHECK-NEXT:    vmovx.f16 s4, s10
+; CHECK-NEXT:    .pad #160
+; CHECK-NEXT:    sub sp, #160
+; CHECK-NEXT:    vldrw.u32 q1, [r0, #80]
+; CHECK-NEXT:    vldrw.u32 q4, [r0, #48]
+; CHECK-NEXT:    vldrw.u32 q3, [r0, #16]
+; CHECK-NEXT:    vldrw.u32 q5, [r0]
+; CHECK-NEXT:    vmovx.f16 s0, s6
+; CHECK-NEXT:    vmov q2, q1
+; CHECK-NEXT:    vstrw.32 q1, [sp, #16] @ 16-byte Spill
+; CHECK-NEXT:    vmovx.f16 s4, s18
 ; CHECK-NEXT:    vins.f16 s4, s0
-; CHECK-NEXT:    vmov r2, s11
-; CHECK-NEXT:    vmov.16 q1[3], r2
-; CHECK-NEXT:    vmovx.f16 s0, s23
-; CHECK-NEXT:    vmovx.f16 s7, s11
-; CHECK-NEXT:    vstrw.32 q2, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT:    vmovx.f16 s0, s11
+; CHECK-NEXT:    vins.f16 s5, s19
+; CHECK-NEXT:    vldrw.u32 q6, [r0, #64]
+; CHECK-NEXT:    vmovx.f16 s7, s19
+; CHECK-NEXT:    vmov.f64 d14, d6
 ; CHECK-NEXT:    vins.f16 s7, s0
-; CHECK-NEXT:    vmov.f32 s9, s31
-; CHECK-NEXT:    vmov.f32 s6, s23
+; CHECK-NEXT:    vstrw.32 q3, [sp] @ 16-byte Spill
+; CHECK-NEXT:    vstrw.32 q4, [sp, #48] @ 16-byte Spill
+; CHECK-NEXT:    vmov.f32 s6, s11
 ; CHECK-NEXT:    vmovx.f16 s0, s5
-; CHECK-NEXT:    vmov.f32 s10, s31
-; CHECK-NEXT:    vldrw.u32 q3, [r0]
+; CHECK-NEXT:    vmov.f32 s9, s15
+; CHECK-NEXT:    vins.f16 s28, s16
+; CHECK-NEXT:    vmov.f32 s10, s15
 ; CHECK-NEXT:    vins.f16 s9, s0
 ; CHECK-NEXT:    vmovx.f16 s0, s10
 ; CHECK-NEXT:    vins.f16 s6, s0
-; CHECK-NEXT:    vmovx.f16 s0, s16
-; CHECK-NEXT:    vmov r2, s0
-; CHECK-NEXT:    vldrw.u32 q6, [r0, #64]
-; CHECK-NEXT:    vmov.f64 d0, d6
-; CHECK-NEXT:    vstrw.32 q1, [sp, #128] @ 16-byte Spill
-; CHECK-NEXT:    vins.f16 s0, s16
 ; CHECK-NEXT:    vmov.f32 s10, s6
-; CHECK-NEXT:    vmov.16 q0[4], r2
-; CHECK-NEXT:    vstrw.32 q2, [sp, #96] @ 16-byte Spill
-; CHECK-NEXT:    vmov.f32 s3, s13
+; CHECK-NEXT:    vstrw.32 q1, [sp, #112] @ 16-byte Spill
+; CHECK-NEXT:    vldrw.u32 q1, [r0, #32]
+; CHECK-NEXT:    vstrw.32 q2, [sp, #128] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s9, s24
-; CHECK-NEXT:    vins.f16 s3, s17
-; CHECK-NEXT:    vmov q1, q0
-; CHECK-NEXT:    vmovx.f16 s0, s12
-; CHECK-NEXT:    vmov.f32 s10, s24
-; CHECK-NEXT:    vins.f16 s9, s0
-; CHECK-NEXT:    vmov.f32 s5, s12
-; CHECK-NEXT:    vmovx.f16 s0, s10
-; CHECK-NEXT:    vins.f16 s6, s0
-; CHECK-NEXT:    vmov.f32 s10, s6
-; CHECK-NEXT:    vstrw.32 q1, [sp, #64] @ 16-byte Spill
-; CHECK-NEXT:    vldrw.u32 q1, [sp, #112] @ 16-byte Reload
-; CHECK-NEXT:    vstrw.32 q2, [sp, #80] @ 16-byte Spill
-; CHECK-NEXT:    vmov.f32 s9, s20
 ; CHECK-NEXT:    vmovx.f16 s0, s4
-; CHECK-NEXT:    vmov.f32 s10, s20
-; CHECK-NEXT:    vmov r0, s0
-; CHECK-NEXT:    vmov.f64 d0, d14
+; CHECK-NEXT:    vstrw.32 q1, [sp, #144] @ 16-byte Spill
+; CHECK-NEXT:    vmov r2, s0
+; CHECK-NEXT:    vmov.f64 d0, d10
 ; CHECK-NEXT:    vins.f16 s0, s4
-; CHECK-NEXT:    vmov.f32 s20, s21
-; CHECK-NEXT:    vmov.16 q0[4], r0
-; CHECK-NEXT:    vmov.f32 s3, s29
+; CHECK-NEXT:    vmov.f32 s10, s24
+; CHECK-NEXT:    vmov.16 q0[4], r2
+; CHECK-NEXT:    vmov.f32 s3, s21
 ; CHECK-NEXT:    vins.f16 s3, s5
 ; CHECK-NEXT:    vmov q1, q0
-; CHECK-NEXT:    vmovx.f16 s0, s28
+; CHECK-NEXT:    vmovx.f16 s0, s20
 ; CHECK-NEXT:    vins.f16 s9, s0
-; CHECK-NEXT:    vmov.f32 s5, s28
+; CHECK-NEXT:    vmov.f32 s5, s20
 ; CHECK-NEXT:    vmovx.f16 s0, s10
 ; CHECK-NEXT:    vins.f16 s6, s0
+; CHECK-NEXT:    vmovx.f16 s0, s16
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    vstrw.32 q1, [sp, #80] @ 16-byte Spill
 ; CHECK-NEXT:    vmov.f32 s10, s6
-; CHECK-NEXT:    vstrw.32 q1, [sp, #32] @ 16-byte Spill
-; CHECK-NEXT:    vmov q1, q4
-; CHECK-NEXT:    vstrw.32 q2, [sp, #48] @ 16-byte Spill
-; CHECK-NEXT:    vmovx.f16 s16, s26
-; CHECK-NEXT:    vmovx.f16 s8, s6
-; CHECK-NEXT:    vins.f16 s8, s16
-; CHECK-NEXT:    vmov r0, s7
-; CHECK-NEXT:    vmov.16 q2[3], r0
-; CHECK-NEXT:    vstrw.32 q1, [sp] @ 16-byte Spill
-; CHECK-NEXT:    vmovx.f16 s11, s7
-; CHECK-NEXT:    vmovx.f16 s16, s27
-; CHECK-NEXT:    vmov q1, q3
-; CHECK-NEXT:    vins.f16 s11, s16
-; CHECK-NEXT:    vmov.f32 s1, s7
+; CHECK-NEXT:    vldrw.u32 q1, [sp, #16] @ 16-byte Reload
+; CHECK-NEXT:    vmov.16 q7[4], r0
+; CHECK-NEXT:    vstrw.32 q2, [sp, #96] @ 16-byte Spill
+; CHECK-NEXT:    vmov.f32 s31, s13
+; CHECK-NEXT:    vmovx.f16 s0, s12
+; CHECK-NEXT:    vmov.f32 s9, s4
+; CHECK-NEXT:    vins.f16 s31, s17
+; CHECK-NEXT:    vmov.f32 s10, s4
+; CHECK-NEXT:    vins.f16 s9, s0
+; CHECK-NEXT:    vmov.f32 s29, s12
+; CHECK-NEXT:    vmovx.f16 s0, s10
+; CHECK-NEXT:    vmovx.f16 s12, s26
+; CHECK-NEXT:    vins.f16 s30, s0
+; CHECK-NEXT:    vldrw.u32 q0, [sp, #144] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s10, s30
+; CHECK-NEXT:    vstrw.32 q2, [sp, #64] @ 16-byte Spill
+; CHECK-NEXT:    vmovx.f16 s8, s2
+; CHECK-NEXT:    vins.f16 s8, s12
+; CHECK-NEXT:    vmovx.f16 s12, s27
+; CHECK-NEXT:    vins.f16 s9, s3
+; CHECK-NEXT:    vmovx.f16 s11, s3
+; CHECK-NEXT:    vmov q0, q5
+; CHECK-NEXT:    vins.f16 s11, s12
+; CHECK-NEXT:    vmov.f32 s13, s23
 ; CHECK-NEXT:    vmov.f32 s10, s27
 ; CHECK-NEXT:    vmovx.f16 s16, s9
-; CHECK-NEXT:    vmov.f32 s2, s7
-; CHECK-NEXT:    vins.f16 s1, s16
-; CHECK-NEXT:    vmovx.f16 s16, s2
+; CHECK-NEXT:    vmov.f32 s14, s23
+; CHECK-NEXT:    vmov q5, q1
+; CHECK-NEXT:    vins.f16 s13, s16
+; CHECK-NEXT:    vmovx.f16 s16, s14
 ; CHECK-NEXT:    vins.f16 s10, s16
-; CHECK-NEXT:    vmovx.f16 s16, s29
-; CHECK-NEXT:    vmov.f32 s2, s10
+; CHECK-NEXT:    vmov.f32 s20, s21
+; CHECK-NEXT:    vmov.f32 s14, s10
+; CHECK-NEXT:    vstrw.32 q3, [sp, #32] @ 16-byte Spill
+; CHECK-NEXT:    vldrw.u32 q3, [sp] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s24, s25
+; CHECK-NEXT:    vmovx.f16 s16, s13
+; CHECK-NEXT:    vmov q1, q3
 ; CHECK-NEXT:    vins.f16 s20, s16
-; CHECK-NEXT:    vmovx.f16 s16, s30
-; CHECK-NEXT:    vstrw.32 q0, [sp, #16] @ 16-byte Spill
+; CHECK-NEXT:    vmovx.f16 s16, s14
 ; CHECK-NEXT:    vins.f16 s22, s16
-; CHECK-NEXT:    vldrw.u32 q0, [sp, #112] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s23, s22
-; CHECK-NEXT:    vmov.f32 s22, s30
-; CHECK-NEXT:    vrev32.16 q3, q0
+; CHECK-NEXT:    vmov.f32 s22, s6
+; CHECK-NEXT:    vldrw.u32 q1, [sp, #48] @ 16-byte Reload
 ; CHECK-NEXT:    vmovx.f16 s16, s21
-; CHECK-NEXT:    vmov.f32 s24, s25
-; CHECK-NEXT:    vins.f16 s13, s16
-; CHECK-NEXT:    vmovx.f16 s16, s14
+; CHECK-NEXT:    vrev32.16 q1, q1
+; CHECK-NEXT:    vins.f16 s5, s16
+; CHECK-NEXT:    vmovx.f16 s16, s6
 ; CHECK-NEXT:    vins.f16 s22, s16
-; CHECK-NEXT:    vmovx.f16 s16, s5
+; CHECK-NEXT:    vmovx.f16 s16, s1
 ; CHECK-NEXT:    vins.f16 s24, s16
-; CHECK-NEXT:    vmovx.f16 s16, s6
+; CHECK-NEXT:    vmovx.f16 s16, s2
 ; CHECK-NEXT:    vins.f16 s26, s16
-; CHECK-NEXT:    vldrw.u32 q0, [sp] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s6, s22
 ; CHECK-NEXT:    vmov.f32 s27, s26
-; CHECK-NEXT:    vmov.f32 s26, s6
-; CHECK-NEXT:    vrev32.16 q4, q0
+; CHECK-NEXT:    vstrw.32 q1, [sp, #48] @ 16-byte Spill
+; CHECK-NEXT:    vmov.f32 s26, s2
+; CHECK-NEXT:    vldrw.u32 q0, [sp, #144] @ 16-byte Reload
 ; CHECK-NEXT:    vmovx.f16 s4, s25
-; CHECK-NEXT:    vldrw.u32 q0, [sp, #96] @ 16-byte Reload
+; CHECK-NEXT:    vrev32.16 q4, q0
+; CHECK-NEXT:    vldrw.u32 q0, [sp, #128] @ 16-byte Reload
 ; CHECK-NEXT:    vins.f16 s17, s4
-; CHECK-NEXT:    vldrw.u32 q1, [sp, #128] @ 16-byte Reload
-; CHECK-NEXT:    vmov.f32 s5, s1
-; CHECK-NEXT:    vmovx.f16 s28, s18
-; CHECK-NEXT:    vmov.f32 s6, s2
-; CHECK-NEXT:    vins.f16 s26, s28
-; CHECK-NEXT:    vstrw.32 q1, [sp, #128] @ 16-byte Spill
-; CHECK-NEXT:    vldrw.u32 q1, [sp, #80] @ 16-byte Reload
-; CHECK-NEXT:    vldrw.u32 q7, [sp, #64] @ 16-byte Reload
-; CHECK-NEXT:    vmov.f32 s14, s22
+; CHECK-NEXT:    vmovx.f16 s12, s18
+; CHECK-NEXT:    vins.f16 s26, s12
+; CHECK-NEXT:    vldrw.u32 q3, [sp, #112] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s13, s1
+; CHECK-NEXT:    vldrw.u32 q1, [sp, #96] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s14, s2
+; CHECK-NEXT:    vldrw.u32 q0, [sp, #80] @ 16-byte Reload
+; CHECK-NEXT:    vmov.f32 s1, s5
+; CHECK-NEXT:    vstrw.32 q3, [r1, #80]
+; CHECK-NEXT:    vmov.f32 s2, s6
+; CHECK-NEXT:    vldrw.u32 q1, [sp, #64] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s18, s26
-; CHECK-NEXT:    vldrw.u32 q0, [sp, #48] @ 16-byte Reload
+; CHECK-NEXT:    vstrw.32 q0, [r1]
 ; CHECK-NEXT:    vmov.f32 s29, s5
 ; CHECK-NEXT:    vmov.f32 s30, s6
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #32] @ 16-byte Reload
-; CHECK-NEXT:    vmov.f32 s5, s1
-; CHECK-NEXT:    vstrw.32 q7, [r1]
-; CHECK-NEXT:    vmov.f32 s6, s2
-; CHECK-NEXT:    vldrw.u32 q0, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT:    vmov.f32 s21, s13
-; CHECK-NEXT:    vstrw.32 q1, [r1, #48]
-; CHECK-NEXT:    vmov.f32 s9, s1
-; CHECK-NEXT:    vmov.f32 s10, s2
-; CHECK-NEXT:    vldrw.u32 q0, [sp, #128] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f32 s25, s17
+; CHECK-NEXT:    vstrw.32 q7, [r1, #48]
+; CHECK-NEXT:    vmov.f32 s9, s5
+; CHECK-NEXT:    vmov.f32 s10, s6
+; CHECK-NEXT:    vldrw.u32 q1, [sp, #48] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q2, [r1, #32]
-; CHECK-NEXT:    vmov.f32 s22, s14
-; CHECK-NEXT:    vstrw.32 q0, [r1, #80]
+; CHECK-NEXT:    vmov.f32 s21, s5
+; CHECK-NEXT:    vmov.f32 s22, s6
 ; CHECK-NEXT:    vmov.f32 s26, s18
 ; CHECK-NEXT:    vstrw.32 q5, [r1, #64]
 ; CHECK-NEXT:    vstrw.32 q6, [r1, #16]
-; CHECK-NEXT:    add sp, #144
+; CHECK-NEXT:    add sp, #160
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    bx lr
 entry: