Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -7982,7 +7982,8 @@
         VT.getVectorElementType() == MVT::f32)
       return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
     // vrev <4 x i16> -> VREV32
-    if (VT.getVectorElementType() == MVT::i16)
+    if (VT.getVectorElementType() == MVT::i16 ||
+        VT.getVectorElementType() == MVT::f16)
       return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
     // vrev <4 x i8> -> VREV16
     assert(VT.getVectorElementType() == MVT::i8);
Index: llvm/test/CodeGen/ARM/fp16-insert-extract.ll
===================================================================
--- llvm/test/CodeGen/ARM/fp16-insert-extract.ll
+++ llvm/test/CodeGen/ARM/fp16-insert-extract.ll
@@ -167,3 +167,131 @@
   %x = insertelement <8 x half> %a, half %b, i32 7
   ret <8 x half> %x
 }
+
+define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
+; CHECKHARD-LABEL: shuffle3step_f16:
+; CHECKHARD:       @ %bb.0: @ %entry
+; CHECKHARD-NEXT:    vmov r1, s0
+; CHECKHARD-NEXT:    vmovx.f16 s12, s1
+; CHECKHARD-NEXT:    vmov r0, s12
+; CHECKHARD-NEXT:    vext.16 d16, d4, d5, #2
+; CHECKHARD-NEXT:    vmovx.f16 s12, s4
+; CHECKHARD-NEXT:    vdup.16 q11, d3[1]
+; CHECKHARD-NEXT:    vrev32.16 d17, d16
+; CHECKHARD-NEXT:    vext.16 d16, d16, d17, #3
+; CHECKHARD-NEXT:    vrev32.16 d17, d3
+; CHECKHARD-NEXT:    vext.16 d17, d17, d3, #1
+; CHECKHARD-NEXT:    vext.16 d16, d16, d17, #2
+; CHECKHARD-NEXT:    vext.16 d17, d16, d16, #2
+; CHECKHARD-NEXT:    vmov.16 d16[0], r1
+; CHECKHARD-NEXT:    vmov.16 d16[1], r0
+; CHECKHARD-NEXT:    vmov r0, s3
+; CHECKHARD-NEXT:    vmov.16 d16[2], r0
+; CHECKHARD-NEXT:    vmov r0, s12
+; CHECKHARD-NEXT:    vmovx.f16 s12, s0
+; CHECKHARD-NEXT:    vmov r1, s12
+; CHECKHARD-NEXT:    vmovx.f16 s12, s3
+; CHECKHARD-NEXT:    vmov.16 d16[3], r0
+; CHECKHARD-NEXT:    vmov r0, s2
+; CHECKHARD-NEXT:    vmov.16 d18[0], r1
+; CHECKHARD-NEXT:    vmov r1, s8
+; CHECKHARD-NEXT:    vmov.16 d18[1], r0
+; CHECKHARD-NEXT:    vmov r0, s12
+; CHECKHARD-NEXT:    vmovx.f16 s12, s9
+; CHECKHARD-NEXT:    vmov.16 d20[1], r1
+; CHECKHARD-NEXT:    vmov.16 d18[2], r0
+; CHECKHARD-NEXT:    vmov r0, s5
+; CHECKHARD-NEXT:    vmov.16 d18[3], r0
+; CHECKHARD-NEXT:    vmov r0, s12
+; CHECKHARD-NEXT:    vmov.16 d20[2], r0
+; CHECKHARD-NEXT:    vmov r0, s11
+; CHECKHARD-NEXT:    vmov.16 d20[3], r0
+; CHECKHARD-NEXT:    vmov r0, s10
+; CHECKHARD-NEXT:    vext.16 d20, d20, d22, #1
+; CHECKHARD-NEXT:    vdup.16 q11, d3[2]
+; CHECKHARD-NEXT:    vext.16 d19, d20, d20, #3
+; CHECKHARD-NEXT:    vadd.f16 q8, q8, q9
+; CHECKHARD-NEXT:    vext.16 d18, d0, d1, #2
+; CHECKHARD-NEXT:    vmovx.f16 s0, s8
+; CHECKHARD-NEXT:    vmov r1, s0
+; CHECKHARD-NEXT:    vmovx.f16 s0, s11
+; CHECKHARD-NEXT:    vext.16 d19, d18, d2, #3
+; CHECKHARD-NEXT:    vext.16 d18, d2, d18, #1
+; CHECKHARD-NEXT:    vext.16 d18, d18, d19, #2
+; CHECKHARD-NEXT:    vext.16 d18, d18, d18, #1
+; CHECKHARD-NEXT:    vmov.16 d20[1], r1
+; CHECKHARD-NEXT:    vmov.16 d20[2], r0
+; CHECKHARD-NEXT:    vmov r0, s0
+; CHECKHARD-NEXT:    vmov.16 d20[3], r0
+; CHECKHARD-NEXT:    vext.16 d20, d20, d22, #1
+; CHECKHARD-NEXT:    vext.16 d19, d20, d20, #3
+; CHECKHARD-NEXT:    vadd.f16 q0, q8, q9
+; CHECKHARD-NEXT:    bx lr
+;
+; CHECKSOFT-LABEL: shuffle3step_f16:
+; CHECKSOFT:       @ %bb.0: @ %entry
+; CHECKSOFT-NEXT:    vmov r1, s0
+; CHECKSOFT-NEXT:    vmovx.f16 s12, s1
+; CHECKSOFT-NEXT:    vmov r0, s12
+; CHECKSOFT-NEXT:    vext.16 d16, d4, d5, #2
+; CHECKSOFT-NEXT:    vmovx.f16 s12, s4
+; CHECKSOFT-NEXT:    vdup.16 q11, d3[1]
+; CHECKSOFT-NEXT:    vrev32.16 d17, d16
+; CHECKSOFT-NEXT:    vext.16 d16, d16, d17, #3
+; CHECKSOFT-NEXT:    vrev32.16 d17, d3
+; CHECKSOFT-NEXT:    vext.16 d17, d17, d3, #1
+; CHECKSOFT-NEXT:    vext.16 d16, d16, d17, #2
+; CHECKSOFT-NEXT:    vext.16 d17, d16, d16, #2
+; CHECKSOFT-NEXT:    vmov.16 d16[0], r1
+; CHECKSOFT-NEXT:    vmov.16 d16[1], r0
+; CHECKSOFT-NEXT:    vmov r0, s3
+; CHECKSOFT-NEXT:    vmov.16 d16[2], r0
+; CHECKSOFT-NEXT:    vmov r0, s12
+; CHECKSOFT-NEXT:    vmovx.f16 s12, s0
+; CHECKSOFT-NEXT:    vmov r1, s12
+; CHECKSOFT-NEXT:    vmovx.f16 s12, s3
+; CHECKSOFT-NEXT:    vmov.16 d16[3], r0
+; CHECKSOFT-NEXT:    vmov r0, s2
+; CHECKSOFT-NEXT:    vmov.16 d18[0], r1
+; CHECKSOFT-NEXT:    vmov r1, s8
+; CHECKSOFT-NEXT:    vmov.16 d18[1], r0
+; CHECKSOFT-NEXT:    vmov r0, s12
+; CHECKSOFT-NEXT:    vmovx.f16 s12, s9
+; CHECKSOFT-NEXT:    vmov.16 d20[1], r1
+; CHECKSOFT-NEXT:    vmov.16 d18[2], r0
+; CHECKSOFT-NEXT:    vmov r0, s5
+; CHECKSOFT-NEXT:    vmov.16 d18[3], r0
+; CHECKSOFT-NEXT:    vmov r0, s12
+; CHECKSOFT-NEXT:    vmov.16 d20[2], r0
+; CHECKSOFT-NEXT:    vmov r0, s11
+; CHECKSOFT-NEXT:    vmov.16 d20[3], r0
+; CHECKSOFT-NEXT:    vmov r0, s10
+; CHECKSOFT-NEXT:    vext.16 d20, d20, d22, #1
+; CHECKSOFT-NEXT:    vdup.16 q11, d3[2]
+; CHECKSOFT-NEXT:    vext.16 d19, d20, d20, #3
+; CHECKSOFT-NEXT:    vadd.f16 q8, q8, q9
+; CHECKSOFT-NEXT:    vext.16 d18, d0, d1, #2
+; CHECKSOFT-NEXT:    vmovx.f16 s0, s8
+; CHECKSOFT-NEXT:    vmov r1, s0
+; CHECKSOFT-NEXT:    vmovx.f16 s0, s11
+; CHECKSOFT-NEXT:    vext.16 d19, d18, d2, #3
+; CHECKSOFT-NEXT:    vext.16 d18, d2, d18, #1
+; CHECKSOFT-NEXT:    vext.16 d18, d18, d19, #2
+; CHECKSOFT-NEXT:    vext.16 d18, d18, d18, #1
+; CHECKSOFT-NEXT:    vmov.16 d20[1], r1
+; CHECKSOFT-NEXT:    vmov.16 d20[2], r0
+; CHECKSOFT-NEXT:    vmov r0, s0
+; CHECKSOFT-NEXT:    vmov.16 d20[3], r0
+; CHECKSOFT-NEXT:    vext.16 d20, d20, d22, #1
+; CHECKSOFT-NEXT:    vext.16 d19, d20, d20, #3
+; CHECKSOFT-NEXT:    vadd.f16 q0, q8, q9
+; CHECKSOFT-NEXT:    bx lr
+entry:
+  %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
+  %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
+  %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
+  %a = fadd <8 x half> %s1, %s2
+  %r = fadd <8 x half> %a, %s3
+  ret <8 x half> %r
+}
+