diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -623,7 +623,7 @@ can be used. For GFX7-GFX8 these are available in the :ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For - GFX9-GFX10 the aperture base addresses are directly available as inline + GFX9+ the aperture base addresses are directly available as inline constant registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64-bit address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32 which makes it easier to convert from flat to segment or @@ -693,7 +693,7 @@ instructions with the scratch buffer descriptor and per wavefront scratch offset, by the scratch instructions, or by flat instructions. Multi-dword access is not supported except by flat and scratch instructions in - GFX9-GFX10. + GFX9+. **Constant 32-bit** *TODO* @@ -2380,10 +2380,10 @@ AMDGPU does not use a segment selector so this is 0. ``minimum_instruction_length`` (ubyte) - For GFX9-GFX10 this is 4. + For GFX9+ this is 4. ``maximum_operations_per_instruction`` (ubyte) - For GFX9-GFX10 this is 1. + For GFX9+ this is 1. Source text for online-compiled programs (for example, those compiled by the OpenCL language runtime) may be embedded into the DWARF Version 5 line table. @@ -2861,12 +2861,12 @@ "NumSGPRs" integer Required Number of scalar registers used by a wavefront for - GFX6-GFX10. This + GFX6+. This includes the special SGPRs for VCC, Flat - Scratch (GFX7-GFX10) + Scratch (GFX7+) and XNACK (for - GFX8-GFX10). It does + GFX8+). It does not include the 16 SGPR added if a trap handler is @@ -2877,7 +2877,7 @@ "NumVGPRs" integer Required Number of vector registers used by each work-item for - GFX6-GFX10 + GFX6+ "MaxFlatWorkGroupSize" integer Required Maximum flat work-group size supported by the @@ -3459,10 +3459,10 @@ instructions, or by flat instructions. If each lane of a wavefront accesses the same private address, the interleaving results in adjacent dwords being accessed and hence requires fewer cache lines to be fetched. Multi-dword access is not -supported except by flat and scratch instructions in GFX9-GFX10. +supported except by flat and scratch instructions in GFX9+. The generic address space uses the hardware flat address support available in -GFX7-GFX10. This uses two fixed ranges of virtual addresses (the private and +GFX7+. This uses two fixed ranges of virtual addresses (the private and local apertures), that are outside the range of addressible global memory, to map from a flat address to a private or local address. @@ -3478,7 +3478,7 @@ apertures address can be used. For GFX7-GFX8 these are available in the :ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For -GFX9-GFX10 the aperture base addresses are directly available as inline constant +GFX9+ the aperture base addresses are directly available as inline constant registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32 which makes it easier to convert from flat to segment or segment to flat. @@ -3601,21 +3601,21 @@ ``COMPUTE_PGM_RSRC3`` configuration register. See - :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-table`. 415:384 4 bytes COMPUTE_PGM_RSRC1 Compute Shader (CS) program settings used by CP to set up ``COMPUTE_PGM_RSRC1`` configuration register. See - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. 447:416 4 bytes COMPUTE_PGM_RSRC2 Compute Shader (CS) program settings used by CP to set up ``COMPUTE_PGM_RSRC2`` configuration register. See - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. 458:448 7 bits *See separate bits below.* Enable the setup of the SGPR user data registers (see @@ -3658,8 +3658,8 @@ .. - .. table:: compute_pgm_rsrc1 for GFX6-GFX10 - :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table + .. table:: compute_pgm_rsrc1 for GFX6+ + :name: amdgpu-amdhsa-compute_pgm_rsrc1-table ======= ======= =============================== =========================================================================== Bits Size Field Name Description @@ -3876,7 +3876,7 @@ ``COMPUTE_PGM_RSRC1.CDBG_USER``. 26 1 bit FP16_OVFL GFX6-GFX8 Reserved, must be 0. - GFX9-GFX10 + GFX9+ Wavefront starts execution with specified fp16 overflow mode. @@ -3944,8 +3944,8 @@ .. - .. table:: compute_pgm_rsrc2 for GFX6-GFX10 - :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table + .. table:: compute_pgm_rsrc2 for GFX6+ + :name: amdgpu-amdhsa-compute_pgm_rsrc2-table ======= ======= =============================== =========================================================================== Bits Size Field Name Description @@ -4068,7 +4068,7 @@ GFX6: roundup(lds-size / (64 * 4)) - GFX7-GFX10: + GFX7+: roundup(lds-size / (128 * 4)) 24 1 bit ENABLE_EXCEPTION_IEEE_754_FP Wavefront starts execution @@ -4102,7 +4102,7 @@ .. .. table:: compute_pgm_rsrc3 for GFX10 - :name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table + :name: amdgpu-amdhsa-compute_pgm_rsrc3-table ======= ======= =============================== =========================================================================== Bits Size Field Name Description @@ -4237,7 +4237,7 @@ GFX7-GFX8 since it is the same value as the second SGPR of Flat Scratch Init. However, it - may be needed for GFX9-GFX10 which + may be needed for GFX9+ which changes the meaning of the Flat Scratch Init value. then Grid Work-Group Count X 1 32-bit count of the number of @@ -4332,8 +4332,8 @@ :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`. The global segment can be accessed either using buffer instructions (GFX6 which -has V# 64-bit address support), flat instructions (GFX7-GFX10), or global -instructions (GFX9-GFX10). +has V# 64-bit address support), flat instructions (GFX7+), or global +instructions (GFX9+). If buffer operations are used, then the compiler can generate a V# with the following properties: @@ -4379,7 +4379,7 @@ available in dispatch packet. For M0, it is also possible to use maximum possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for GFX7-GFX8). -GFX9-GFX10 +GFX9+ The M0 register is not used for range checking LDS accesses and so does not need to be initialized in the prolog. @@ -4586,7 +4586,7 @@ termed vector memory operations. Private address space uses ``buffer_load/store`` using the scratch V# -(GFX6-GFX8), or ``scratch_load/store`` (GFX9-GFX10). Since only a single thread +(GFX6-GFX8), or ``scratch_load/store`` (GFX9+). Since only a single thread is accessing the memory, atomic memory orderings are not meaningful, and all accesses are treated as non-atomic. @@ -6025,7 +6025,7 @@ sample instructions. In this mode vmcnt reports completion of load, atomic with return and sample instructions in order, and the vscnt reports the completion of store and atomic without return in order. See ``MEM_ORDERED`` field in -:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. +:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. Wavefronts can be executed in WGP or CU wavefront execution mode: @@ -6041,7 +6041,7 @@ work-group synchronization. See ``WGP_MODE`` field in -:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table` and +:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table` and :ref:`amdgpu-target-features`. The code sequences used to implement the memory model for GFX10 are defined in @@ -8732,7 +8732,7 @@ --------- AMDGPU backend has LLVM-MC based assembler which is currently in development. -It supports AMDGCN GFX6-GFX10. +It supports AMDGCN GFX6+. This section describes general syntax for instructions and operands. @@ -9264,105 +9264,105 @@ ======================================================== =================== ============ =================== Directive Default Supported On Description ======================================================== =================== ============ =================== - ``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX10 Controls GROUP_SEGMENT_FIXED_SIZE in + ``.amdhsa_group_segment_fixed_size`` 0 GFX6+ Controls GROUP_SEGMENT_FIXED_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX10 Controls PRIVATE_SEGMENT_FIXED_SIZE in + ``.amdhsa_private_segment_fixed_size`` 0 GFX6+ Controls PRIVATE_SEGMENT_FIXED_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_kernarg_size`` 0 GFX6-GFX10 Controls KERNARG_SIZE in + ``.amdhsa_kernarg_size`` 0 GFX6+ Controls KERNARG_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in + ``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6+ Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_PTR in + ``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6+ Controls ENABLE_SGPR_DISPATCH_PTR in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_QUEUE_PTR in + ``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6+ Controls ENABLE_SGPR_QUEUE_PTR in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in + ``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6+ Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_ID in + ``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6+ Controls ENABLE_SGPR_DISPATCH_ID in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX10 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in + ``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6+ Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in + ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6+ Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. ``.amdhsa_wavefront_size32`` Target GFX10 Controls ENABLE_WAVEFRONT_SIZE32 in Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. Specific (wavefrontsize64) - ``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX10 Controls ENABLE_PRIVATE_SEGMENT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_X in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_Y in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_Z in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_INFO in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_system_vgpr_workitem_id`` 0 GFX6-GFX10 Controls ENABLE_VGPR_WORKITEM_ID in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. + ``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6+ Controls ENABLE_PRIVATE_SEGMENT in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6+ Controls ENABLE_SGPR_WORKGROUP_ID_X in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6+ Controls ENABLE_SGPR_WORKGROUP_ID_Y in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6+ Controls ENABLE_SGPR_WORKGROUP_ID_Z in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6+ Controls ENABLE_SGPR_WORKGROUP_INFO in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_system_vgpr_workitem_id`` 0 GFX6+ Controls ENABLE_VGPR_WORKITEM_ID in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. Possible values are defined in :ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`. - ``.amdhsa_next_free_vgpr`` Required GFX6-GFX10 Maximum VGPR number explicitly referenced, plus one. + ``.amdhsa_next_free_vgpr`` Required GFX6+ Maximum VGPR number explicitly referenced, plus one. Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. - ``.amdhsa_next_free_sgpr`` Required GFX6-GFX10 Maximum SGPR number explicitly referenced, plus one. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. + ``.amdhsa_next_free_sgpr`` Required GFX6+ Maximum SGPR number explicitly referenced, plus one. Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. - ``.amdhsa_reserve_vcc`` 1 GFX6-GFX10 Whether the kernel may use the special VCC SGPR. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. + ``.amdhsa_reserve_vcc`` 1 GFX6+ Whether the kernel may use the special VCC SGPR. Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. - ``.amdhsa_reserve_flat_scratch`` 1 GFX7-GFX10 Whether the kernel may use flat instructions to access + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. + ``.amdhsa_reserve_flat_scratch`` 1 GFX7+ Whether the kernel may use flat instructions to access scratch memory. Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. - ``.amdhsa_reserve_xnack_mask`` Target GFX8-GFX10 Whether the kernel may trigger XNACK replay. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. + ``.amdhsa_reserve_xnack_mask`` Target GFX8+ Whether the kernel may trigger XNACK replay. Feature Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in - Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. + Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. (xnack) - ``.amdhsa_float_round_mode_32`` 0 GFX6-GFX10 Controls FLOAT_ROUND_MODE_32 in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. + ``.amdhsa_float_round_mode_32`` 0 GFX6+ Controls FLOAT_ROUND_MODE_32 in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. Possible values are defined in :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`. - ``.amdhsa_float_round_mode_16_64`` 0 GFX6-GFX10 Controls FLOAT_ROUND_MODE_16_64 in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. + ``.amdhsa_float_round_mode_16_64`` 0 GFX6+ Controls FLOAT_ROUND_MODE_16_64 in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. Possible values are defined in :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`. - ``.amdhsa_float_denorm_mode_32`` 0 GFX6-GFX10 Controls FLOAT_DENORM_MODE_32 in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. + ``.amdhsa_float_denorm_mode_32`` 0 GFX6+ Controls FLOAT_DENORM_MODE_32 in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. Possible values are defined in :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`. - ``.amdhsa_float_denorm_mode_16_64`` 3 GFX6-GFX10 Controls FLOAT_DENORM_MODE_16_64 in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. + ``.amdhsa_float_denorm_mode_16_64`` 3 GFX6+ Controls FLOAT_DENORM_MODE_16_64 in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. Possible values are defined in :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`. - ``.amdhsa_dx10_clamp`` 1 GFX6-GFX10 Controls ENABLE_DX10_CLAMP in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. - ``.amdhsa_ieee_mode`` 1 GFX6-GFX10 Controls ENABLE_IEEE_MODE in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. - ``.amdhsa_fp16_overflow`` 0 GFX9-GFX10 Controls FP16_OVFL in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. + ``.amdhsa_dx10_clamp`` 1 GFX6+ Controls ENABLE_DX10_CLAMP in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. + ``.amdhsa_ieee_mode`` 1 GFX6+ Controls ENABLE_IEEE_MODE in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. + ``.amdhsa_fp16_overflow`` 0 GFX9+ Controls FP16_OVFL in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. ``.amdhsa_workgroup_processor_mode`` Target GFX10 Controls ENABLE_WGP_MODE in Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. Specific (cumode) ``.amdhsa_memory_ordered`` 1 GFX10 Controls MEM_ORDERED in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. ``.amdhsa_forward_progress`` 0 GFX10 Controls FWD_PROGRESS in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. - ``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_exception_fp_denorm_src`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. - ``.amdhsa_exception_int_div_zero`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`. + ``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_exception_fp_denorm_src`` 0 GFX6+ Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. + ``.amdhsa_exception_int_div_zero`` 0 GFX6+ Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`. ======================================================== =================== ============ =================== .amdgpu_metadata