diff --git a/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h b/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h --- a/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h +++ b/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h @@ -174,6 +174,11 @@ MCSection *getSectionForJumpTable(const Function &F, const TargetMachine &TM) const override; + MCSection * + getSectionForMachineBasicBlock(const Function &F, + const MachineBasicBlock &MBB, + const TargetMachine &TM) const override; + /// Emit Obj-C garbage collection and linker options. void emitModuleMetadata(MCStreamer &Streamer, Module &M) const override; diff --git a/llvm/lib/CodeGen/BasicBlockSections.cpp b/llvm/lib/CodeGen/BasicBlockSections.cpp --- a/llvm/lib/CodeGen/BasicBlockSections.cpp +++ b/llvm/lib/CodeGen/BasicBlockSections.cpp @@ -81,12 +81,12 @@ // Placing the cold clusters in a separate section mitigates against poor // profiles and allows optimizations such as hugepage mapping to be applied at a -// section granularity. Defaults to ".text.split." which is recognized by lld -// via the `-z keep-text-section-prefix` flag. +// section granularity. Defaults to "split" which is recognized by lld via the +// `-z keep-text-section-prefix` flag. cl::opt llvm::BBSectionsColdTextPrefix( "bbsections-cold-text-prefix", cl::desc("The text prefix to use for cold basic block clusters"), - cl::init(".text.split."), cl::Hidden); + cl::init("split"), cl::Hidden); cl::opt BBSectionsDetectSourceDrift( "bbsections-detect-source-drift", diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -953,7 +953,9 @@ // name, or a unique ID for the section. SmallString<128> Name; if (MBB.getSectionID() == MBBSectionID::ColdSectionID) { + Name += ".text."; Name += BBSectionsColdTextPrefix; + Name += "."; Name += MBB.getParent()->getName(); } else if (MBB.getSectionID() == MBBSectionID::ExceptionSectionID) { Name += ".text.eh."; @@ -1693,6 +1695,25 @@ COFF::IMAGE_COMDAT_SELECT_ASSOCIATIVE, UniqueID); } +/// Returns a unique section for the given machine basic block. +MCSection *TargetLoweringObjectFileCOFF::getSectionForMachineBasicBlock( + const Function &F, const MachineBasicBlock &MBB, + const TargetMachine &TM) const { + assert(MBB.isBeginSection() && "Basic block does not start a section!"); + assert(MBB.getSectionID() == MBBSectionID::ColdSectionID); + SmallString<128> Name, GroupName; + Name += ".text$"; + Name += BBSectionsColdTextPrefix; + GroupName += MBB.getParent()->getName(); + GroupName += BBSectionsColdTextPrefix; + return getContext().getCOFFSection( + Name, + COFF::IMAGE_SCN_CNT_CODE | COFF::IMAGE_SCN_MEM_EXECUTE | + COFF::IMAGE_SCN_MEM_READ | COFF::IMAGE_SCN_LNK_COMDAT, + SectionKind::getText(), GroupName, + COFF::IMAGE_COMDAT_SELECT_NODUPLICATES); +} + void TargetLoweringObjectFileCOFF::emitModuleMetadata(MCStreamer &Streamer, Module &M) const { emitLinkerDirectives(Streamer, M); diff --git a/llvm/test/CodeGen/X86/basic-block-sections-cold.ll b/llvm/test/CodeGen/X86/basic-block-sections-cold.ll --- a/llvm/test/CodeGen/X86/basic-block-sections-cold.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-cold.ll @@ -3,7 +3,7 @@ ; RUN: echo '!_Z3bazb' > %t ; RUN: echo '!!0' >> %t ; RUN: llc < %s -mtriple=x86_64 -function-sections -basic-block-sections=%t -unique-basic-block-section-names | FileCheck %s -check-prefix=LINUX-SECTIONS -; RUN: llc < %s -mtriple=x86_64 -function-sections -basic-block-sections=%t -unique-basic-block-section-names -bbsections-cold-text-prefix=".text.unlikely." | FileCheck %s -check-prefix=LINUX-SPLIT +; RUN: llc < %s -mtriple=x86_64 -function-sections -basic-block-sections=%t -unique-basic-block-section-names -bbsections-cold-text-prefix="unlikely" | FileCheck %s -check-prefix=LINUX-SPLIT define void @_Z3bazb(i1 zeroext %0) nounwind { br i1 %0, label %2, label %4 diff --git a/llvm/test/CodeGen/X86/machine-function-splitter.ll b/llvm/test/CodeGen/X86/machine-function-splitter.ll --- a/llvm/test/CodeGen/X86/machine-function-splitter.ll +++ b/llvm/test/CodeGen/X86/machine-function-splitter.ll @@ -1,11 +1,15 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -split-machine-functions | FileCheck %s -check-prefix=MFS-DEFAULTS +; RUN: llc < %s -mtriple=x86_64-windows-msvc -split-machine-functions -function-sections | FileCheck %s -check-prefix=MFS-DEFAULTS-MSVC ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -split-machine-functions -mfs-psi-cutoff=0 -mfs-count-threshold=2000 | FileCheck %s --dump-input=always -check-prefix=MFS-OPTS1 +; RUN: llc < %s -mtriple=x86_64-windows-msvc -split-machine-functions -function-sections -mfs-psi-cutoff=0 -mfs-count-threshold=2000 | FileCheck %s --dump-input=always -check-prefix=MFS-OPTS1-MSVC ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -split-machine-functions -mfs-psi-cutoff=950000 | FileCheck %s -check-prefix=MFS-OPTS2 +; RUN: llc < %s -mtriple=x86_64-windows-msvc -split-machine-functions -function-sections -mfs-psi-cutoff=950000 | FileCheck %s -check-prefix=MFS-OPTS2-MSVC define void @foo1(i1 zeroext %0) nounwind !prof !14 !section_prefix !15 { -;; Check that cold block is moved to .text.split. +;; Check that cold block is moved to .text.split for ELF or .text$split for COFF ; MFS-DEFAULTS-LABEL: foo1 ; MFS-DEFAULTS: .section .text.split.foo1 +; MFS-DEFAULTS-MSVC: .section .text$split,"xr",one_only,foo1split ; MFS-DEFAULTS-NEXT: foo1.cold: ; MFS-DEFAULTS-NOT: callq bar ; MFS-DEFAULTS-NEXT: callq baz @@ -66,6 +70,7 @@ ;; Check that count threshold works. ; MFS-OPTS1-LABEL: foo4 ; MFS-OPTS1: .section .text.split.foo4 +; MFS-OPTS1-MSVC: .section .text$split,"xr",one_only,foo4split ; MFS-OPTS1-NEXT: foo4.cold: ; MFS-OPTS1-NOT: callq bar ; MFS-OPTS1-NOT: callq baz @@ -100,6 +105,7 @@ ;; Check that profile summary info cutoff works. ; MFS-OPTS2-LABEL: foo5 ; MFS-OPTS2: .section .text.split.foo5 +; MFS-OPTS2-MSVC: .section .text$split,"xr",one_only,foo5split ; MFS-OPTS2-NEXT: foo5.cold: ; MFS-OPTS2-NOT: callq bar ; MFS-OPTS2-NOT: callq baz @@ -153,6 +159,7 @@ ;; Check that a single cold ehpad is split out. ; MFS-DEFAULTS-LABEL: foo7 ; MFS-DEFAULTS: .section .text.split.foo7,"ax",@progbits +; MFS-DEFAULTS-MSVC: .section .text$split,"xr",one_only,foo7split ; MFS-DEFAULTS-NEXT: foo7.cold: ; MFS-DEFAULTS: callq baz ; MFS-DEFAULTS: callq _Unwind_Resume@PLT diff --git a/llvm/test/CodeGen/X86/wineh-machine-function-splitter.ll b/llvm/test/CodeGen/X86/wineh-machine-function-splitter.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/wineh-machine-function-splitter.ll @@ -0,0 +1,758 @@ +; RUN: llc < %s -mtriple=x86_64-windows-msvc -split-machine-functions -function-sections | llvm-mc -triple x86_64-windows-msvc -filetype=obj - | llvm-readobj -S --sd --sr -u - | FileCheck %s + +define void @foo1(i1 zeroext %0) !prof !14 !section_prefix !15 { + br i1 %0, label %2, label %4, !prof !17 + +2: ; preds = %1 + %3 = call i32 @bar() + br label %6 + +4: ; preds = %1 + %5 = call i32 @baz() + br label %6 + +6: ; preds = %4, %2 + %7 = tail call i32 @qux() + ret void +} + +define void @foo2(i1 zeroext %0) !prof !23 !section_prefix !16 { + br i1 %0, label %2, label %4, !prof !17 + +2: ; preds = %1 + %3 = call i32 @bar() + br label %6 + +4: ; preds = %1 + %5 = call i32 @baz() + br label %6 + +6: ; preds = %4, %2 + %7 = tail call i32 @qux() + ret void +} + +define void @foo3(i1 zeroext %0) !section_prefix !15 { + br i1 %0, label %2, label %4 + +2: ; preds = %1 + %3 = call i32 @bar() + br label %6 + +4: ; preds = %1 + %5 = call i32 @baz() + br label %6 + +6: ; preds = %4, %2 + %7 = tail call i32 @qux() + ret void +} + +define void @foo4(i1 zeroext %0, i1 zeroext %1) !prof !20 { + br i1 %0, label %3, label %7, !prof !18 + +3: + %4 = call i32 @bar() + br label %7 + +5: + %6 = call i32 @baz() + br label %7 + +7: + br i1 %1, label %8, label %10, !prof !19 + +8: + %9 = call i32 @bam() + br label %12 + +10: + %11 = call i32 @baz() + br label %12 + +12: + %13 = tail call i32 @qux() + ret void +} + +define void @foo5(i1 zeroext %0, i1 zeroext %1) !prof !20 { + br i1 %0, label %3, label %7, !prof !21 + +3: + %4 = call i32 @bar() + br label %7 + +5: + %6 = call i32 @baz() + br label %7 + +7: + br i1 %1, label %8, label %10, !prof !22 + +8: + %9 = call i32 @bam() + br label %12 + +10: + %11 = call i32 @baz() + br label %12 + +12: + %13 = call i32 @qux() + ret void +} + +define void @foo6(i1 zeroext %0) section "nosplit" !prof !14 { + br i1 %0, label %2, label %4, !prof !17 + +2: ; preds = %1 + %3 = call i32 @bar() + br label %6 + +4: ; preds = %1 + %5 = call i32 @baz() + br label %6 + +6: ; preds = %4, %2 + %7 = tail call i32 @qux() + ret void +} + +define i32 @foo7(i1 zeroext %0) personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) !prof !14 { +entry: + invoke void @_Z1fv() + to label %try.cont unwind label %lpad + +lpad: + %1 = landingpad { i8*, i32 } + cleanup + catch i8* bitcast (i8** @_ZTIi to i8*) + resume { i8*, i32 } %1 + +try.cont: + br i1 %0, label %2, label %4, !prof !17 + +2: ; preds = try.cont + %3 = call i32 @bar() + br label %6 + +4: ; preds = %1 + %5 = call i32 @baz() + br label %6 + +6: ; preds = %4, %2 + %7 = tail call i32 @qux() + ret i32 %7 +} + +define i32 @foo8(i1 zeroext %0) personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) !prof !14 { +entry: + invoke void @_Z1fv() + to label %try.cont unwind label %lpad1 + +lpad1: + %1 = landingpad { i8*, i32 } + cleanup + catch i8* bitcast (i8** @_ZTIi to i8*) + resume { i8*, i32 } %1 + +try.cont: + br i1 %0, label %hot, label %cold, !prof !17 + +hot: + %2 = call i32 @bar() + invoke void @_Z1fv() + to label %exit unwind label %lpad2, !prof !21 + +lpad2: + %3 = landingpad { i8*, i32 } + cleanup + catch i8* bitcast (i8** @_ZTIi to i8*) + resume { i8*, i32 } %3 + +cold: + %4 = call i32 @baz() + br label %exit + +exit: + %5 = tail call i32 @qux() + ret i32 %5 +} + +; CHECK: Sections [ +; CHECK: Section { +; CHECK: Name: .text$hot +; CHECK: RawDataSize: 27 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_16BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_CODE +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: 0x8 IMAGE_REL_AMD64_REL32 foo1.cold (71) +; CHECK-NEXT: 0xD IMAGE_REL_AMD64_REL32 bar (72) +; CHECK-NEXT: 0x17 IMAGE_REL_AMD64_REL32 qux (73) +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 4883EC28 84C90F84 00000000 E8000000 +; CHECK-NEXT: 0010: 00904883 C428E900 000000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .text$split +; CHECK: RawDataSize: 10 +; CHECK: RelocationCount: 2 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_1BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_CODE +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: 0x1 IMAGE_REL_AMD64_REL32 baz (74) +; CHECK-NEXT: 0x6 IMAGE_REL_AMD64_REL32 .text$hot (6) +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: E8000000 00E91100 0000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .xdata +; CHECK: RawDataSize: 8 +; CHECK: RelocationCount: 0 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01040100 04420000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .text$hot +; CHECK: RawDataSize: 36 +; CHECK: RelocationCount: 4 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_16BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_CODE +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: 0x8 IMAGE_REL_AMD64_REL32 _Z1fv (77) +; CHECK-NEXT: 0x10 IMAGE_REL_AMD64_REL32 foo7.cold (78) +; CHECK-NEXT: 0x15 IMAGE_REL_AMD64_REL32 bar (72) +; CHECK-NEXT: 0x20 IMAGE_REL_AMD64_REL32 qux (73) +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 534883EC 2089CBE8 00000000 84DB0F84 +; CHECK-NEXT: 0010: 00000000 E8000000 00904883 C4205BE9 +; CHECK-NEXT: 0020: 00000000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .text$split +; CHECK: RawDataSize: 11 +; CHECK: RelocationCount: 2 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_1BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_CODE +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: 0x1 IMAGE_REL_AMD64_REL32 baz (74) +; CHECK-NEXT: 0x6 IMAGE_REL_AMD64_REL32 .text$hot (38) +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: E8000000 00E91900 0000CC +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .text$hot +; CHECK: RawDataSize: 41 +; CHECK: RelocationCount: 5 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_16BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_CODE +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: 0x8 IMAGE_REL_AMD64_REL32 _Z1fv (77) +; CHECK-NEXT: 0x10 IMAGE_REL_AMD64_REL32 foo8.cold (79) +; CHECK-NEXT: 0x15 IMAGE_REL_AMD64_REL32 bar (72) +; CHECK-NEXT: 0x1A IMAGE_REL_AMD64_REL32 _Z1fv (77) +; CHECK-NEXT: 0x25 IMAGE_REL_AMD64_REL32 qux (73) +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 534883EC 2089CBE8 00000000 84DB0F84 +; CHECK-NEXT: 0010: 00000000 E8000000 00E80000 00009048 +; CHECK-NEXT: 0020: 83C4205B E9000000 00 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .text$split +; CHECK: RawDataSize: 10 +; CHECK: RelocationCount: 2 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_1BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_CODE +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK-NEXT: Relocations [ +; CHECK-NEXT: 0x1 IMAGE_REL_AMD64_REL32 baz (74) +; CHECK-NEXT: 0x6 IMAGE_REL_AMD64_REL32 .text$hot (46) +; CHECK-NEXT: ] +; CHECK-NEXT: SectionData ( +; CHECK-NEXT: 0000: E8000000 00E91E00 0000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .pdata +; CHECK: RawDataSize: 12 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES (0x300000) +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) +; CHECK-NEXT: IMAGE_SCN_MEM_READ (0x40000000) +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: [[BeginDispfoo6:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo6 +; CHECK-NEXT: [[EndDispfoo6:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo6 +; CHECK-NEXT: [[UnwindDispfoo6:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 00000000 1E000000 00000000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .xdata +; CHECK: RawDataSize: 8 +; CHECK: RelocationCount: 0 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01040100 04420000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .xdata +; CHECK: RawDataSize: 8 +; CHECK: RelocationCount: 0 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01040100 04420000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .xdata +; CHECK: RawDataSize: 8 +; CHECK: RelocationCount: 0 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01040100 04420000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .xdata +; CHECK: RawDataSize: 8 +; CHECK: RelocationCount: 0 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK: ] +; CHECK: Relocations [ +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01050200 05320130 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .xdata +; CHECK: RawDataSize: 8 +; CHECK: RelocationCount: 0 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01050200 05320130 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .xdata +; CHECK: RawDataSize: 8 +; CHECK: RelocationCount: 0 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01050200 05320130 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .xdata +; CHECK: RawDataSize: 8 +; CHECK: RelocationCount: 0 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01050200 05320130 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .pdata +; CHECK: RawDataSize: 12 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: [[BeginDispfoo1:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo1 +; CHECK-NEXT: [[EndDispfoo1:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo1 +; CHECK-NEXT: [[UnwindDispfoo1:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 00000000 1B000000 00000000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .pdata +; CHECK: RawDataSize: 12 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: [[BeginDispfoo2:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo2 +; CHECK-NEXT: [[EndDispfoo2:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo2 +; CHECK-NEXT: [[UnwindDispfoo2:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata +; CHECK: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 00000000 1E000000 00000000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .pdata +; CHECK: RawDataSize: 12 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics [ +; CHECK: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: [[BeginDispfoo3:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo3 +; CHECK-NEXT: [[EndDispfoo3:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo3 +; CHECK-NEXT: [[UnwindDispfoo3:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 00000000 1E000000 00000000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .pdata +; CHECK: RawDataSize: 12 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: [[BeginDispfoo4:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo4 +; CHECK-NEXT: [[EndDispfoo4:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo4 +; CHECK-NEXT: [[UnwindDispfoo4:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 00000000 2B000000 00000000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .pdata +; CHECK: RawDataSize: 12 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: [[BeginDispfoo5:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo5 +; CHECK-NEXT: [[EndDispfoo5:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo5 +; CHECK-NEXT: [[UnwindDispfoo5:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 00000000 2C000000 00000000 +; CHECK-NEXT: ) +; CHECK-NEXT: } +; CHECK: Section { +; CHECK: Name: .pdata +; CHECK: RawDataSize: 12 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: [[BeginDispfoo7:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo7 +; CHECK-NEXT: [[EndDispfoo7:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo7 +; CHECK-NEXT: [[UnwindDispfoo7:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 00000000 24000000 00000000 +; CHECK: Section { +; CHECK: Name: .pdata +; CHECK: RawDataSize: 12 +; CHECK: RelocationCount: 3 +; CHECK: Characteristics [ +; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT +; CHECK-NEXT: IMAGE_SCN_MEM_READ +; CHECK-NEXT: ] +; CHECK: Relocations [ +; CHECK-NEXT: [[BeginDispfoo8:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo8 +; CHECK-NEXT: [[EndDispfoo8:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB foo8 +; CHECK-NEXT: [[UnwindDispfoo8:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata +; CHECK-NEXT: ] +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 00000000 29000000 00000000 +; CHECK: UnwindInformation [ +; CHECK-NEXT: RuntimeFunction { +; CHECK-NEXT: StartAddress: foo6 {{(\+0x[A-F0-9]+ )?}}([[BeginDispfoo6]]) +; CHECK-NEXT: EndAddress: foo6 {{(\+0x[A-F0-9]+ )?}}([[EndDispfoo6]]) +; CHECK-NEXT: UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDispfoo6]]) +; CHECK-NEXT: UnwindInfo { +; CHECK-NEXT: Version: 1 +; CHECK-NEXT: Flags [ (0x0) +; CHECK-NEXT: ] +; CHECK-NEXT: PrologSize: 4 +; CHECK-NEXT: FrameRegister: - +; CHECK-NEXT: FrameOffset: - +; CHECK-NEXT: UnwindCodeCount: 1 +; CHECK-NEXT: UnwindCodes [ +; CHECK-NEXT: 0x04: ALLOC_SMALL size=40 +; CHECK-NEXT: ] +; CHECK-NEXT: } +; CHECK-NEXT: } +; CHECK-NEXT: RuntimeFunction { +; CHECK-NEXT: StartAddress: foo1 {{(\+0x[A-F0-9]+ )?}}([[BeginDispfoo1]]) +; CHECK-NEXT: EndAddress: foo1 +0x1B {{(\+0x[A-F0-9]+ )?}}([[EndDispfoo1]]) +; CHECK-NEXT: UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDispfoo1]]) +; CHECK-NEXT: UnwindInfo { +; CHECK-NEXT: Version: 1 +; CHECK-NEXT: Flags [ (0x0) +; CHECK-NEXT: ] +; CHECK-NEXT: PrologSize: 4 +; CHECK-NEXT: FrameRegister: - +; CHECK-NEXT: FrameOffset: - +; CHECK-NEXT: UnwindCodeCount: 1 +; CHECK-NEXT: UnwindCodes [ +; CHECK-NEXT: 0x04: ALLOC_SMALL size=40 +; CHECK-NEXT: ] +; CHECK-NEXT: } +; CHECK-NEXT: } +; CHECK-NEXT: RuntimeFunction { +; CHECK-NEXT: StartAddress: foo2 {{(\+0x[A-F0-9]+ )?}}([[BeginDispfoo2]]) +; CHECK-NEXT: EndAddress: foo2 +0x1E {{(\+0x[A-F0-9]+ )?}}([[EndDispfoo2]]) +; CHECK-NEXT: UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDispfoo2]]) +; CHECK-NEXT: UnwindInfo { +; CHECK-NEXT: Version: 1 +; CHECK-NEXT: Flags [ (0x0) +; CHECK-NEXT: ] +; CHECK-NEXT: PrologSize: 4 +; CHECK-NEXT: FrameRegister: - +; CHECK-NEXT: FrameOffset: - +; CHECK-NEXT: UnwindCodeCount: 1 +; CHECK-NEXT: UnwindCodes [ +; CHECK-NEXT: 0x04: ALLOC_SMALL size=40 +; CHECK-NEXT: ] +; CHECK-NEXT: } +; CHECK-NEXT: } +; CHECK-NEXT: RuntimeFunction { +; CHECK-NEXT: StartAddress: foo3 {{(\+0x[A-F0-9]+ )?}}([[BeginDispfoo3]]) +; CHECK-NEXT: EndAddress: foo3 +0x1E {{(\+0x[A-F0-9]+ )?}}([[EndDispfoo3]]) +; CHECK-NEXT: UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDispfoo3]]) +; CHECK-NEXT: UnwindInfo { +; CHECK-NEXT: Version: 1 +; CHECK-NEXT: Flags [ (0x0) +; CHECK-NEXT: ] +; CHECK-NEXT: PrologSize: 4 +; CHECK-NEXT: FrameRegister: - +; CHECK-NEXT: FrameOffset: - +; CHECK-NEXT: UnwindCodeCount: 1 +; CHECK-NEXT: UnwindCodes [ +; CHECK-NEXT: 0x04: ALLOC_SMALL size=40 +; CHECK-NEXT: ] +; CHECK-NEXT: } +; CHECK-NEXT: } +; CHECK-NEXT: RuntimeFunction { +; CHECK-NEXT: StartAddress: foo4 {{(\+0x[A-F0-9]+ )?}}([[BeginDispfoo4]]) +; CHECK-NEXT: EndAddress: foo4 +0x2B {{(\+0x[A-F0-9]+ )?}}([[EndDispfoo4]]) +; CHECK-NEXT: UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDispfoo4]]) +; CHECK-NEXT: UnwindInfo { +; CHECK-NEXT: Version: 1 +; CHECK-NEXT: Flags [ (0x0) +; CHECK-NEXT: ] +; CHECK-NEXT: PrologSize: 5 +; CHECK-NEXT: FrameRegister: - +; CHECK-NEXT: FrameOffset: - +; CHECK-NEXT: UnwindCodeCount: 2 +; CHECK-NEXT: UnwindCodes [ +; CHECK-NEXT: 0x05: ALLOC_SMALL size=32 +; CHECK-NEXT: 0x01: PUSH_NONVOL reg=RBX +; CHECK-NEXT: ] +; CHECK-NEXT: } +; CHECK-NEXT: } +; CHECK-NEXT: RuntimeFunction { +; CHECK-NEXT: StartAddress: foo5 {{(\+0x[A-F0-9]+ )?}}([[BeginDispfoo5]]) +; CHECK-NEXT: EndAddress: foo5 +0x2C {{(\+0x[A-F0-9]+ )?}}([[EndDispfoo5]]) +; CHECK-NEXT: UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDispfoo5]]) +; CHECK-NEXT: UnwindInfo { +; CHECK-NEXT: Version: 1 +; CHECK-NEXT: Flags [ (0x0) +; CHECK-NEXT: ] +; CHECK-NEXT: PrologSize: 5 +; CHECK-NEXT: FrameRegister: - +; CHECK-NEXT: FrameOffset: - +; CHECK-NEXT: UnwindCodeCount: 2 +; CHECK-NEXT: UnwindCodes [ +; CHECK-NEXT: 0x05: ALLOC_SMALL size=32 +; CHECK-NEXT: 0x01: PUSH_NONVOL reg=RBX +; CHECK-NEXT: ] +; CHECK-NEXT: } +; CHECK-NEXT: } +; CHECK-NEXT: RuntimeFunction { +; CHECK-NEXT: StartAddress: foo7 {{(\+0x[A-F0-9]+ )?}}([[BeginDispfoo7]]) +; CHECK-NEXT: EndAddress: foo7 +0x24 {{(\+0x[A-F0-9]+ )?}}([[EndDispfoo7]]) +; CHECK-NEXT: UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDispfoo7]]) +; CHECK-NEXT: UnwindInfo { +; CHECK-NEXT: Version: 1 +; CHECK-NEXT: Flags [ (0x0) +; CHECK-NEXT: ] +; CHECK-NEXT: PrologSize: 5 +; CHECK-NEXT: FrameRegister: - +; CHECK-NEXT: FrameOffset: - +; CHECK-NEXT: UnwindCodeCount: 2 +; CHECK-NEXT: UnwindCodes [ +; CHECK-NEXT: 0x05: ALLOC_SMALL size=32 +; CHECK-NEXT: 0x01: PUSH_NONVOL reg=RBX +; CHECK-NEXT: ] +; CHECK-NEXT: } +; CHECK-NEXT: } +; CHECK-NEXT: RuntimeFunction { +; CHECK-NEXT: StartAddress: foo8 {{(\+0x[A-F0-9]+ )?}}([[BeginDispfoo8]]) +; CHECK-NEXT: EndAddress: foo8 +0x29 {{(\+0x[A-F0-9]+ )?}}([[EndDispfoo8]]) +; CHECK-NEXT: UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDispfoo8]]) +; CHECK-NEXT: UnwindInfo { +; CHECK-NEXT: Version: 1 +; CHECK-NEXT: Flags [ (0x0) +; CHECK-NEXT: ] +; CHECK-NEXT: PrologSize: 5 +; CHECK-NEXT: FrameRegister: - +; CHECK-NEXT: FrameOffset: - +; CHECK-NEXT: UnwindCodeCount: 2 +; CHECK-NEXT: UnwindCodes [ +; CHECK-NEXT: 0x05: ALLOC_SMALL size=32 +; CHECK-NEXT: 0x01: PUSH_NONVOL reg=RBX +; CHECK-NEXT: ] +; CHECK-NEXT: } +; CHECK-NEXT: } +; CHECK-NEXT: ] + +declare i32 @bar() +declare i32 @baz() +declare i32 @bam() +declare i32 @qux() +declare void @_Z1fv() +declare i32 @__C_specific_handler(...) + +@_ZTIi = external constant i8* + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"ProfileSummary", !1} +!1 = !{!2, !3, !4, !5, !6, !7, !8, !9} +!2 = !{!"ProfileFormat", !"InstrProf"} +!3 = !{!"TotalCount", i64 10000} +!4 = !{!"MaxCount", i64 10} +!5 = !{!"MaxInternalCount", i64 1} +!6 = !{!"MaxFunctionCount", i64 1000} +!7 = !{!"NumCounts", i64 3} +!8 = !{!"NumFunctions", i64 5} +!9 = !{!"DetailedSummary", !10} +!10 = !{!11, !12, !13} +!11 = !{i32 10000, i64 100, i32 1} +!12 = !{i32 999900, i64 100, i32 1} +!13 = !{i32 999999, i64 1, i32 2} +!14 = !{!"function_entry_count", i64 7000} +!15 = !{!"function_section_prefix", !"hot"} +!16 = !{!"function_section_prefix", !"unlikely"} +!17 = !{!"branch_weights", i32 7000, i32 0} +!18 = !{!"branch_weights", i32 3000, i32 4000} +!19 = !{!"branch_weights", i32 1000, i32 6000} +!20 = !{!"function_entry_count", i64 10000} +!21 = !{!"branch_weights", i32 6000, i32 4000} +!22 = !{!"branch_weights", i32 80, i32 9920} +!23 = !{!"function_entry_count", i64 7}