diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -16522,6 +16522,27 @@ FlagSet |= PPC::MOF_RPlusSImm16Mult16; }; + auto IsFrameIndexAligned = [&](SDValue N) { + // Set alignment flags based on whether or not the Frame Index is aligned. + bool IsAdd = N.getOpcode() == ISD::ADD; + if (FrameIndexSDNode *FI = + dyn_cast(IsAdd ? N.getOperand(0) : N)) { + const MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + unsigned FrameIndexVal = MFI.getObjectAlign(FI->getIndex()).value(); + if ((FrameIndexVal % 4) != 0) + FlagSet &= ~PPC::MOF_RPlusSImm16Mult4; + if ((FrameIndexVal % 16) != 0) + FlagSet &= ~PPC::MOF_RPlusSImm16Mult16; + + if (!IsAdd) { + if ((FrameIndexVal % 4) == 0) + FlagSet |= PPC::MOF_RPlusSImm16Mult4; + if ((FrameIndexVal % 16) == 0) + FlagSet |= PPC::MOF_RPlusSImm16Mult16; + } + } + }; + auto computeFlagsForAddressComputation = [&](SDValue N) { if (ConstantSDNode *CN = dyn_cast(N)) { // All 32-bit constants can be computed as LIS + Disp. @@ -16529,6 +16550,7 @@ if (ConstImm.isSignedIntN(32)) { // Flag to handle 32-bit constants. FlagSet |= PPC::MOF_AddrIsSImm32; SetAlignFlagsForImm(ConstImm.getZExtValue()); + IsFrameIndexAligned(N); } if (ConstImm.isSignedIntN(34)) // Flag to handle 34-bit constants. FlagSet |= PPC::MOF_RPlusSImm34; @@ -16547,6 +16569,7 @@ if (ConstImm.isSignedIntN(16)) { FlagSet |= PPC::MOF_RPlusSImm16; // Signed 16-bit immediates. SetAlignFlagsForImm(ConstImm.getZExtValue()); + IsFrameIndexAligned(N); } if (ConstImm.isSignedIntN(34)) FlagSet |= PPC::MOF_RPlusSImm34; // Signed 34-bit immediates. @@ -16621,6 +16644,27 @@ FlagSet &= ~PPC::MOF_NoExt; } + // If the node, N, is a frame index, ensure that we only only match aligned + // DForms if the frame index is aligned. As the `PPC::MOF_NotAddNorCst` flag + // can also be mapped to aligned DForms, this check is performed near the end + // in order to remove the `PPC::MOF_NotAddNorCst` flag and prevent generating + // an aligned DForm when the frame index is not aligned. + if (FrameIndexSDNode *FI = dyn_cast(N)) { + PPC::AddrMode Mode = getAddrModeForFlags(FlagSet); + bool IsDSForm = Mode == PPC::AM_DSForm; + bool IsDQForm = Mode == PPC::AM_DQForm; + if ((IsDSForm || IsDQForm) && (FlagSet & PPC::MOF_NotAddNorCst)) { + // If the address mode computed is a [DS|DQ]Form, double check that that + // the frame index is aligned. + IsFrameIndexAligned(N); + // If the frame index is not aligned, unset `PPC::MOF_NotAddNorCst` to + // prevent matching to an aligned DForm (to match by XForm). + if (((IsDSForm) && (!(FlagSet & PPC::MOF_RPlusSImm16Mult4))) || + ((IsDQForm) && (!(FlagSet & PPC::MOF_RPlusSImm16Mult16)))) + FlagSet &= ~PPC::MOF_NotAddNorCst; + } + } + // Prior to P10, constants that fit in 34-bits on should be marked with // `PPC::MOF_NotAddNorCst` to match by D-Form. if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::OR && @@ -16739,8 +16783,12 @@ case PPC::AM_None: break; default: { // By default, X-Form is always available to be selected. - Base = N.getOperand(1); - Disp = N.getOperand(0); + // When a frame index is not aligned, we also match by XForm. + FrameIndexSDNode *FI = dyn_cast(N); + Base = FI ? N : N.getOperand(1); + Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, + N.getValueType()) + : N.getOperand(0); break; } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -315,13 +315,13 @@ let CodeSize = 3 in def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), "#XFLOADf64", - [(set f64:$XT, (load ForceXForm:$src))]>; + [(set f64:$XT, (load XForm:$src))]>; let Predicates = [HasVSX, HasOnlySwappingMemOps] in def LXVD2X : XX1Form_memOp<31, 844, (outs vsrc:$XT), (ins memrr:$src), "lxvd2x $XT, $src", IIC_LdStLFD, - [(set v2f64:$XT, (int_ppc_vsx_lxvd2x ForceXForm:$src))]>; + []>; def LXVDSX : XX1Form_memOp<31, 332, (outs vsrc:$XT), (ins memrr:$src), @@ -346,7 +346,7 @@ let CodeSize = 3 in def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), "#XFSTOREf64", - [(store f64:$XT, ForceXForm:$dst)]>; + [(store f64:$XT, XForm:$dst)]>; let Predicates = [HasVSX, HasOnlySwappingMemOps] in { // The behaviour of this instruction is endianness-specific so we provide no @@ -1125,7 +1125,7 @@ let CodeSize = 3 in def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src), "#XFLOADf32", - [(set f32:$XT, (load ForceXForm:$src))]>; + [(set f32:$XT, (load XForm:$src))]>; // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), "#LIWAX", @@ -1148,7 +1148,7 @@ let CodeSize = 3 in def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst), "#XFSTOREf32", - [(store f32:$XT, ForceXForm:$dst)]>; + [(store f32:$XT, XForm:$dst)]>; // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), "#STIWX", @@ -2414,6 +2414,7 @@ // [HasVSX, IsLittleEndian] // [HasVSX, NoP9Vector] // [HasVSX, NoP9Vector, IsLittleEndian] +// [HasVSX, NoP9Vector, IsBigEndian] // [HasVSX, HasOnlySwappingMemOps] // [HasVSX, HasOnlySwappingMemOps, IsBigEndian] // [HasVSX, HasP8Vector] @@ -3032,14 +3033,19 @@ (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; } // HasVSX, NoP9Vector, IsLittleEndian +let Predicates = [HasVSX, NoP9Vector, IsBigEndian] in { + def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)), + (LXVD2X ForceXForm:$src)>; + def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst), + (STXVD2X $rS, ForceXForm:$dst)>; +} // HasVSX, NoP9Vector, IsBigEndian + // Any VSX subtarget that only has loads and stores that load in big endian // order regardless of endianness. This is really pre-Power9 subtargets. let Predicates = [HasVSX, HasOnlySwappingMemOps] in { def : Pat<(v2f64 (PPClxvd2x ForceXForm:$src)), (LXVD2X ForceXForm:$src)>; // Stores. - def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst), - (STXVD2X $rS, ForceXForm:$dst)>; def : Pat<(PPCstxvd2x v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>; } // HasVSX, HasOnlySwappingMemOps @@ -3061,8 +3067,8 @@ let Predicates = [HasVSX, HasP8Vector] in { def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B), (XXLEQV $A, $B)>; -def : Pat<(f64 (extloadf32 ForceXForm:$src)), - (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$src), VSFRC)>; +def : Pat<(f64 (extloadf32 XForm:$src)), + (COPY_TO_REGCLASS (XFLOADf32 XForm:$src), VSFRC)>; def : Pat<(f32 (fpround (f64 (extloadf32 ForceXForm:$src)))), (f32 (XFLOADf32 ForceXForm:$src))>; def : Pat<(f64 (any_fpextend f32:$src)), @@ -3686,48 +3692,34 @@ (v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; // D-Form Load/Store -def : Pat<(v4i32 (quadwOffsetLoad DQForm:$src)), (LXV memrix16:$src)>; -def : Pat<(v4f32 (quadwOffsetLoad DQForm:$src)), (LXV memrix16:$src)>; -def : Pat<(v2i64 (quadwOffsetLoad DQForm:$src)), (LXV memrix16:$src)>; -def : Pat<(v2f64 (quadwOffsetLoad DQForm:$src)), (LXV memrix16:$src)>; -def : Pat<(f128 (quadwOffsetLoad DQForm:$src)), +foreach Ty = [v4i32, v4f32, v2i64, v2f64] in { + def : Pat<(Ty (load DQForm:$src)), (LXV memrix16:$src)>; + def : Pat<(Ty (load XForm:$src)), (LXVX XForm:$src)>; + def : Pat<(store Ty:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; + def : Pat<(store Ty:$rS, XForm:$dst), (STXVX $rS, XForm:$dst)>; +} + +def : Pat<(f128 (load DQForm:$src)), (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>; +def : Pat<(f128 (load XForm:$src)), + (COPY_TO_REGCLASS (LXVX XForm:$src), VRRC)>; def : Pat<(v4i32 (int_ppc_vsx_lxvw4x DQForm:$src)), (LXV memrix16:$src)>; def : Pat<(v2f64 (int_ppc_vsx_lxvd2x DQForm:$src)), (LXV memrix16:$src)>; +def : Pat<(v4i32 (int_ppc_vsx_lxvw4x XForm:$src)), (LXVX XForm:$src)>; +def : Pat<(v2f64 (int_ppc_vsx_lxvd2x XForm:$src)), (LXVX XForm:$src)>; -def : Pat<(quadwOffsetStore v4f32:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; -def : Pat<(quadwOffsetStore v4i32:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; -def : Pat<(quadwOffsetStore v2f64:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; -def : Pat<(quadwOffsetStore f128:$rS, DQForm:$dst), +def : Pat<(store f128:$rS, DQForm:$dst), (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>; -def : Pat<(quadwOffsetStore v2i64:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; +def : Pat<(store f128:$rS, XForm:$dst), + (STXVX (COPY_TO_REGCLASS $rS, VSRC), XForm:$dst)>; def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, DQForm:$dst), (STXV $rS, memrix16:$dst)>; - -def : Pat<(v2f64 (nonQuadwOffsetLoad ForceXForm:$src)), (LXVX ForceXForm:$src)>; -def : Pat<(v2i64 (nonQuadwOffsetLoad ForceXForm:$src)), (LXVX ForceXForm:$src)>; -def : Pat<(v4f32 (nonQuadwOffsetLoad ForceXForm:$src)), (LXVX ForceXForm:$src)>; -def : Pat<(v4i32 (nonQuadwOffsetLoad ForceXForm:$src)), (LXVX ForceXForm:$src)>; -def : Pat<(v4i32 (int_ppc_vsx_lxvw4x ForceXForm:$src)), (LXVX ForceXForm:$src)>; -def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)), (LXVX ForceXForm:$src)>; -def : Pat<(f128 (nonQuadwOffsetLoad ForceXForm:$src)), - (COPY_TO_REGCLASS (LXVX ForceXForm:$src), VRRC)>; -def : Pat<(nonQuadwOffsetStore f128:$rS, ForceXForm:$dst), - (STXVX (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>; -def : Pat<(nonQuadwOffsetStore v2f64:$rS, ForceXForm:$dst), - (STXVX $rS, ForceXForm:$dst)>; -def : Pat<(nonQuadwOffsetStore v2i64:$rS, ForceXForm:$dst), - (STXVX $rS, ForceXForm:$dst)>; -def : Pat<(nonQuadwOffsetStore v4f32:$rS, ForceXForm:$dst), - (STXVX $rS, ForceXForm:$dst)>; -def : Pat<(nonQuadwOffsetStore v4i32:$rS, ForceXForm:$dst), - (STXVX $rS, ForceXForm:$dst)>; -def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst), - (STXVX $rS, ForceXForm:$dst)>; -def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst), - (STXVX $rS, ForceXForm:$dst)>; +def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, XForm:$dst), + (STXVX $rS, XForm:$dst)>; +def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst), + (STXVX $rS, XForm:$dst)>; // Build vectors from i8 loads defm : ScalToVecWPermute %2, <4 x i32>* %0, align 16 ret void ; CHECK-LABEL: test2 -; CHECK: addi 3, 3, 8 -; CHECK: addi [[REG:[0-9]+]], 4, 4 -; CHECK: lxvx [[LD:[0-9]+]], 0, 3 -; CHECK: stxvx [[LD]], 0, [[REG]] +; CHECK: li [[REG:[0-9]+]], 8 +; CHECK: lxvx [[LD:[0-9]+]], 3, [[REG]] +; CHECK: li [[REG2:[0-9]+]], 4 +; CHECK: stxvx [[LD]], 4, [[REG2]] } diff --git a/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll b/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll --- a/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll +++ b/llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll @@ -29,7 +29,7 @@ ; CHECK-P9: addis r4, r2, .LC0@toc@ha ; CHECK-P9: lxvwsx vs0, 0, r3 ; CHECK-P9: ld r4, .LC0@toc@l(r4) -; CHECK-P9: stxvx vs0, 0, r4 +; CHECK-P9: stxv vs0, 0(r4) ; CHECK-P9: lis r4, 1024 ; CHECK-P9: lfiwax f0, 0, r3 ; CHECK-P9: addis r3, r2, .LC1@toc@ha diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll --- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll @@ -858,14 +858,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsi: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsi: @@ -927,7 +927,7 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr ; @@ -1022,11 +1022,11 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: sldi r4, r4, 2 ; P9BE-NEXT: add r3, r3, r4 -; P9BE-NEXT: addi r3, r3, -12 -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: li r4, -12 +; P9BE-NEXT: lxvx v2, r3, r4 ; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr ; @@ -1034,11 +1034,11 @@ ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: sldi r4, r4, 2 ; P9LE-NEXT: add r3, r3, r4 -; P9LE-NEXT: addi r3, r3, -12 -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: li r4, -12 +; P9LE-NEXT: lxvx v2, r3, r4 ; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; P9LE-NEXT: lxvx v3, 0, r3 +; P9LE-NEXT: lxv v3, 0(r3) ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: blr ; @@ -1384,14 +1384,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoi: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoi: @@ -1449,7 +1449,7 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: xvcvspsxws v2, v2 ; P9BE-NEXT: blr @@ -1459,7 +1459,7 @@ ; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l -; P9LE-NEXT: lxvx v3, 0, r3 +; P9LE-NEXT: lxv v3, 0(r3) ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: xvcvspsxws v2, v2 ; P9LE-NEXT: blr @@ -1836,14 +1836,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoi: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoi: @@ -1952,23 +1952,23 @@ ; ; P8BE-LABEL: fromDiffMemConsDConvdtoi: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: lfdx f3, 0, r3 -; P8BE-NEXT: lfd f0, 24(r3) -; P8BE-NEXT: lfd f1, 8(r3) -; P8BE-NEXT: lfd f2, 16(r3) +; P8BE-NEXT: lfd f0, 16(r3) +; P8BE-NEXT: lfd f1, 0(r3) +; P8BE-NEXT: lfd f2, 24(r3) +; P8BE-NEXT: lfd f3, 8(r3) ; P8BE-NEXT: xxmrghd vs0, vs0, vs1 ; P8BE-NEXT: xxmrghd vs1, vs2, vs3 ; P8BE-NEXT: xvcvdpsxws v2, vs0 ; P8BE-NEXT: xvcvdpsxws v3, vs1 -; P8BE-NEXT: vmrgew v2, v2, v3 +; P8BE-NEXT: vmrgew v2, v3, v2 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffMemConsDConvdtoi: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: lfdx f3, 0, r3 ; P8LE-NEXT: lfd f0, 24(r3) ; P8LE-NEXT: lfd f1, 8(r3) ; P8LE-NEXT: lfd f2, 16(r3) +; P8LE-NEXT: lfd f3, 0(r3) ; P8LE-NEXT: xxmrghd vs0, vs1, vs0 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2 ; P8LE-NEXT: xvcvdpsxws v2, vs0 @@ -2376,14 +2376,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsui: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsui: @@ -2445,7 +2445,7 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr ; @@ -2540,11 +2540,11 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: sldi r4, r4, 2 ; P9BE-NEXT: add r3, r3, r4 -; P9BE-NEXT: addi r3, r3, -12 -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: li r4, -12 +; P9BE-NEXT: lxvx v2, r3, r4 ; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: blr ; @@ -2552,11 +2552,11 @@ ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: sldi r4, r4, 2 ; P9LE-NEXT: add r3, r3, r4 -; P9LE-NEXT: addi r3, r3, -12 -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: li r4, -12 +; P9LE-NEXT: lxvx v2, r3, r4 ; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l -; P9LE-NEXT: lxvx v3, 0, r3 +; P9LE-NEXT: lxv v3, 0(r3) ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: blr ; @@ -2902,14 +2902,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoui: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoui: @@ -2967,7 +2967,7 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l -; P9BE-NEXT: lxvx v3, 0, r3 +; P9BE-NEXT: lxv v3, 0(r3) ; P9BE-NEXT: vperm v2, v2, v2, v3 ; P9BE-NEXT: xvcvspuxws v2, v2 ; P9BE-NEXT: blr @@ -2977,7 +2977,7 @@ ; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l -; P9LE-NEXT: lxvx v3, 0, r3 +; P9LE-NEXT: lxv v3, 0(r3) ; P9LE-NEXT: vperm v2, v2, v2, v3 ; P9LE-NEXT: xvcvspuxws v2, v2 ; P9LE-NEXT: blr @@ -3355,14 +3355,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoui: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoui: @@ -3471,23 +3471,23 @@ ; ; P8BE-LABEL: fromDiffMemConsDConvdtoui: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: lfdx f3, 0, r3 -; P8BE-NEXT: lfd f0, 24(r3) -; P8BE-NEXT: lfd f1, 8(r3) -; P8BE-NEXT: lfd f2, 16(r3) +; P8BE-NEXT: lfd f0, 16(r3) +; P8BE-NEXT: lfd f1, 0(r3) +; P8BE-NEXT: lfd f2, 24(r3) +; P8BE-NEXT: lfd f3, 8(r3) ; P8BE-NEXT: xxmrghd vs0, vs0, vs1 ; P8BE-NEXT: xxmrghd vs1, vs2, vs3 ; P8BE-NEXT: xvcvdpuxws v2, vs0 ; P8BE-NEXT: xvcvdpuxws v3, vs1 -; P8BE-NEXT: vmrgew v2, v2, v3 +; P8BE-NEXT: vmrgew v2, v3, v2 ; P8BE-NEXT: blr ; ; P8LE-LABEL: fromDiffMemConsDConvdtoui: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: lfdx f3, 0, r3 ; P8LE-NEXT: lfd f0, 24(r3) ; P8LE-NEXT: lfd f1, 8(r3) ; P8LE-NEXT: lfd f2, 16(r3) +; P8LE-NEXT: lfd f3, 0(r3) ; P8LE-NEXT: xxmrghd vs0, vs1, vs0 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2 ; P8LE-NEXT: xvcvdpuxws v2, vs0 @@ -3775,14 +3775,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst1ll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst1ll: @@ -3808,14 +3808,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst16kll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst16kll: @@ -3841,14 +3841,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst32kll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst32kll: @@ -3904,14 +3904,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsll: @@ -4238,14 +4238,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvftoll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvftoll: @@ -4311,14 +4311,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoll: @@ -4358,7 +4358,7 @@ ; ; P8BE-LABEL: fromDiffMemConsAConvftoll: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: lfsx f0, 0, r3 +; P8BE-NEXT: lfs f0, 0(r3) ; P8BE-NEXT: lfs f1, 4(r3) ; P8BE-NEXT: xxmrghd vs0, vs0, vs1 ; P8BE-NEXT: xvcvdpsxds v2, vs0 @@ -4366,7 +4366,7 @@ ; ; P8LE-LABEL: fromDiffMemConsAConvftoll: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: lfsx f0, 0, r3 +; P8LE-NEXT: lfs f0, 0(r3) ; P8LE-NEXT: lfs f1, 4(r3) ; P8LE-NEXT: xxmrghd vs0, vs1, vs0 ; P8LE-NEXT: xvcvdpsxds v2, vs0 @@ -4600,14 +4600,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvdtoll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvdtoll: @@ -4673,14 +4673,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoll: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoll: @@ -4963,14 +4963,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst1ull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst1ull: @@ -4996,14 +4996,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst16kull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst16kull: @@ -5029,14 +5029,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltConst32kull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltConst32kull: @@ -5092,14 +5092,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsull: @@ -5426,14 +5426,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvftoull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvftoull: @@ -5499,14 +5499,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvftoull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvftoull: @@ -5546,7 +5546,7 @@ ; ; P8BE-LABEL: fromDiffMemConsAConvftoull: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: lfsx f0, 0, r3 +; P8BE-NEXT: lfs f0, 0(r3) ; P8BE-NEXT: lfs f1, 4(r3) ; P8BE-NEXT: xxmrghd vs0, vs0, vs1 ; P8BE-NEXT: xvcvdpuxds v2, vs0 @@ -5554,7 +5554,7 @@ ; ; P8LE-LABEL: fromDiffMemConsAConvftoull: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: lfsx f0, 0, r3 +; P8LE-NEXT: lfs f0, 0(r3) ; P8LE-NEXT: lfs f1, 4(r3) ; P8LE-NEXT: xxmrghd vs0, vs1, vs0 ; P8LE-NEXT: xvcvdpuxds v2, vs0 @@ -5788,14 +5788,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: spltCnstConvdtoull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: spltCnstConvdtoull: @@ -5861,14 +5861,14 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r3 +; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffConstsConvdtoull: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l -; P9LE-NEXT: lxvx v2, 0, r3 +; P9LE-NEXT: lxv v2, 0(r3) ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffConstsConvdtoull: diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll @@ -112,7 +112,7 @@ ret fp128 %2 ; CHECK-LABEL: insert_exp_qp ; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3 -; CHECK-DAG: lxvx [[VECREG:v[0-9]+]] +; CHECK-DAG: lxv [[VECREG:v[0-9]+]] ; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]] ; CHECK: blr } @@ -127,7 +127,7 @@ %1 = call i64 @llvm.ppc.scalar.extract.expq(fp128 %0) ret i64 %1 ; CHECK-LABEL: extract_exp -; CHECK: lxvx [[VECIN:v[0-9]+]] +; CHECK: lxv [[VECIN:v[0-9]+]] ; CHECK: xsxexpqp [[VECOUT:v[0-9]+]], [[VECIN]] ; CHECK: mfvsrd r3, [[VECOUT]] ; CHECK: blr diff --git a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll --- a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll +++ b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll @@ -478,7 +478,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vmrgow v2, v3, v2 ; CHECK-P9-NEXT: blr ; @@ -527,7 +527,7 @@ ; CHECK-P9-NEXT: lxsiwzx v2, r3, r4 ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: blr ; diff --git a/llvm/test/CodeGen/PowerPC/constant-pool.ll b/llvm/test/CodeGen/PowerPC/constant-pool.ll --- a/llvm/test/CodeGen/PowerPC/constant-pool.ll +++ b/llvm/test/CodeGen/PowerPC/constant-pool.ll @@ -64,7 +64,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret fp128 0xL00000000000000003C00FFFFC5D02B3A @@ -80,7 +80,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <16 x i8> @@ -96,7 +96,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <8 x i16> @@ -112,7 +112,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <4 x i32> @@ -128,7 +128,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <2 x i64> @@ -144,7 +144,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI8_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI8_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <1 x i128> @@ -160,7 +160,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <4 x float> @@ -176,7 +176,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l -; CHECK-P9-NEXT: lxvx vs34, 0, r3 +; CHECK-P9-NEXT: lxv vs34, 0(r3) ; CHECK-P9-NEXT: blr entry: ret <2 x double> @@ -320,15 +320,15 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-NEXT: lxvx vs35, 0, r3 +; CHECK-P9-NEXT: lxv vs35, 0(r3) ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_1@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_1@toc@l ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 -; CHECK-P9-NEXT: lxvx vs35, 0, r3 +; CHECK-P9-NEXT: lxv vs35, 0(r3) ; CHECK-P9-NEXT: addis r3, r2, .LCPI15_2@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI15_2@toc@l ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 -; CHECK-P9-NEXT: lxvx vs35, 0, r3 +; CHECK-P9-NEXT: lxv vs35, 0(r3) ; CHECK-P9-NEXT: xsaddqp v2, v2, v3 ; CHECK-P9-NEXT: blr entry: @@ -408,10 +408,10 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI17_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI17_0@toc@l -; CHECK-P9-NEXT: lxvx vs0, 0, r3 +; CHECK-P9-NEXT: lxv vs0, 0(r3) ; CHECK-P9-NEXT: addis r3, r2, .LCPI17_1@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI17_1@toc@l -; CHECK-P9-NEXT: lxvx vs2, 0, r3 +; CHECK-P9-NEXT: lxv vs2, 0(r3) ; CHECK-P9-NEXT: xvadddp vs1, vs34, vs0 ; CHECK-P9-NEXT: xvadddp vs1, vs1, vs2 ; CHECK-P9-NEXT: xvadddp vs34, vs1, vs0 diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll b/llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll --- a/llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll +++ b/llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll @@ -23,7 +23,7 @@ ; CHECK-NEXT: bl cos ; CHECK-NEXT: nop ; CHECK-NEXT: addi 30, 30, 8 -; CHECK-NEXT: stfdx 1, 0, 29 +; CHECK-NEXT: stfd 1, 0(29) ; CHECK-NEXT: cmpldi 30, 2040 ; CHECK-NEXT: bne 0, .LBB0_1 ; CHECK-NEXT: # %bb.2: # %exit @@ -62,7 +62,7 @@ ; CHECK-NEXT: # ; CHECK-NEXT: lfdu 0, 8(3) ; CHECK-NEXT: xssqrtdp 0, 0 -; CHECK-NEXT: stfdx 0, 0, 3 +; CHECK-NEXT: stfd 0, 0(3) ; CHECK-NEXT: bdnz .LBB1_1 ; CHECK-NEXT: # %bb.2: # %exit ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/extract-and-store.ll b/llvm/test/CodeGen/PowerPC/extract-and-store.ll --- a/llvm/test/CodeGen/PowerPC/extract-and-store.ll +++ b/llvm/test/CodeGen/PowerPC/extract-and-store.ll @@ -599,7 +599,7 @@ ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1 ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-NEXT: lxvx vs35, 0, r3 +; CHECK-P9-NEXT: lxv vs35, 0(r3) ; CHECK-P9-NEXT: li r3, 16 ; CHECK-P9-NEXT: stfiwx f0, r5, r3 ; CHECK-P9-NEXT: li r3, 20 diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll --- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll @@ -536,7 +536,7 @@ ; CHECK-NEXT: std r6, 56(r1) ; CHECK-NEXT: std r7, 64(r1) ; CHECK-NEXT: std r8, 72(r1) -; CHECK-NEXT: lxvx v2, 0, r4 +; CHECK-NEXT: lxv v2, 0(r4) ; CHECK-NEXT: std r9, 80(r1) ; CHECK-NEXT: std r10, 88(r1) ; CHECK-NEXT: bltlr cr0 @@ -560,7 +560,7 @@ ; CHECK-BE-NEXT: std r6, 72(r1) ; CHECK-BE-NEXT: std r7, 80(r1) ; CHECK-BE-NEXT: std r8, 88(r1) -; CHECK-BE-NEXT: lxvx v2, 0, r4 +; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: std r9, 96(r1) ; CHECK-BE-NEXT: std r10, 104(r1) ; CHECK-BE-NEXT: bltlr cr0 diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll --- a/llvm/test/CodeGen/PowerPC/f128-arith.ll +++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll @@ -152,10 +152,10 @@ define dso_local void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) { ; CHECK-LABEL: testLdNSt: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi r3, r3, 4 -; CHECK-NEXT: addi r4, r4, 8 -; CHECK-NEXT: lxvx vs0, 0, r3 -; CHECK-NEXT: stxvx vs0, 0, r4 +; CHECK-NEXT: li r5, 4 +; CHECK-NEXT: lxvx vs0, r3, r5 +; CHECK-NEXT: li r3, 8 +; CHECK-NEXT: stxvx vs0, r4, r3 ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: testLdNSt: @@ -784,10 +784,10 @@ ; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: addis r3, r2, a@toc@ha ; CHECK-NEXT: addi r3, r3, a@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b@toc@ha ; CHECK-NEXT: addi r3, r3, b@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: bl fmodf128 ; CHECK-NEXT: nop ; CHECK-NEXT: addi r1, r1, 32 diff --git a/llvm/test/CodeGen/PowerPC/f128-compare.ll b/llvm/test/CodeGen/PowerPC/f128-compare.ll --- a/llvm/test/CodeGen/PowerPC/f128-compare.ll +++ b/llvm/test/CodeGen/PowerPC/f128-compare.ll @@ -15,10 +15,10 @@ ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: iselgt r3, r4, r3 @@ -63,10 +63,10 @@ ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: isellt r3, r4, r3 @@ -108,10 +108,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: cror 4*cr5+lt, un, lt @@ -155,10 +155,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: cror 4*cr5+lt, un, gt @@ -205,10 +205,10 @@ ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: iseleq r3, r4, r3 @@ -251,10 +251,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: iselgt r3, 0, r3 @@ -300,10 +300,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: isellt r3, 0, r3 @@ -347,10 +347,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: crnor 4*cr5+lt, lt, un @@ -394,10 +394,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: crnor 4*cr5+lt, gt, un @@ -443,10 +443,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: iseleq r3, 0, r3 @@ -490,10 +490,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: bgtlr cr0 ; CHECK-NEXT: # %bb.1: # %entry @@ -554,10 +554,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: # %bb.1: # %entry @@ -618,10 +618,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: crnor 4*cr5+lt, un, lt ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 @@ -683,10 +683,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: crnor 4*cr5+lt, un, gt ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 @@ -748,10 +748,10 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-NEXT: addi r3, r3, a_qp@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: addis r3, r2, b_qp@toc@ha ; CHECK-NEXT: addi r3, r3, b_qp@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: beqlr cr0 ; CHECK-NEXT: # %bb.1: # %entry diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll --- a/llvm/test/CodeGen/PowerPC/f128-conv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll @@ -1144,7 +1144,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-NEXT: ld r4, .LC6@toc@l(r4) -; CHECK-NEXT: lxvx v2, 0, r4 +; CHECK-NEXT: lxv v2, 0(r4) ; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: stxsd v2, 0(r3) ; CHECK-NEXT: blr @@ -1164,7 +1164,7 @@ ; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: stfdx f1, 0, r30 +; CHECK-P8-NEXT: stfd f1, 0(r30) ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -1184,7 +1184,7 @@ ; CHECK-NEXT: addis r5, r2, .LC7@toc@ha ; CHECK-NEXT: sldi r4, r4, 3 ; CHECK-NEXT: ld r5, .LC7@toc@l(r5) -; CHECK-NEXT: lxvx v2, 0, r5 +; CHECK-NEXT: lxv v2, 0(r5) ; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: stxsdx v2, r3, r4 ; CHECK-NEXT: blr @@ -1251,7 +1251,7 @@ ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: stfdx f1, 0, r30 +; CHECK-P8-NEXT: stfd f1, 0(r30) ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -1303,7 +1303,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-NEXT: ld r4, .LC6@toc@l(r4) -; CHECK-NEXT: lxvx v2, 0, r4 +; CHECK-NEXT: lxv v2, 0(r4) ; CHECK-NEXT: xscvqpdpo v2, v2 ; CHECK-NEXT: xsrsp f0, v2 ; CHECK-NEXT: stfs f0, 0(r3) @@ -1324,7 +1324,7 @@ ; CHECK-P8-NEXT: lvx v2, 0, r4 ; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: stfsx f1, 0, r30 +; CHECK-P8-NEXT: stfs f1, 0(r30) ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -1414,7 +1414,7 @@ ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: stfsx f1, 0, r30 +; CHECK-P8-NEXT: stfs f1, 0(r30) ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -1465,7 +1465,7 @@ ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: xscvdpqp v2, v2 -; CHECK-NEXT: stxvx v2, 0, r3 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: dpConv2qp_02: @@ -1475,7 +1475,7 @@ ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: lfdx f1, 0, r3 +; CHECK-P8-NEXT: lfd f1, 0(r3) ; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha @@ -1501,7 +1501,7 @@ ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: xscvdpqp v2, v2 -; CHECK-NEXT: stxvx v2, 0, r3 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: dpConv2qp_02b: @@ -1639,7 +1639,7 @@ ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: xscvdpqp v2, v2 -; CHECK-NEXT: stxvx v2, 0, r3 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: spConv2qp_02: @@ -1649,7 +1649,7 @@ ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: lfsx f1, 0, r3 +; CHECK-P8-NEXT: lfs f1, 0(r3) ; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha @@ -1675,7 +1675,7 @@ ; CHECK-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: xscvdpqp v2, v2 -; CHECK-NEXT: stxvx v2, 0, r3 +; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: spConv2qp_02b: diff --git a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll --- a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll +++ b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll @@ -11,7 +11,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-NEXT: lxvx v2, 0, r3 +; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: loadConstant: @@ -32,7 +32,7 @@ ; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-NEXT: lxvx v3, 0, r3 +; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: blr ; @@ -608,7 +608,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld r3, 104(r1) ; CHECK-NEXT: stxv v2, 0(r9) -; CHECK-NEXT: stxvx v3, 0, r3 +; CHECK-NEXT: stxv v3, 0(r3) ; CHECK-NEXT: mtvsrwa v3, r10 ; CHECK-NEXT: lxv v2, 0(r9) ; CHECK-NEXT: xscvsdqp v3, v3 @@ -648,7 +648,7 @@ ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: stfdx f1, 0, r28 +; CHECK-P8-NEXT: stfd f1, 0(r28) ; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -713,7 +713,7 @@ ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: stfdx f1, 0, r28 +; CHECK-P8-NEXT: stfd f1, 0(r28) ; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll --- a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll @@ -413,7 +413,7 @@ ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sldi r4, r4, 3 ; CHECK-NEXT: ld r5, .LC0@toc@l(r5) -; CHECK-NEXT: lxvx v2, 0, r5 +; CHECK-NEXT: lxv v2, 0(r5) ; CHECK-NEXT: xscvqpudz v2, v2 ; CHECK-NEXT: stxsdx v2, r3, r4 ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll b/llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll --- a/llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll @@ -17,7 +17,7 @@ %this.addr = alloca %SomeStruct*, align 8 %V.addr = alloca double, align 8 store %SomeStruct* %this, %SomeStruct** %this.addr, align 8 -; ELF64VSX: stfdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}} +; ELF64VSX: stfd {{[0-9][0-9]?}}, -{{[1-9][0-9]?}}({{[1-9][0-9]?}}) store double %V, double* %V.addr, align 8 %this1 = load %SomeStruct*, %SomeStruct** %this.addr %Val = getelementptr inbounds %SomeStruct, %SomeStruct* %this1, i32 0, i32 0 diff --git a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll --- a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll +++ b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll @@ -42,8 +42,8 @@ ; CHECK-NEXT: ld 4, a15@toc@l(4) ; CHECK-NEXT: lfd 2, a2@toc@l(3) ; CHECK-NEXT: addis 3, 2, a3@toc@ha -; CHECK-NEXT: lxvx 34, 0, 6 -; CHECK-NEXT: lxvx 0, 0, 5 +; CHECK-NEXT: lxv 34, 0(6) +; CHECK-NEXT: lxv 0, 0(5) ; CHECK-NEXT: li 5, 152 ; CHECK-NEXT: lfd 3, a3@toc@l(3) ; CHECK-NEXT: addis 3, 2, a4@toc@ha diff --git a/llvm/test/CodeGen/PowerPC/fma-combine.ll b/llvm/test/CodeGen/PowerPC/fma-combine.ll --- a/llvm/test/CodeGen/PowerPC/fma-combine.ll +++ b/llvm/test/CodeGen/PowerPC/fma-combine.ll @@ -142,11 +142,11 @@ ; CHECK-FAST-LABEL: fma_combine_no_ice: ; CHECK-FAST: # %bb.0: ; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; CHECK-FAST-NEXT: addis 4, 2, .LCPI4_1@toc@ha ; CHECK-FAST-NEXT: lfs 0, .LCPI4_0@toc@l(3) -; CHECK-FAST-NEXT: lfsx 2, 0, 3 +; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_1@toc@ha +; CHECK-FAST-NEXT: lfs 2, 0(3) +; CHECK-FAST-NEXT: lfs 3, .LCPI4_1@toc@l(3) ; CHECK-FAST-NEXT: addis 3, 2, .LCPI4_2@toc@ha -; CHECK-FAST-NEXT: lfs 3, .LCPI4_1@toc@l(4) ; CHECK-FAST-NEXT: lfs 1, .LCPI4_2@toc@l(3) ; CHECK-FAST-NEXT: xsmaddasp 3, 2, 0 ; CHECK-FAST-NEXT: xsmaddasp 1, 2, 3 @@ -170,11 +170,11 @@ ; CHECK-LABEL: fma_combine_no_ice: ; CHECK: # %bb.0: ; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; CHECK-NEXT: addis 4, 2, .LCPI4_1@toc@ha ; CHECK-NEXT: lfs 0, .LCPI4_0@toc@l(3) -; CHECK-NEXT: lfsx 2, 0, 3 +; CHECK-NEXT: addis 3, 2, .LCPI4_1@toc@ha +; CHECK-NEXT: lfs 2, 0(3) +; CHECK-NEXT: lfs 3, .LCPI4_1@toc@l(3) ; CHECK-NEXT: addis 3, 2, .LCPI4_2@toc@ha -; CHECK-NEXT: lfs 3, .LCPI4_1@toc@l(4) ; CHECK-NEXT: lfs 1, .LCPI4_2@toc@l(3) ; CHECK-NEXT: fmr 4, 3 ; CHECK-NEXT: xsmaddasp 3, 2, 0 @@ -202,9 +202,9 @@ ; CHECK-FAST-LABEL: getNegatedExpression_crash: ; CHECK-FAST: # %bb.0: ; CHECK-FAST-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; CHECK-FAST-NEXT: addis 4, 2, .LCPI5_0@toc@ha ; CHECK-FAST-NEXT: lfs 3, .LCPI5_1@toc@l(3) -; CHECK-FAST-NEXT: lfs 4, .LCPI5_0@toc@l(4) +; CHECK-FAST-NEXT: addis 3, 2, .LCPI5_0@toc@ha +; CHECK-FAST-NEXT: lfs 4, .LCPI5_0@toc@l(3) ; CHECK-FAST-NEXT: xssubdp 0, 1, 3 ; CHECK-FAST-NEXT: xsmaddadp 3, 1, 4 ; CHECK-FAST-NEXT: xsmaddadp 0, 3, 2 @@ -225,9 +225,9 @@ ; CHECK-LABEL: getNegatedExpression_crash: ; CHECK: # %bb.0: ; CHECK-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; CHECK-NEXT: addis 4, 2, .LCPI5_0@toc@ha ; CHECK-NEXT: lfs 3, .LCPI5_1@toc@l(3) -; CHECK-NEXT: lfs 4, .LCPI5_0@toc@l(4) +; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha +; CHECK-NEXT: lfs 4, .LCPI5_0@toc@l(3) ; CHECK-NEXT: xssubdp 0, 1, 3 ; CHECK-NEXT: xsmaddadp 3, 1, 4 ; CHECK-NEXT: xsmaddadp 0, 3, 2 diff --git a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll --- a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll +++ b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll @@ -289,9 +289,9 @@ ; FMF-NEXT: # %bb.1: ; FMF-NEXT: xsrsqrtesp 0, 1 ; FMF-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; FMF-NEXT: addis 4, 2, .LCPI10_1@toc@ha ; FMF-NEXT: lfs 2, .LCPI10_0@toc@l(3) -; FMF-NEXT: lfs 3, .LCPI10_1@toc@l(4) +; FMF-NEXT: addis 3, 2, .LCPI10_1@toc@ha +; FMF-NEXT: lfs 3, .LCPI10_1@toc@l(3) ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 0 ; FMF-NEXT: xsmulsp 1, 1, 2 @@ -312,9 +312,9 @@ ; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: xsrsqrtesp 0, 1 ; GLOBAL-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; GLOBAL-NEXT: addis 4, 2, .LCPI10_1@toc@ha ; GLOBAL-NEXT: lfs 2, .LCPI10_0@toc@l(3) -; GLOBAL-NEXT: lfs 3, .LCPI10_1@toc@l(4) +; GLOBAL-NEXT: addis 3, 2, .LCPI10_1@toc@ha +; GLOBAL-NEXT: lfs 3, .LCPI10_1@toc@l(3) ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmulsp 0, 1, 3 @@ -357,9 +357,9 @@ ; FMF-NEXT: # %bb.1: ; FMF-NEXT: xsrsqrtesp 0, 1 ; FMF-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; FMF-NEXT: addis 4, 2, .LCPI12_1@toc@ha ; FMF-NEXT: lfs 2, .LCPI12_0@toc@l(3) -; FMF-NEXT: lfs 3, .LCPI12_1@toc@l(4) +; FMF-NEXT: addis 3, 2, .LCPI12_1@toc@ha +; FMF-NEXT: lfs 3, .LCPI12_1@toc@l(3) ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 0 ; FMF-NEXT: xsmulsp 1, 1, 2 @@ -377,9 +377,9 @@ ; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: xsrsqrtesp 0, 1 ; GLOBAL-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; GLOBAL-NEXT: addis 4, 2, .LCPI12_1@toc@ha ; GLOBAL-NEXT: lfs 2, .LCPI12_0@toc@l(3) -; GLOBAL-NEXT: lfs 3, .LCPI12_1@toc@l(4) +; GLOBAL-NEXT: addis 3, 2, .LCPI12_1@toc@ha +; GLOBAL-NEXT: lfs 3, .LCPI12_1@toc@l(3) ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmulsp 0, 1, 3 @@ -427,9 +427,9 @@ ; FMF-NEXT: # %bb.1: ; FMF-NEXT: xsrsqrtesp 0, 1 ; FMF-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; FMF-NEXT: addis 4, 2, .LCPI14_1@toc@ha ; FMF-NEXT: lfs 2, .LCPI14_0@toc@l(3) -; FMF-NEXT: lfs 3, .LCPI14_1@toc@l(4) +; FMF-NEXT: addis 3, 2, .LCPI14_1@toc@ha +; FMF-NEXT: lfs 3, .LCPI14_1@toc@l(3) ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmaddasp 2, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 3 @@ -449,9 +449,9 @@ ; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: xsrsqrtesp 0, 1 ; GLOBAL-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; GLOBAL-NEXT: addis 4, 2, .LCPI14_1@toc@ha ; GLOBAL-NEXT: lfs 2, .LCPI14_0@toc@l(3) -; GLOBAL-NEXT: lfs 3, .LCPI14_1@toc@l(4) +; GLOBAL-NEXT: addis 3, 2, .LCPI14_1@toc@ha +; GLOBAL-NEXT: lfs 3, .LCPI14_1@toc@l(3) ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmulsp 0, 1, 3 @@ -482,9 +482,9 @@ ; FMF-NEXT: # %bb.1: ; FMF-NEXT: xsrsqrtesp 0, 1 ; FMF-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; FMF-NEXT: addis 4, 2, .LCPI15_1@toc@ha ; FMF-NEXT: lfs 2, .LCPI15_0@toc@l(3) -; FMF-NEXT: lfs 3, .LCPI15_1@toc@l(4) +; FMF-NEXT: addis 3, 2, .LCPI15_1@toc@ha +; FMF-NEXT: lfs 3, .LCPI15_1@toc@l(3) ; FMF-NEXT: xsmulsp 1, 1, 0 ; FMF-NEXT: xsmaddasp 2, 1, 0 ; FMF-NEXT: xsmulsp 0, 1, 3 @@ -501,9 +501,9 @@ ; GLOBAL-NEXT: # %bb.1: ; GLOBAL-NEXT: xsrsqrtesp 0, 1 ; GLOBAL-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; GLOBAL-NEXT: addis 4, 2, .LCPI15_1@toc@ha ; GLOBAL-NEXT: lfs 2, .LCPI15_0@toc@l(3) -; GLOBAL-NEXT: lfs 3, .LCPI15_1@toc@l(4) +; GLOBAL-NEXT: addis 3, 2, .LCPI15_1@toc@ha +; GLOBAL-NEXT: lfs 3, .LCPI15_1@toc@l(3) ; GLOBAL-NEXT: xsmulsp 1, 1, 0 ; GLOBAL-NEXT: xsmaddasp 2, 1, 0 ; GLOBAL-NEXT: xsmulsp 0, 1, 3 diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll --- a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll +++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll @@ -617,8 +617,8 @@ ; P8-NEXT: xxlxor f3, f3, f3 ; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; P8-NEXT: lfs f0, .LCPI13_0@toc@l(r3) -; P8-NEXT: fcmpo cr0, f2, f3 ; P8-NEXT: lis r3, -32768 +; P8-NEXT: fcmpo cr0, f2, f3 ; P8-NEXT: xxlxor f3, f3, f3 ; P8-NEXT: fcmpo cr1, f1, f0 ; P8-NEXT: crand 4*cr5+lt, 4*cr1+eq, lt diff --git a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll --- a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll +++ b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll @@ -45,12 +45,12 @@ ; PPC64-DAG: stfd 2, [[OFFSET_HI:-?[0-9]+]]([[SP:[0-9]+]]) ; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]]) ; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1 -; PPC64-DAG: rldic [[FLIP_BIT]], [[FLIP_BIT]], 63, 0 +; PPC64-DAG: rldic [[RES:[0-9]+]], [[FLIP_BIT]], 63, 0 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]]) ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]]) ; PPC64-NOT: BARRIER -; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]] -; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]] +; PPC64-DAG: xor 3, [[HI]], [[RES]] +; PPC64-DAG: xor 4, [[LO]], [[RES]] ; PPC64: blr ; PPC64-P8-LABEL: test_neg: diff --git a/llvm/test/CodeGen/PowerPC/instr-properties.ll b/llvm/test/CodeGen/PowerPC/instr-properties.ll --- a/llvm/test/CodeGen/PowerPC/instr-properties.ll +++ b/llvm/test/CodeGen/PowerPC/instr-properties.ll @@ -3,7 +3,7 @@ ; Verify XFLOADf64 didn't implict def 'rm'. define double @rm() { ; CHECK-P8-LABEL: bb.0.entry -; CHECK-P8: %{{[0-9]+}}:vsfrc = XFLOADf64 $zero8, %{{[0-9]+}} :: +; CHECK-P8: %{{[0-9]+}}:f8rc = LFD target-flags(ppc-toc-lo) %const.0, %{{[0-9]+}}, implicit $x2 :: entry: ret double 2.300000e+00 } diff --git a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll --- a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll +++ b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll @@ -96,7 +96,7 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x i32>, <4 x i32>* %vp1 @@ -134,7 +134,7 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x i32>, <4 x i32>* %vp1 @@ -172,7 +172,7 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <8 x i16>, <8 x i16>* %vp1 @@ -210,7 +210,7 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <8 x i16>, <8 x i16>* %vp1 @@ -346,7 +346,7 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x float>, <4 x float>* %vp1 @@ -384,7 +384,7 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x float>, <4 x float>* %vp1 @@ -475,7 +475,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI13_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -512,7 +512,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI14_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI14_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 +; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -549,7 +549,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -586,7 +586,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 +; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -745,7 +745,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI21_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI21_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v3, 0, r3 +; CHECK-P9-BE-NEXT: lxv v3, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr @@ -782,7 +782,7 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI22_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI22_0@toc@l -; CHECK-P9-BE-NEXT: lxvx v2, 0, r3 +; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll b/llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll --- a/llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll +++ b/llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -ppc-late-peephole=false -o - %s | FileCheck %s +; RUN: llc -O3 -ppc-late-peephole=false -ppc-convert-rr-to-ri=false -o - %s | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/mcm-4.ll b/llvm/test/CodeGen/PowerPC/mcm-4.ll --- a/llvm/test/CodeGen/PowerPC/mcm-4.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-4.ll @@ -33,7 +33,7 @@ ; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0 ; MEDIUM-VSX-LABEL: test_double_const: ; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha -; MEDIUM-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) +; MEDIUM-VSX: lfd {{[0-9]+}}, 0({{[0-9]+}}) ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: ; LARGE: .quad 0x3f4fd4920b498cf0 @@ -47,7 +47,7 @@ ; LARGE-VSX-LABEL: test_double_const: ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) -; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] +; LARGE-VSX: lfd {{[0-9]+}}, 0({{[0-9]+}}) ; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]: ; MEDIUM-P9: .quad 0x3f4fd4920b498cf0 diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll --- a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll +++ b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll @@ -55,7 +55,7 @@ ; CHECK-NEXT: stxv vs0, 48(r30) ; CHECK-NEXT: stxv vs1, 32(r30) ; CHECK-NEXT: stxv vs2, 16(r30) -; CHECK-NEXT: stxvx vs3, 0, r30 +; CHECK-NEXT: stxv vs3, 0(r30) ; CHECK-NEXT: addi r1, r1, 176 ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -105,7 +105,7 @@ ; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v4 ; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: stxv vs1, 16(r30) -; CHECK-BE-NEXT: stxvx vs0, 0, r30 +; CHECK-BE-NEXT: stxv vs0, 0(r30) ; CHECK-BE-NEXT: stxv vs3, 48(r30) ; CHECK-BE-NEXT: stxv vs2, 32(r30) ; CHECK-BE-NEXT: ld r30, 240(r1) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll --- a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll +++ b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll @@ -31,7 +31,7 @@ ; CHECK-NEXT: stxv vs0, 48(r3) ; CHECK-NEXT: stxv vs1, 32(r3) ; CHECK-NEXT: stxv vs2, 16(r3) -; CHECK-NEXT: stxvx vs3, 0, r3 +; CHECK-NEXT: stxv vs3, 0(r3) ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: intrinsics1: @@ -54,7 +54,7 @@ ; CHECK-BE-NEXT: pmxvf64gernp acc0, vsp4, v0, 0, 0 ; CHECK-BE-NEXT: xxmfacc acc0 ; CHECK-BE-NEXT: stxv vs1, 16(r3) -; CHECK-BE-NEXT: stxvx vs0, 0, r3 +; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/mul-const-vector.ll b/llvm/test/CodeGen/PowerPC/mul-const-vector.ll --- a/llvm/test/CodeGen/PowerPC/mul-const-vector.ll +++ b/llvm/test/CodeGen/PowerPC/mul-const-vector.ll @@ -277,7 +277,7 @@ ; CHECK-LABEL: test1_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]] @@ -289,7 +289,7 @@ ; CHECK-LABEL: test2_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]] @@ -302,7 +302,7 @@ ; CHECK-LABEL: test3_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2 @@ -317,7 +317,7 @@ ; CHECK-LABEL: test4_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]], @@ -332,7 +332,7 @@ ; CHECK-LABEL: test5_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]] @@ -348,7 +348,7 @@ ; CHECK-LABEL: test6_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]] @@ -364,7 +364,7 @@ ; CHECK-LABEL: test7_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]] @@ -376,7 +376,7 @@ ; CHECK-LABEL: test8_v2i64: ; CHECK-P8: lxvd2x vs[[REG1:[0-9]+]], 0, r{{[0-9]+}} ; CHECK-P8-NEXT: xxswapd v[[REG2:[0-9]+]], vs[[REG1]] -; CHECK-P9: lxvx v[[REG2:[0-9]+]], 0, r{{[0-9]+}} +; CHECK-P9: lxv v[[REG2:[0-9]+]], 0(r{{[0-9]+}}) ; CHECK-NOT: vmul ; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]] ; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2 diff --git a/llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll b/llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll --- a/llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll +++ b/llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll @@ -7,12 +7,12 @@ ; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3 ; CHECK-NEXT: #DEBUG_VALUE: test:Vptr <- $x4 ; CHECK-NEXT: addis 5, 2, .LCPI0_0@toc@ha +; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3 ; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .loc 1 2 38 prologue_end -; CHECK-NEXT: lfsx 0, 0, 3 +; CHECK-NEXT: lfs 0, 0(3) ; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; CHECK-NEXT: .Ltmp1: -; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3 ; CHECK-NEXT: .loc 1 0 38 is_stmt 0 ; CHECK-NEXT: lfs 1, .LCPI0_0@toc@l(5) ; CHECK-NEXT: lfd 2, .LCPI0_1@toc@l(3) diff --git a/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll b/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll --- a/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll +++ b/llvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll @@ -37,7 +37,7 @@ ; CHECK-NOPREFIX: # %bb.0: # %entry ; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-NOPREFIX-NEXT: lxvx vs34, 0, r3 +; CHECK-NOPREFIX-NEXT: lxv vs34, 0(r3) ; CHECK-NOPREFIX-NEXT: blr ; ; CHECK-BE-LABEL: testDoubleToDoubleFail: @@ -72,7 +72,7 @@ ; CHECK-NOPREFIX: # %bb.0: # %entry ; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-NOPREFIX-NEXT: lxvx vs34, 0, r3 +; CHECK-NOPREFIX-NEXT: lxv vs34, 0(r3) ; CHECK-NOPREFIX-NEXT: blr ; ; CHECK-BE-LABEL: testFloatDenormToDouble: @@ -107,7 +107,7 @@ ; CHECK-NOPREFIX: # %bb.0: # %entry ; CHECK-NOPREFIX-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-NOPREFIX-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-NOPREFIX-NEXT: lxvx vs34, 0, r3 +; CHECK-NOPREFIX-NEXT: lxv vs34, 0(r3) ; CHECK-NOPREFIX-NEXT: blr ; ; CHECK-BE-LABEL: testDoubleToDoubleNaNFail: diff --git a/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll b/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll --- a/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll +++ b/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll @@ -34,7 +34,7 @@ ; CHECK-BE: # %bb.0: ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vrlq v2, v3, v2 ; CHECK-BE-NEXT: blr %shl.i = shl <1 x i128> , %x @@ -55,7 +55,7 @@ ; CHECK-BE: # %bb.0: ; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vrlq v2, v3, v2 ; CHECK-BE-NEXT: blr %shl.i = shl <1 x i128> , %x @@ -90,7 +90,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxvx v5, 0, r3 +; CHECK-BE-NEXT: lxv v5, 0(r3) ; CHECK-BE-NEXT: vperm v3, v3, v4, v5 ; CHECK-BE-NEXT: vrlqnm v2, v2, v3 ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll --- a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll +++ b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll @@ -451,7 +451,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -464,7 +464,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -482,7 +482,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -505,7 +505,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -518,7 +518,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -536,7 +536,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -559,7 +559,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -577,7 +577,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1455,7 +1455,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1478,7 +1478,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1496,7 +1496,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1509,7 +1509,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1527,7 +1527,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1550,7 +1550,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1568,7 +1568,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1586,7 +1586,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1599,7 +1599,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1617,7 +1617,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1635,7 +1635,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1658,7 +1658,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1676,7 +1676,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: @@ -1689,7 +1689,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1707,7 +1707,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l -; CHECK-NEXT: lxvx 35, 0, 3 +; CHECK-NEXT: lxv 35, 0(3) ; CHECK-NEXT: vperm 2, 2, 2, 3 ; CHECK-NEXT: blr ; @@ -1730,7 +1730,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll --- a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll +++ b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll @@ -110,9 +110,13 @@ ; CHECK-LABEL: ReadWrite128: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, input128@got@pcrel(0), 1 -; CHECK-NEXT: lxvx vs0, 0, r3 +; CHECK-NEXT: .Lpcrel4: +; CHECK-NEXT: .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8) +; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: pld r3, output128@got@pcrel(0), 1 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: .Lpcrel5: +; CHECK-NEXT: .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8) +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr entry: %0 = load i128, i128* @input128, align 16 @@ -124,9 +128,9 @@ ; CHECK-LABEL: ReadWritef32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, inputf32@got@pcrel(0), 1 -; CHECK-NEXT: .Lpcrel4: +; CHECK-NEXT: .Lpcrel6: ; CHECK-NEXT: xxspltidp vs1, 1078103900 -; CHECK-NEXT: .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8) +; CHECK-NEXT: .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8) ; CHECK-NEXT: lfs f0, 0(r3) ; CHECK-NEXT: pld r3, outputf32@got@pcrel(0), 1 ; CHECK-NEXT: xsaddsp f0, f0, f1 @@ -143,9 +147,9 @@ ; CHECK-LABEL: ReadWritef64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, inputf64@got@pcrel(0), 1 -; CHECK-NEXT: .Lpcrel5: +; CHECK-NEXT: .Lpcrel7: ; CHECK-NEXT: plfd f1, .LCPI6_0@PCREL(0), 1 -; CHECK-NEXT: .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8) +; CHECK-NEXT: .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8) ; CHECK-NEXT: lfd f0, 0(r3) ; CHECK-NEXT: pld r3, outputf64@got@pcrel(0), 1 ; CHECK-NEXT: xsadddp f0, f0, f1 @@ -164,12 +168,14 @@ ; CHECK-LABEL: ReadWriteVi32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, inputVi32@got@pcrel(0), 1 +; CHECK-NEXT: .Lpcrel8: ; CHECK-NEXT: li r4, 45 ; CHECK-NEXT: mtfprwz f1, r4 -; CHECK-NEXT: lxvx vs0, 0, r3 +; CHECK-NEXT: .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8) +; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: pld r3, outputVi32@got@pcrel(0), 1 ; CHECK-NEXT: xxinsertw vs0, vs1, 8 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr entry: %0 = load <4 x i32>, <4 x i32>* @inputVi32, align 16 @@ -182,9 +188,13 @@ ; CHECK-LABEL: ReadWriteVi64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, inputVi64@got@pcrel(0), 1 -; CHECK-NEXT: lxvx vs0, 0, r3 +; CHECK-NEXT: .Lpcrel9: +; CHECK-NEXT: .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8) +; CHECK-NEXT: lxv vs0, 0(r3) ; CHECK-NEXT: pld r3, outputVi64@got@pcrel(0), 1 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: .Lpcrel10: +; CHECK-NEXT: .reloc .Lpcrel10-8,R_PPC64_PCREL_OPT,.-(.Lpcrel10-8) +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr entry: %0 = load <2 x i64>, <2 x i64>* @inputVi64, align 16 @@ -196,9 +206,9 @@ ; CHECK-LABEL: ReadWriteArray: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, ArrayIn@got@pcrel(0), 1 -; CHECK-NEXT: .Lpcrel6: +; CHECK-NEXT: .Lpcrel11: ; CHECK-NEXT: pld r4, ArrayOut@got@pcrel(0), 1 -; CHECK-NEXT: .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8) +; CHECK-NEXT: .reloc .Lpcrel11-8,R_PPC64_PCREL_OPT,.-(.Lpcrel11-8) ; CHECK-NEXT: lwz r3, 28(r3) ; CHECK-NEXT: addi r3, r3, 42 ; CHECK-NEXT: stw r3, 8(r4) @@ -229,12 +239,12 @@ ; CHECK-LABEL: ReadWriteIntPtr: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, IntPtrIn@got@pcrel(0), 1 -; CHECK-NEXT: .Lpcrel7: +; CHECK-NEXT: .Lpcrel12: ; CHECK-NEXT: pld r4, IntPtrOut@got@pcrel(0), 1 -; CHECK-NEXT: .Lpcrel8: -; CHECK-NEXT: .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8) +; CHECK-NEXT: .Lpcrel13: +; CHECK-NEXT: .reloc .Lpcrel12-8,R_PPC64_PCREL_OPT,.-(.Lpcrel12-8) ; CHECK-NEXT: ld r3, 0(r3) -; CHECK-NEXT: .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8) +; CHECK-NEXT: .reloc .Lpcrel13-8,R_PPC64_PCREL_OPT,.-(.Lpcrel13-8) ; CHECK-NEXT: ld r4, 0(r4) ; CHECK-NEXT: lwz r5, 216(r3) ; CHECK-NEXT: lwz r3, 48(r3) @@ -258,9 +268,9 @@ ; CHECK-LABEL: ReadWriteFuncPtr: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, FuncPtrIn@got@pcrel(0), 1 -; CHECK-NEXT: .Lpcrel9: +; CHECK-NEXT: .Lpcrel14: ; CHECK-NEXT: pld r4, FuncPtrOut@got@pcrel(0), 1 -; CHECK-NEXT: .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8) +; CHECK-NEXT: .reloc .Lpcrel14-8,R_PPC64_PCREL_OPT,.-(.Lpcrel14-8) ; CHECK-NEXT: ld r3, 0(r3) ; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr @@ -289,8 +299,8 @@ ; CHECK: .localentry FuncPtrCall, 1 ; CHECK-NEXT: # %bb.0: # %entry ; CHECK-NEXT: pld r3, FuncPtrIn@got@pcrel(0), 1 -; CHECK-NEXT: .Lpcrel10: -; CHECK-NEXT: .reloc .Lpcrel10-8,R_PPC64_PCREL_OPT,.-(.Lpcrel10-8) +; CHECK-NEXT: .Lpcrel15: +; CHECK-NEXT: .reloc .Lpcrel15-8,R_PPC64_PCREL_OPT,.-(.Lpcrel15-8) ; CHECK-NEXT: ld r12, 0(r3) ; CHECK-NEXT: mtctr r12 ; CHECK-NEXT: bctr @@ -305,8 +315,8 @@ ; CHECK-LABEL: ReadVecElement: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pld r3, inputVi32@got@pcrel(0), 1 -; CHECK-NEXT: .Lpcrel11: -; CHECK-NEXT: .reloc .Lpcrel11-8,R_PPC64_PCREL_OPT,.-(.Lpcrel11-8) +; CHECK-NEXT: .Lpcrel16: +; CHECK-NEXT: .reloc .Lpcrel16-8,R_PPC64_PCREL_OPT,.-(.Lpcrel16-8) ; CHECK-NEXT: lwa r3, 4(r3) ; CHECK-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll --- a/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll @@ -33,14 +33,14 @@ ; ; CHECK-VSX-LABEL: test: ; CHECK-VSX: # %bb.0: # %entry -; CHECK-VSX-NEXT: std 3, 48(1) -; CHECK-VSX-NEXT: std 6, 72(1) -; CHECK-VSX-NEXT: std 5, 64(1) -; CHECK-VSX-NEXT: std 4, 56(1) ; CHECK-VSX-NEXT: std 5, -16(1) ; CHECK-VSX-NEXT: std 6, -8(1) ; CHECK-VSX-NEXT: lfd 1, -16(1) ; CHECK-VSX-NEXT: lfd 2, -8(1) +; CHECK-VSX-NEXT: std 6, 72(1) +; CHECK-VSX-NEXT: std 5, 64(1) +; CHECK-VSX-NEXT: std 3, 48(1) +; CHECK-VSX-NEXT: std 4, 56(1) ; CHECK-VSX-NEXT: blr ; ; CHECK-P9-LABEL: test: diff --git a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll --- a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll @@ -63,7 +63,7 @@ ; FIXME: li [[R1:r[0-9]+]], 1 ; FIXME: li [[R2:r[0-9]+]], 0 ; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]] -; CHECK-P9: lxvx [[V1:v[0-9]+]] +; CHECK-P9: lxv [[V1:v[0-9]+]] ; CHECK-P9: vadduqm v2, v2, [[V1]] ; CHECK-P9: blr @@ -237,8 +237,8 @@ ; CHECK-LE: blr ; CHECK-P9-LABEL: @call_v1i128_increment_by_val -; CHECK-P9-DAG: lxvx v2 -; CHECK-P9-DAG: lxvx v3 +; CHECK-P9-DAG: lxv v2 +; CHECK-P9-DAG: lxv v3 ; CHECK-P9: bl v1i128_increment_by_val ; CHECK-P9: blr diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll --- a/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll +++ b/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll @@ -1293,8 +1293,8 @@ ; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha ; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: lfs 0, .LCPI31_0@toc@l(3) -; PC64LE-NEXT: fcmpo 0, 2, 3 ; PC64LE-NEXT: lis 3, -32768 +; PC64LE-NEXT: fcmpo 0, 2, 3 ; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: fcmpo 1, 1, 0 ; PC64LE-NEXT: crand 20, 6, 0 @@ -1428,12 +1428,12 @@ ; PC64LE-NEXT: xxlxor 2, 2, 2 ; PC64LE-NEXT: li 3, 0 ; PC64LE-NEXT: mr 30, 4 -; PC64LE-NEXT: lfsx 31, 0, 29 +; PC64LE-NEXT: lfs 31, 0(29) ; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: std 3, 8(4) ; PC64LE-NEXT: fmr 1, 31 ; PC64LE-NEXT: fmr 3, 31 -; PC64LE-NEXT: stfdx 31, 0, 4 +; PC64LE-NEXT: stfd 31, 0(4) ; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: nop ; PC64LE-NEXT: fmr 3, 1 @@ -1452,7 +1452,7 @@ ; PC64LE-NEXT: bl __powitf2 ; PC64LE-NEXT: nop ; PC64LE-NEXT: xsrsp 0, 1 -; PC64LE-NEXT: stfsx 0, 0, 29 +; PC64LE-NEXT: stfs 0, 0(29) ; PC64LE-NEXT: stfd 1, -16(30) ; PC64LE-NEXT: stfd 2, -8(30) ; PC64LE-NEXT: addi 1, 1, 80 @@ -1727,8 +1727,8 @@ ; PC64LE-NEXT: addis 3, 2, .LCPI36_0@toc@ha ; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: fmr 31, 2 ; PC64LE-NEXT: lfs 3, .LCPI36_0@toc@l(3) +; PC64LE-NEXT: fmr 31, 2 ; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: nop ; PC64LE-NEXT: cmpdi 30, 0 @@ -1879,8 +1879,8 @@ ; PC64LE-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: fmr 30, 1 -; PC64LE-NEXT: fmr 31, 2 ; PC64LE-NEXT: lfd 3, .LCPI38_0@toc@l(3) +; PC64LE-NEXT: fmr 31, 2 ; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: nop ; PC64LE-NEXT: cmpdi 30, 0 diff --git a/llvm/test/CodeGen/PowerPC/pr30715.ll b/llvm/test/CodeGen/PowerPC/pr30715.ll --- a/llvm/test/CodeGen/PowerPC/pr30715.ll +++ b/llvm/test/CodeGen/PowerPC/pr30715.ll @@ -67,7 +67,7 @@ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body -; CHECK: stfdx +; CHECK: stfd ; CHECK: lxvd2x } diff --git a/llvm/test/CodeGen/PowerPC/pr36292.ll b/llvm/test/CodeGen/PowerPC/pr36292.ll --- a/llvm/test/CodeGen/PowerPC/pr36292.ll +++ b/llvm/test/CodeGen/PowerPC/pr36292.ll @@ -19,12 +19,12 @@ ; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB0_1: # %bounds.ok ; CHECK-NEXT: # -; CHECK-NEXT: lfsx 2, 0, 3 +; CHECK-NEXT: lfs 2, 0(3) ; CHECK-NEXT: xxlxor 1, 1, 1 ; CHECK-NEXT: bl fmodf ; CHECK-NEXT: nop ; CHECK-NEXT: addi 30, 30, 1 -; CHECK-NEXT: stfsx 1, 0, 3 +; CHECK-NEXT: stfs 1, 0(3) ; CHECK-NEXT: cmpld 30, 29 ; CHECK-NEXT: blt+ 0, .LBB0_1 ; CHECK-NEXT: .LBB0_2: # %bounds.fail diff --git a/llvm/test/CodeGen/PowerPC/pr38087.ll b/llvm/test/CodeGen/PowerPC/pr38087.ll --- a/llvm/test/CodeGen/PowerPC/pr38087.ll +++ b/llvm/test/CodeGen/PowerPC/pr38087.ll @@ -17,7 +17,7 @@ ; CHECK-NEXT: xvcvsxwsp vs0, v3 ; CHECK-NEXT: xxspltw vs0, vs0, 2 ; CHECK-NEXT: xvmaddasp vs0, v2, v2 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr entry: %.size = load i32, i32* undef diff --git a/llvm/test/CodeGen/PowerPC/pr43527.ll b/llvm/test/CodeGen/PowerPC/pr43527.ll --- a/llvm/test/CodeGen/PowerPC/pr43527.ll +++ b/llvm/test/CodeGen/PowerPC/pr43527.ll @@ -23,7 +23,7 @@ ; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB0_3: # %bb5 ; CHECK-NEXT: # -; CHECK-NEXT: lfsx f1, 0, r29 +; CHECK-NEXT: lfs f1, 0(r29) ; CHECK-NEXT: bl lrint ; CHECK-NEXT: nop ; CHECK-NEXT: addi r30, r30, -1 diff --git a/llvm/test/CodeGen/PowerPC/pr45628.ll b/llvm/test/CodeGen/PowerPC/pr45628.ll --- a/llvm/test/CodeGen/PowerPC/pr45628.ll +++ b/llvm/test/CodeGen/PowerPC/pr45628.ll @@ -270,13 +270,13 @@ ; P9-VSX: # %bb.0: # %entry ; P9-VSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha ; P9-VSX-NEXT: addi r3, r3, .LCPI8_0@toc@l -; P9-VSX-NEXT: lxvx v3, 0, r3 +; P9-VSX-NEXT: lxv v3, 0(r3) ; P9-VSX-NEXT: addis r3, r2, .LCPI8_1@toc@ha ; P9-VSX-NEXT: addi r3, r3, .LCPI8_1@toc@l ; P9-VSX-NEXT: vslo v4, v2, v3 ; P9-VSX-NEXT: vspltb v3, v3, 15 ; P9-VSX-NEXT: vsl v3, v4, v3 -; P9-VSX-NEXT: lxvx v4, 0, r3 +; P9-VSX-NEXT: lxv v4, 0(r3) ; P9-VSX-NEXT: vsro v2, v2, v4 ; P9-VSX-NEXT: vspltb v4, v4, 15 ; P9-VSX-NEXT: vsr v2, v2, v4 diff --git a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll --- a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll +++ b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll @@ -16,10 +16,10 @@ ; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: li r6, 0 ; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l -; CHECK-NEXT: lxvx v2, 0, r5 +; CHECK-NEXT: lxv v2, 0(r5) ; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha ; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l -; CHECK-NEXT: lxvx v4, 0, r5 +; CHECK-NEXT: lxv v4, 0(r5) ; CHECK-NEXT: li r5, 4 ; CHECK-NEXT: vperm v0, v3, v5, v2 ; CHECK-NEXT: mtctr r5 @@ -72,11 +72,11 @@ ; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: li r6, 0 ; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l -; P9BE-NEXT: lxvx v2, 0, r5 +; P9BE-NEXT: lxv v2, 0(r5) ; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha ; P9BE-NEXT: xxlor v5, vs0, vs0 ; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l -; P9BE-NEXT: lxvx v4, 0, r5 +; P9BE-NEXT: lxv v4, 0(r5) ; P9BE-NEXT: li r5, 4 ; P9BE-NEXT: vperm v0, v3, v5, v2 ; P9BE-NEXT: mtctr r5 @@ -183,10 +183,10 @@ ; CHECK-NEXT: lxsd v1, 0(r4) ; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-NEXT: lxvx v4, 0, r3 +; CHECK-NEXT: lxv v4, 0(r3) ; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l -; CHECK-NEXT: lxvx v0, 0, r3 +; CHECK-NEXT: lxv v0, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: vperm v5, v3, v2, v4 ; CHECK-NEXT: vperm v2, v3, v2, v0 @@ -209,12 +209,12 @@ ; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; P9BE-NEXT: lxvx v4, 0, r3 +; P9BE-NEXT: lxv v4, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l ; P9BE-NEXT: xxlor v2, vs0, vs0 ; P9BE-NEXT: lfd f0, 0(r4) -; P9BE-NEXT: lxvx v0, 0, r3 +; P9BE-NEXT: lxv v0, 0(r3) ; P9BE-NEXT: xxlor v1, vs0, vs0 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vperm v5, v3, v2, v4 @@ -285,7 +285,7 @@ ; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-NEXT: xxlxor v3, v3, v3 ; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-NEXT: lxvx v4, 0, r3 +; CHECK-NEXT: lxv v4, 0(r3) ; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: lxsiwzx v5, r5, r3 ; CHECK-NEXT: vperm v2, v2, v3, v4 @@ -296,7 +296,7 @@ ; CHECK-NEXT: vslw v3, v3, v4 ; CHECK-NEXT: vsubuwm v2, v3, v2 ; CHECK-NEXT: xxswapd vs0, v2 -; CHECK-NEXT: stxvx vs0, 0, r3 +; CHECK-NEXT: stxv vs0, 0(r3) ; CHECK-NEXT: blr ; ; P9BE-LABEL: test32: @@ -307,7 +307,7 @@ ; P9BE-NEXT: xxlxor v3, v3, v3 ; P9BE-NEXT: xxsldwi v2, f0, f0, 1 ; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; P9BE-NEXT: lxvx v4, 0, r3 +; P9BE-NEXT: lxv v4, 0(r3) ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: lfiwzx f0, r5, r3 ; P9BE-NEXT: vperm v2, v3, v2, v4 @@ -319,7 +319,7 @@ ; P9BE-NEXT: vslw v3, v3, v4 ; P9BE-NEXT: vsubuwm v2, v3, v2 ; P9BE-NEXT: xxswapd vs0, v2 -; P9BE-NEXT: stxvx vs0, 0, r3 +; P9BE-NEXT: stxv vs0, 0(r3) ; P9BE-NEXT: blr entry: %idx.ext63 = sext i32 %i_pix2 to i64 @@ -363,7 +363,7 @@ ; CHECK-NEXT: vmrghh v2, v3, v2 ; CHECK-NEXT: vsplth v3, v3, 3 ; CHECK-NEXT: vmrglw v3, v4, v3 -; CHECK-NEXT: lxvx v4, 0, r3 +; CHECK-NEXT: lxv v4, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: vperm v2, v2, v3, v4 ; CHECK-NEXT: xxspltw v3, v2, 2 @@ -391,7 +391,7 @@ ; P9BE-NEXT: vmrghh v2, v3, v2 ; P9BE-NEXT: vsplth v3, v3, 0 ; P9BE-NEXT: vmrghw v3, v3, v4 -; P9BE-NEXT: lxvx v4, 0, r3 +; P9BE-NEXT: lxv v4, 0(r3) ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: xxspltw v3, v2, 1 @@ -452,7 +452,7 @@ ; CHECK-NEXT: vmrglw v2, v2, v4 ; CHECK-NEXT: vmrglh v3, v3, v4 ; CHECK-NEXT: vmrglw v3, v4, v3 -; CHECK-NEXT: lxvx v4, 0, r3 +; CHECK-NEXT: lxv v4, 0(r3) ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: vperm v2, v3, v2, v4 ; CHECK-NEXT: xxspltw v3, v2, 2 @@ -481,7 +481,7 @@ ; P9BE-NEXT: vmrghh v4, v4, v3 ; P9BE-NEXT: xxspltw v3, v3, 0 ; P9BE-NEXT: vmrghw v2, v4, v2 -; P9BE-NEXT: lxvx v4, 0, r3 +; P9BE-NEXT: lxv v4, 0(r3) ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: xxspltw v3, v2, 1 diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll --- a/llvm/test/CodeGen/PowerPC/recipest.ll +++ b/llvm/test/CodeGen/PowerPC/recipest.ll @@ -136,14 +136,14 @@ ; CHECK-P8-LABEL: foof_fmf: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsrsqrtesp 0, 2 +; CHECK-P8-NEXT: addis 3, 2, .LCPI3_1@toc@ha +; CHECK-P8-NEXT: lfs 3, .LCPI3_1@toc@l(3) ; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI3_1@toc@ha -; CHECK-P8-NEXT: lfs 3, .LCPI3_0@toc@l(3) -; CHECK-P8-NEXT: lfs 4, .LCPI3_1@toc@l(4) +; CHECK-P8-NEXT: lfs 4, .LCPI3_0@toc@l(3) ; CHECK-P8-NEXT: xsmulsp 2, 2, 0 -; CHECK-P8-NEXT: xsmaddasp 3, 2, 0 -; CHECK-P8-NEXT: xsmulsp 0, 0, 4 -; CHECK-P8-NEXT: xsmulsp 0, 0, 3 +; CHECK-P8-NEXT: xsmulsp 3, 0, 3 +; CHECK-P8-NEXT: xsmaddasp 4, 2, 0 +; CHECK-P8-NEXT: xsmulsp 0, 3, 4 ; CHECK-P8-NEXT: xsmuldp 1, 1, 0 ; CHECK-P8-NEXT: blr ; @@ -300,14 +300,14 @@ ; CHECK-P8-LABEL: goo_fmf: ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsrsqrtesp 0, 2 +; CHECK-P8-NEXT: addis 3, 2, .LCPI7_1@toc@ha +; CHECK-P8-NEXT: lfs 3, .LCPI7_1@toc@l(3) ; CHECK-P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI7_1@toc@ha -; CHECK-P8-NEXT: lfs 3, .LCPI7_0@toc@l(3) -; CHECK-P8-NEXT: lfs 4, .LCPI7_1@toc@l(4) +; CHECK-P8-NEXT: lfs 4, .LCPI7_0@toc@l(3) ; CHECK-P8-NEXT: xsmulsp 2, 2, 0 -; CHECK-P8-NEXT: xsmaddasp 3, 2, 0 -; CHECK-P8-NEXT: xsmulsp 0, 0, 4 -; CHECK-P8-NEXT: xsmulsp 0, 0, 3 +; CHECK-P8-NEXT: xsmulsp 3, 0, 3 +; CHECK-P8-NEXT: xsmaddasp 4, 2, 0 +; CHECK-P8-NEXT: xsmulsp 0, 3, 4 ; CHECK-P8-NEXT: xsmulsp 1, 1, 0 ; CHECK-P8-NEXT: blr ; @@ -398,9 +398,9 @@ ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsrsqrtesp 0, 1 ; CHECK-P8-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI10_1@toc@ha ; CHECK-P8-NEXT: lfs 4, .LCPI10_0@toc@l(3) -; CHECK-P8-NEXT: lfs 5, .LCPI10_1@toc@l(4) +; CHECK-P8-NEXT: addis 3, 2, .LCPI10_1@toc@ha +; CHECK-P8-NEXT: lfs 5, .LCPI10_1@toc@l(3) ; CHECK-P8-NEXT: xsmulsp 1, 1, 0 ; CHECK-P8-NEXT: xsmaddasp 4, 1, 0 ; CHECK-P8-NEXT: xsmulsp 0, 0, 5 @@ -502,12 +502,12 @@ ; CHECK-P9-NEXT: xvrsqrtesp 0, 35 ; CHECK-P9-NEXT: addis 3, 2, .LCPI12_0@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI12_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 +; CHECK-P9-NEXT: lxv 2, 0(3) ; CHECK-P9-NEXT: addis 3, 2, .LCPI12_1@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI12_1@toc@l ; CHECK-P9-NEXT: xvmulsp 1, 35, 0 ; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 -; CHECK-P9-NEXT: lxvx 1, 0, 3 +; CHECK-P9-NEXT: lxv 1, 0(3) ; CHECK-P9-NEXT: xvmulsp 0, 0, 1 ; CHECK-P9-NEXT: xvmulsp 0, 0, 2 ; CHECK-P9-NEXT: xvmulsp 34, 34, 0 @@ -959,9 +959,9 @@ ; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: xsrsqrtesp 0, 1 ; CHECK-P8-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; CHECK-P8-NEXT: addis 4, 2, .LCPI23_1@toc@ha ; CHECK-P8-NEXT: lfs 2, .LCPI23_0@toc@l(3) -; CHECK-P8-NEXT: lfs 3, .LCPI23_1@toc@l(4) +; CHECK-P8-NEXT: addis 3, 2, .LCPI23_1@toc@ha +; CHECK-P8-NEXT: lfs 3, .LCPI23_1@toc@l(3) ; CHECK-P8-NEXT: xsmulsp 1, 1, 0 ; CHECK-P8-NEXT: xsmaddasp 2, 1, 0 ; CHECK-P8-NEXT: xsmulsp 0, 1, 3 @@ -1064,12 +1064,12 @@ ; CHECK-P9-NEXT: xvrsqrtesp 0, 34 ; CHECK-P9-NEXT: addis 3, 2, .LCPI25_0@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI25_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 +; CHECK-P9-NEXT: lxv 2, 0(3) ; CHECK-P9-NEXT: addis 3, 2, .LCPI25_1@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI25_1@toc@l ; CHECK-P9-NEXT: xvmulsp 1, 34, 0 ; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 -; CHECK-P9-NEXT: lxvx 0, 0, 3 +; CHECK-P9-NEXT: lxv 0, 0(3) ; CHECK-P9-NEXT: xvmulsp 0, 1, 0 ; CHECK-P9-NEXT: xvmulsp 34, 0, 2 ; CHECK-P9-NEXT: blr @@ -1190,13 +1190,13 @@ ; CHECK-P9-NEXT: xvrsqrtedp 0, 34 ; CHECK-P9-NEXT: addis 3, 2, .LCPI27_0@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI27_0@toc@l -; CHECK-P9-NEXT: lxvx 2, 0, 3 +; CHECK-P9-NEXT: lxv 2, 0(3) ; CHECK-P9-NEXT: addis 3, 2, .LCPI27_1@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI27_1@toc@l ; CHECK-P9-NEXT: xvmuldp 1, 34, 0 ; CHECK-P9-NEXT: xxlor 3, 2, 2 ; CHECK-P9-NEXT: xvmaddadp 3, 1, 0 -; CHECK-P9-NEXT: lxvx 1, 0, 3 +; CHECK-P9-NEXT: lxv 1, 0(3) ; CHECK-P9-NEXT: xvmuldp 0, 0, 1 ; CHECK-P9-NEXT: xvmuldp 0, 0, 3 ; CHECK-P9-NEXT: xvmuldp 3, 34, 0 diff --git a/llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll b/llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll --- a/llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll +++ b/llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll @@ -100,15 +100,15 @@ ; CHECK-P8: # %bb.0: ; CHECK-P8-NEXT: xsmulsp f1, f2, f1 ; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha -; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P8-NEXT: xssubsp f0, f3, f4 ; CHECK-P8-NEXT: lfs f3, .LCPI2_0@toc@l(r3) -; CHECK-P8-NEXT: lfs f4, .LCPI2_1@toc@l(r4) +; CHECK-P8-NEXT: addis r3, r2, .LCPI2_1@toc@ha +; CHECK-P8-NEXT: lfs f4, .LCPI2_1@toc@l(r3) ; CHECK-P8-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-P8-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-P8-NEXT: xsmaddasp f1, f0, f3 ; CHECK-P8-NEXT: xsmulsp f0, f2, f4 -; CHECK-P8-NEXT: stfsx f0, 0, r3 +; CHECK-P8-NEXT: stfs f0, 0(r3) ; CHECK-P8-NEXT: blr ; ; CHECK-FMA-LABEL: foo_float_reuse_const: diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll --- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll +++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll @@ -131,7 +131,7 @@ ; P8BE-LABEL: s2v_test_f1: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: lfdx f0, 0, r3 +; P8BE-NEXT: lfd f0, 0(r3) ; P8BE-NEXT: xxpermdi v2, vs0, v2, 1 ; P8BE-NEXT: blr entry: @@ -263,7 +263,7 @@ ; P8BE-LABEL: s2v_test_f5: ; P8BE: # %bb.0: # %entry -; P8BE-NEXT: lfdx f0, 0, r5 +; P8BE-NEXT: lfd f0, 0(r5) ; P8BE-NEXT: xxpermdi v2, vs0, v2, 1 ; P8BE-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll --- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll +++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll @@ -27,18 +27,18 @@ ; ; P8LE-LABEL: test_liwzx1: ; P8LE: # %bb.0: -; P8LE-NEXT: lfsx f0, 0, r3 -; P8LE-NEXT: lfsx f1, 0, r4 +; P8LE-NEXT: lfs f0, 0(r3) +; P8LE-NEXT: lfs f1, 0(r4) ; P8LE-NEXT: xsaddsp f0, f0, f1 -; P8LE-NEXT: stfsx f0, 0, r5 +; P8LE-NEXT: stfs f0, 0(r5) ; P8LE-NEXT: blr ; ; P8BE-LABEL: test_liwzx1: ; P8BE: # %bb.0: -; P8BE-NEXT: lfsx f0, 0, r3 -; P8BE-NEXT: lfsx f1, 0, r4 +; P8BE-NEXT: lfs f0, 0(r3) +; P8BE-NEXT: lfs f1, 0(r4) ; P8BE-NEXT: xsaddsp f0, f0, f1 -; P8BE-NEXT: stfsx f0, 0, r5 +; P8BE-NEXT: stfs f0, 0(r5) ; P8BE-NEXT: blr @@ -71,20 +71,20 @@ ; ; P8LE-LABEL: test_liwzx2: ; P8LE: # %bb.0: -; P8LE-NEXT: lfsx f0, 0, r3 -; P8LE-NEXT: lfsx f1, 0, r4 +; P8LE-NEXT: lfs f0, 0(r3) +; P8LE-NEXT: lfs f1, 0(r4) ; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: xssubsp f0, f0, f1 -; P8LE-NEXT: stfsx f0, 0, r5 +; P8LE-NEXT: stfs f0, 0(r5) ; P8LE-NEXT: blr ; ; P8BE-LABEL: test_liwzx2: ; P8BE: # %bb.0: -; P8BE-NEXT: lfsx f0, 0, r3 -; P8BE-NEXT: lfsx f1, 0, r4 +; P8BE-NEXT: lfs f0, 0(r3) +; P8BE-NEXT: lfs f1, 0(r4) ; P8BE-NEXT: mr r3, r5 ; P8BE-NEXT: xssubsp f0, f0, f1 -; P8BE-NEXT: stfsx f0, 0, r5 +; P8BE-NEXT: stfs f0, 0(r5) ; P8BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/select_const.ll b/llvm/test/CodeGen/PowerPC/select_const.ll --- a/llvm/test/CodeGen/PowerPC/select_const.ll +++ b/llvm/test/CodeGen/PowerPC/select_const.ll @@ -726,7 +726,7 @@ ; ISEL-NEXT: addi 4, 4, .LCPI42_0@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI42_1@toc@l ; ISEL-NEXT: iselgt 3, 3, 4 -; ISEL-NEXT: lfdx 1, 0, 3 +; ISEL-NEXT: lfd 1, 0(3) ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fadd_constant: @@ -741,7 +741,7 @@ ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB42_2 ; NO_ISEL-NEXT: .LBB42_2: -; NO_ISEL-NEXT: lfdx 1, 0, 3 +; NO_ISEL-NEXT: lfd 1, 0(3) ; NO_ISEL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = fadd double %sel, 5.1 @@ -757,7 +757,7 @@ ; ISEL-NEXT: addi 4, 4, .LCPI43_0@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI43_1@toc@l ; ISEL-NEXT: iselgt 3, 3, 4 -; ISEL-NEXT: lfdx 1, 0, 3 +; ISEL-NEXT: lfd 1, 0(3) ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fsub_constant: @@ -772,7 +772,7 @@ ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB43_2 ; NO_ISEL-NEXT: .LBB43_2: -; NO_ISEL-NEXT: lfdx 1, 0, 3 +; NO_ISEL-NEXT: lfd 1, 0(3) ; NO_ISEL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = fsub double %sel, 5.1 @@ -788,7 +788,7 @@ ; ISEL-NEXT: addi 4, 4, .LCPI44_0@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI44_1@toc@l ; ISEL-NEXT: iselgt 3, 3, 4 -; ISEL-NEXT: lfdx 1, 0, 3 +; ISEL-NEXT: lfd 1, 0(3) ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: fsub_constant_sel_constants: @@ -803,7 +803,7 @@ ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB44_2 ; NO_ISEL-NEXT: .LBB44_2: -; NO_ISEL-NEXT: lfdx 1, 0, 3 +; NO_ISEL-NEXT: lfd 1, 0(3) ; NO_ISEL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = fsub double 5.1, %sel @@ -819,7 +819,7 @@ ; ISEL-NEXT: addi 4, 4, .LCPI45_0@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI45_1@toc@l ; ISEL-NEXT: iselgt 3, 3, 4 -; ISEL-NEXT: lfdx 1, 0, 3 +; ISEL-NEXT: lfd 1, 0(3) ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fmul_constant: @@ -834,7 +834,7 @@ ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB45_2 ; NO_ISEL-NEXT: .LBB45_2: -; NO_ISEL-NEXT: lfdx 1, 0, 3 +; NO_ISEL-NEXT: lfd 1, 0(3) ; NO_ISEL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = fmul double %sel, 5.1 @@ -850,7 +850,7 @@ ; ISEL-NEXT: addi 4, 4, .LCPI46_0@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI46_1@toc@l ; ISEL-NEXT: iselgt 3, 3, 4 -; ISEL-NEXT: lfdx 1, 0, 3 +; ISEL-NEXT: lfd 1, 0(3) ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fdiv_constant: @@ -865,7 +865,7 @@ ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB46_2 ; NO_ISEL-NEXT: .LBB46_2: -; NO_ISEL-NEXT: lfdx 1, 0, 3 +; NO_ISEL-NEXT: lfd 1, 0(3) ; NO_ISEL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = fdiv double %sel, 5.1 @@ -881,7 +881,7 @@ ; ISEL-NEXT: addi 4, 4, .LCPI47_0@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI47_1@toc@l ; ISEL-NEXT: iselgt 3, 3, 4 -; ISEL-NEXT: lfdx 1, 0, 3 +; ISEL-NEXT: lfd 1, 0(3) ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: fdiv_constant_sel_constants: @@ -896,7 +896,7 @@ ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB47_2 ; NO_ISEL-NEXT: .LBB47_2: -; NO_ISEL-NEXT: lfdx 1, 0, 3 +; NO_ISEL-NEXT: lfd 1, 0(3) ; NO_ISEL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = fdiv double 5.1, %sel @@ -930,7 +930,7 @@ ; ISEL-NEXT: addi 4, 4, .LCPI49_0@toc@l ; ISEL-NEXT: addi 3, 3, .LCPI49_1@toc@l ; ISEL-NEXT: iselgt 3, 3, 4 -; ISEL-NEXT: lfdx 1, 0, 3 +; ISEL-NEXT: lfd 1, 0(3) ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: frem_constant_sel_constants: @@ -945,7 +945,7 @@ ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB49_2 ; NO_ISEL-NEXT: .LBB49_2: -; NO_ISEL-NEXT: lfdx 1, 0, 3 +; NO_ISEL-NEXT: lfd 1, 0(3) ; NO_ISEL-NEXT: blr %sel = select i1 %cond, double -4.0, double 23.3 %bo = frem double 5.1, %sel diff --git a/llvm/test/CodeGen/PowerPC/store_fptoi.ll b/llvm/test/CodeGen/PowerPC/store_fptoi.ll --- a/llvm/test/CodeGen/PowerPC/store_fptoi.ll +++ b/llvm/test/CodeGen/PowerPC/store_fptoi.ll @@ -179,7 +179,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2sdw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 ; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 ; CHECK-PWR8-NEXT: blr @@ -203,7 +203,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2sw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 ; CHECK-PWR8-NEXT: blr @@ -227,7 +227,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2shw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: sth 3, 0(4) @@ -252,7 +252,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2sb: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: stb 3, 0(4) @@ -277,7 +277,7 @@ ; ; CHECK-PWR8-LABEL: spConv2sdw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 ; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 ; CHECK-PWR8-NEXT: blr @@ -301,7 +301,7 @@ ; ; CHECK-PWR8-LABEL: spConv2sw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 ; CHECK-PWR8-NEXT: blr @@ -325,7 +325,7 @@ ; ; CHECK-PWR8-LABEL: spConv2shw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: sth 3, 0(4) @@ -350,7 +350,7 @@ ; ; CHECK-PWR8-LABEL: spConv2sb: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: stb 3, 0(4) @@ -376,7 +376,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2sdw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: sldi 3, 5, 3 ; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 ; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 @@ -405,7 +405,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2sw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: sldi 3, 5, 2 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 @@ -434,7 +434,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2shw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: sldi 5, 5, 1 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 @@ -463,7 +463,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2sb_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: stbx 3, 4, 5 @@ -492,7 +492,7 @@ ; ; CHECK-PWR8-LABEL: spConv2sdw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: sldi 3, 5, 3 ; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 ; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 @@ -521,7 +521,7 @@ ; ; CHECK-PWR8-LABEL: spConv2sw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: sldi 3, 5, 2 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 @@ -550,7 +550,7 @@ ; ; CHECK-PWR8-LABEL: spConv2shw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: sldi 5, 5, 1 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 @@ -579,7 +579,7 @@ ; ; CHECK-PWR8-LABEL: spConv2sb_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: stbx 3, 4, 5 @@ -611,7 +611,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2udw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 ; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 ; CHECK-PWR8-NEXT: blr @@ -635,7 +635,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2uw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 ; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 ; CHECK-PWR8-NEXT: blr @@ -659,7 +659,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2uhw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: sth 3, 0(4) @@ -684,7 +684,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2ub: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: stb 3, 0(4) @@ -709,7 +709,7 @@ ; ; CHECK-PWR8-LABEL: spConv2udw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 ; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 ; CHECK-PWR8-NEXT: blr @@ -733,7 +733,7 @@ ; ; CHECK-PWR8-LABEL: spConv2uw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 ; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 ; CHECK-PWR8-NEXT: blr @@ -757,7 +757,7 @@ ; ; CHECK-PWR8-LABEL: spConv2uhw: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: sth 3, 0(4) @@ -782,7 +782,7 @@ ; ; CHECK-PWR8-LABEL: spConv2ub: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: stb 3, 0(4) @@ -808,7 +808,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2udw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: sldi 3, 5, 3 ; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 ; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 @@ -837,7 +837,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2uw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: sldi 3, 5, 2 ; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 ; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 @@ -866,7 +866,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2uhw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: sldi 5, 5, 1 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 @@ -895,7 +895,7 @@ ; ; CHECK-PWR8-LABEL: dpConv2ub_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: lfd 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: stbx 3, 4, 5 @@ -924,7 +924,7 @@ ; ; CHECK-PWR8-LABEL: spConv2udw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: sldi 3, 5, 3 ; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 ; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 @@ -953,7 +953,7 @@ ; ; CHECK-PWR8-LABEL: spConv2uw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: sldi 3, 5, 2 ; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 ; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 @@ -982,7 +982,7 @@ ; ; CHECK-PWR8-LABEL: spConv2uhw_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: sldi 5, 5, 1 ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 @@ -1011,7 +1011,7 @@ ; ; CHECK-PWR8-LABEL: spConv2ub_x: ; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: lfs 0, 0(3) ; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 ; CHECK-PWR8-NEXT: mffprwz 3, 0 ; CHECK-PWR8-NEXT: stbx 3, 4, 5 diff --git a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll --- a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll +++ b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll @@ -46,7 +46,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: addis r3, r2, .LC0@toc@ha ; CHECK-P9: ld r3, .LC0@toc@l(r3) -; CHECK-P9: lxvx vs0, 0, r3 +; CHECK-P9: lxv vs0, 0(r3) ; CHECK-P9: addis r3, r2, .LC1@toc@ha ; CHECK-P9: ld r3, .LC1@toc@l(r3) ; CHECK-P9: lfd f1, 0(r3) @@ -54,7 +54,7 @@ ; CHECK-P9: ld r3, .LC2@toc@l(r3) ; CHECK-P9: xxswapd vs1, f1 ; CHECK-P9: xxpermdi vs0, vs0, vs1, 1 -; CHECK-P9: stxvx vs0, 0, r3 +; CHECK-P9: stxv vs0, 0(r3) ; CHECK-P9: blr entry: %0 = load <2 x double>, <2 x double>* @x, align 16 @@ -91,7 +91,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: addis r3, r2, .LC0@toc@ha ; CHECK-P9: ld r3, .LC0@toc@l(r3) -; CHECK-P9: lxvx vs0, 0, r3 +; CHECK-P9: lxv vs0, 0(r3) ; CHECK-P9: addis r3, r2, .LC1@toc@ha ; CHECK-P9: ld r3, .LC1@toc@l(r3) ; CHECK-P9: lfd f1, 0(r3) @@ -99,7 +99,7 @@ ; CHECK-P9: ld r3, .LC2@toc@l(r3) ; CHECK-P9: xxswapd vs1, f1 ; CHECK-P9: xxmrgld vs0, vs1, vs0 -; CHECK-P9: stxvx vs0, 0, r3 +; CHECK-P9: stxv vs0, 0(r3) ; CHECK-P9: blr entry: %0 = load <2 x double>, <2 x double>* @x, align 16 diff --git a/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll b/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll --- a/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll +++ b/llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll @@ -23,7 +23,7 @@ ; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: bl callee -; CHECK-NEXT: stfdx f1, 0, r30 +; CHECK-NEXT: stfd f1, 0(r30) ; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -45,7 +45,7 @@ ; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: bl callee - ; CHECK-NEXT: stfdx f1, 0, r30 + ; CHECK-NEXT: stfd f1, 0(r30) ; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/PowerPC/toc-float.ll b/llvm/test/CodeGen/PowerPC/toc-float.ll --- a/llvm/test/CodeGen/PowerPC/toc-float.ll +++ b/llvm/test/CodeGen/PowerPC/toc-float.ll @@ -50,11 +50,10 @@ ; ; CHECK-P8-LABEL: floatConstantArray: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, FArr@toc@ha +; CHECK-P8-NEXT: addis 3, 2, FArr@toc@ha+12 ; CHECK-P8-NEXT: addis 4, 2, .LCPI2_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, FArr@toc@l +; CHECK-P8-NEXT: lfs 0, FArr@toc@l+12(3) ; CHECK-P8-NEXT: lfs 1, .LCPI2_0@toc@l(4) -; CHECK-P8-NEXT: lfs 0, 12(3) ; CHECK-P8-NEXT: xsaddsp 1, 0, 1 ; CHECK-P8-NEXT: blr %1 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* @FArr, i64 0, i64 3), align 4 @@ -93,11 +92,10 @@ ; ; CHECK-P8-LABEL: doubleConstantArray: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, d@toc@ha +; CHECK-P8-NEXT: addis 3, 2, d@toc@ha+24 ; CHECK-P8-NEXT: addis 4, 2, .LCPI4_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, d@toc@l +; CHECK-P8-NEXT: lfd 0, d@toc@l+24(3) ; CHECK-P8-NEXT: lfd 1, .LCPI4_0@toc@l(4) -; CHECK-P8-NEXT: lfd 0, 24(3) ; CHECK-P8-NEXT: xsadddp 1, 0, 1 ; CHECK-P8-NEXT: blr %1 = load double, double* getelementptr inbounds ([200 x double], [200 x double]* @d, i64 0, i64 3), align 8 @@ -128,8 +126,8 @@ ; CHECK-P8-NEXT: addis 5, 2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addi 3, 3, arr@toc@l ; CHECK-P8-NEXT: ori 4, 4, 32768 -; CHECK-P8-NEXT: lfdx 0, 3, 4 ; CHECK-P8-NEXT: lfd 1, .LCPI5_0@toc@l(5) +; CHECK-P8-NEXT: lfdx 0, 3, 4 ; CHECK-P8-NEXT: xsadddp 1, 0, 1 ; CHECK-P8-NEXT: blr %1 = load double, double* getelementptr inbounds ([20000 x double], [20000 x double]* @arr, i64 0, i64 4096), align 8 diff --git a/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll b/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll --- a/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll +++ b/llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll @@ -55,10 +55,10 @@ define void @test_xoaddr(i32* %arr, i32* %arrTo) { ; CHECK-LABEL: test_xoaddr: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi r3, r3, 8 -; CHECK-NEXT: addi r4, r4, 4 -; CHECK-NEXT: lxvx vs0, 0, r3 -; CHECK-NEXT: stxvx vs0, 0, r4 +; CHECK-NEXT: li r5, 8 +; CHECK-NEXT: lxvx vs0, r3, r5 +; CHECK-NEXT: li r3, 4 +; CHECK-NEXT: stxvx vs0, r4, r3 ; CHECK-NEXT: blr entry: %arrayidx = getelementptr inbounds i32, i32* %arrTo, i64 1 diff --git a/llvm/test/CodeGen/PowerPC/unaligned.ll b/llvm/test/CodeGen/PowerPC/unaligned.ll --- a/llvm/test/CodeGen/PowerPC/unaligned.ll +++ b/llvm/test/CodeGen/PowerPC/unaligned.ll @@ -92,8 +92,8 @@ ; ; CHECK-VSX-LABEL: foo5: ; CHECK-VSX: # %bb.0: # %entry -; CHECK-VSX-NEXT: lfdx 0, 0, 3 -; CHECK-VSX-NEXT: stfdx 0, 0, 4 +; CHECK-VSX-NEXT: lfd 0, 0(3) +; CHECK-VSX-NEXT: stfd 0, 0(4) ; CHECK-VSX-NEXT: blr entry: %v = load double, double* %p, align 1 diff --git a/llvm/test/CodeGen/PowerPC/vavg.ll b/llvm/test/CodeGen/PowerPC/vavg.ll --- a/llvm/test/CodeGen/PowerPC/vavg.ll +++ b/llvm/test/CodeGen/PowerPC/vavg.ll @@ -140,7 +140,7 @@ ; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx 35, 0, 3 +; CHECK-P9-NEXT: lxv 35, 0(3) ; CHECK-P9-NEXT: vadduhm 2, 2, 3 ; CHECK-P9-NEXT: vspltish 3, 1 ; CHECK-P9-NEXT: vsrah 2, 2, 3 diff --git a/llvm/test/CodeGen/PowerPC/vec-itofp.ll b/llvm/test/CodeGen/PowerPC/vec-itofp.ll --- a/llvm/test/CodeGen/PowerPC/vec-itofp.ll +++ b/llvm/test/CodeGen/PowerPC/vec-itofp.ll @@ -53,24 +53,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI0_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v2 @@ -83,24 +83,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI0_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI0_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v2 @@ -141,12 +141,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v2 @@ -159,12 +159,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v2 @@ -197,7 +197,7 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v2 ; CHECK-P9-NEXT: stxv vs0, 0(r3) @@ -209,7 +209,7 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v2 ; CHECK-BE-NEXT: stxv vs0, 0(r3) @@ -275,27 +275,27 @@ ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -309,27 +309,27 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -377,13 +377,13 @@ ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI4_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -397,13 +397,13 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -441,7 +441,7 @@ ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp vs0, v2 @@ -453,7 +453,7 @@ ; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp vs0, v2 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll @@ -100,7 +100,7 @@ ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: blr @@ -139,12 +139,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 @@ -192,12 +192,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v4, 0, r4 +; CHECK-P9-NEXT: lxv v4, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v0 -; CHECK-P9-NEXT: lxvx v0, 0, r4 +; CHECK-P9-NEXT: lxv v0, 0(r4) ; CHECK-P9-NEXT: vperm v3, v5, v3, v0 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 @@ -217,12 +217,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v0 -; CHECK-BE-NEXT: lxvx v0, 0, r4 +; CHECK-BE-NEXT: lxv v0, 0(r4) ; CHECK-BE-NEXT: vperm v3, v5, v3, v0 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 @@ -377,7 +377,7 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v2 ; CHECK-BE-NEXT: vextsh2w v3, v3 @@ -454,7 +454,7 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: vperm v0, v5, v3, v4 ; CHECK-BE-NEXT: vperm v4, v5, v2, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v3 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll @@ -27,7 +27,7 @@ ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: blr @@ -38,7 +38,7 @@ ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: blr @@ -76,12 +76,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v2 @@ -94,12 +94,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v2 @@ -154,24 +154,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v2 @@ -183,24 +183,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v2 @@ -278,24 +278,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: xxlxor v5, v5, v5 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v4, 0, r4 +; CHECK-P9-NEXT: lxv v4, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v0, v5, v3, v4 ; CHECK-P9-NEXT: xvcvuxddp vs0, v0 -; CHECK-P9-NEXT: lxvx v0, 0, r4 +; CHECK-P9-NEXT: lxv v0, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: vperm v1, v5, v3, v0 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v1 -; CHECK-P9-NEXT: lxvx v1, 0, r4 +; CHECK-P9-NEXT: lxv v1, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: vperm v6, v5, v3, v1 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v6 -; CHECK-P9-NEXT: lxvx v6, 0, r4 +; CHECK-P9-NEXT: lxv v6, 0(r4) ; CHECK-P9-NEXT: vperm v3, v5, v3, v6 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v3 @@ -321,24 +321,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v5, v5, v5 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v0, v3, v5, v4 ; CHECK-BE-NEXT: xvcvuxddp vs0, v0 -; CHECK-BE-NEXT: lxvx v0, 0, r4 +; CHECK-BE-NEXT: lxv v0, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: vperm v1, v5, v3, v0 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v1 -; CHECK-BE-NEXT: lxvx v1, 0, r4 +; CHECK-BE-NEXT: lxv v1, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v6, v5, v3, v1 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v6 -; CHECK-BE-NEXT: lxvx v6, 0, r4 +; CHECK-BE-NEXT: lxv v6, 0(r4) ; CHECK-BE-NEXT: vperm v3, v5, v3, v6 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v3 @@ -385,7 +385,7 @@ ; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2 @@ -396,7 +396,7 @@ ; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2 @@ -441,13 +441,13 @@ ; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -461,13 +461,13 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -533,27 +533,27 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsh2d v2, v2 @@ -566,27 +566,27 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -682,20 +682,20 @@ ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r5 +; CHECK-P9-NEXT: lxv v3, 0(r5) ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l -; CHECK-P9-NEXT: lxvx v5, 0, r5 +; CHECK-P9-NEXT: lxv v5, 0(r5) ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: vperm v4, v2, v2, v3 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l ; CHECK-P9-NEXT: vextsh2d v4, v4 -; CHECK-P9-NEXT: lxvx v0, 0, r5 +; CHECK-P9-NEXT: lxv v0, 0(r5) ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: xvcvsxddp vs0, v4 ; CHECK-P9-NEXT: vperm v4, v2, v2, v5 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l -; CHECK-P9-NEXT: lxvx v1, 0, r5 +; CHECK-P9-NEXT: lxv v1, 0(r5) ; CHECK-P9-NEXT: vextsh2d v4, v4 ; CHECK-P9-NEXT: xvcvsxddp vs1, v4 ; CHECK-P9-NEXT: vperm v4, v2, v2, v0 @@ -736,10 +736,10 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l -; CHECK-BE-NEXT: lxvx v2, 0, r5 +; CHECK-BE-NEXT: lxv v2, 0(r5) ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r5 +; CHECK-BE-NEXT: lxv v3, 0(r5) ; CHECK-BE-NEXT: vperm v0, v5, v4, v2 ; CHECK-BE-NEXT: vperm v2, v5, v1, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2 @@ -751,7 +751,7 @@ ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v0, v0 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2 -; CHECK-BE-NEXT: lxvx v2, 0, r4 +; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: xvcvsxddp vs1, v0 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l @@ -764,7 +764,7 @@ ; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: xvcvsxddp vs6, v2 ; CHECK-BE-NEXT: vperm v4, v4, v4, v3 ; CHECK-BE-NEXT: vperm v2, v1, v1, v3 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll @@ -95,7 +95,7 @@ ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2 ; CHECK-P9-NEXT: blr @@ -106,7 +106,7 @@ ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp v2, v2 ; CHECK-BE-NEXT: blr @@ -142,12 +142,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs1, v2 @@ -160,12 +160,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v2 @@ -216,24 +216,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxwsp vs3, v2 @@ -245,24 +245,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxwsp vs3, v2 @@ -362,7 +362,7 @@ ; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2 @@ -373,7 +373,7 @@ ; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: xvcvsxwsp v2, v2 @@ -414,13 +414,13 @@ ; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2w v2, v2 @@ -434,13 +434,13 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2w v2, v2 @@ -500,27 +500,27 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: xvcvsxwsp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsb2w v2, v2 @@ -533,27 +533,27 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsb2w v2, v2 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll @@ -27,7 +27,7 @@ ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp v2, v2 ; CHECK-P9-NEXT: blr @@ -38,7 +38,7 @@ ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp v2, v2 ; CHECK-BE-NEXT: blr @@ -76,12 +76,12 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v2 @@ -94,12 +94,12 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v2 @@ -156,24 +156,24 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v2 @@ -186,24 +186,24 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v2 @@ -290,48 +290,48 @@ ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: xvcvuxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: xvcvuxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_4@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_4@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: xvcvuxddp vs3, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_5@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_5@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: xvcvuxddp vs4, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_6@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_6@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: xvcvuxddp vs5, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_7@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_7@toc@l ; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: xvcvuxddp vs6, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: xvcvuxddp vs7, v2 @@ -343,48 +343,48 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v4, v3 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 0(r3) ; CHECK-BE-NEXT: xvcvuxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 16(r3) ; CHECK-BE-NEXT: xvcvuxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_4@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_4@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 32(r3) ; CHECK-BE-NEXT: xvcvuxddp vs3, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_5@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_5@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs3, 48(r3) ; CHECK-BE-NEXT: xvcvuxddp vs4, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_6@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_6@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs4, 64(r3) ; CHECK-BE-NEXT: xvcvuxddp vs5, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_7@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_7@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs5, 80(r3) ; CHECK-BE-NEXT: xvcvuxddp vs6, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs6, 96(r3) ; CHECK-BE-NEXT: xvcvuxddp vs7, v2 @@ -418,7 +418,7 @@ ; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r3 +; CHECK-P9-NEXT: lxv v3, 0(r3) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2 @@ -429,7 +429,7 @@ ; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r3 +; CHECK-BE-NEXT: lxv v3, 0(r3) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2 @@ -474,13 +474,13 @@ ; CHECK-P9-NEXT: mtvsrws v2, r4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -494,13 +494,13 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 @@ -568,27 +568,27 @@ ; CHECK-P9-NEXT: mtvsrd v2, r4 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -602,27 +602,27 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: xxlxor v4, v4, v4 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 @@ -728,55 +728,55 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_4@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_4@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs2, 32(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs3, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_5@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_5@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs4, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_6@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs4, 64(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs5, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_7@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_7@toc@l ; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs5, 80(r3) ; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3 -; CHECK-P9-NEXT: lxvx v3, 0, r4 +; CHECK-P9-NEXT: lxv v3, 0(r4) ; CHECK-P9-NEXT: vperm v2, v2, v2, v3 ; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: vextsb2d v2, v2 @@ -789,55 +789,55 @@ ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: xxlxor v3, v3, v3 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs0, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs1, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: xvcvsxddp vs2, v4 -; CHECK-BE-NEXT: lxvx v4, 0, r4 +; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l ; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs3, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs5, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l ; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3 -; CHECK-BE-NEXT: lxvx v3, 0, r4 +; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: stxv vs6, 64(r3) ; CHECK-BE-NEXT: vextsb2d v2, v2 diff --git a/llvm/test/CodeGen/PowerPC/vec_int_ext.ll b/llvm/test/CodeGen/PowerPC/vec_int_ext.ll --- a/llvm/test/CodeGen/PowerPC/vec_int_ext.ll +++ b/llvm/test/CodeGen/PowerPC/vec_int_ext.ll @@ -12,7 +12,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsb2w 2, 2 ; CHECK-BE-NEXT: blr @@ -43,7 +43,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsb2d 2, 2 ; CHECK-BE-NEXT: blr @@ -68,7 +68,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsh2w 2, 2 ; CHECK-BE-NEXT: blr @@ -99,7 +99,7 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: lxv 35, 0(3) ; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsh2d 2, 2 ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll --- a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll +++ b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll @@ -47,10 +47,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI1_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI1_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI1_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvdivdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -67,16 +67,16 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI2_3@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI2_2@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI2_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI2_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI2_3@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI2_2@toc@l(5) +; PC64LE-NEXT: lfs 2, .LCPI2_2@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PC64LE-NEXT: xsdivsp 1, 1, 0 ; PC64LE-NEXT: lfs 3, .LCPI2_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI2_4@toc@ha -; PC64LE-NEXT: xsdivsp 2, 2, 0 +; PC64LE-NEXT: xsdivsp 1, 1, 0 ; PC64LE-NEXT: addi 3, 3, .LCPI2_4@toc@l +; PC64LE-NEXT: xsdivsp 2, 2, 0 ; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xsdivsp 0, 3, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 @@ -102,7 +102,7 @@ ; PC64LE9-NEXT: lfs 3, .LCPI2_3@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI2_4@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI2_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsdivsp 2, 2, 0 ; PC64LE9-NEXT: xsdivsp 0, 3, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0 @@ -154,10 +154,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI3_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI3_2@toc@l ; PC64LE9-NEXT: xsdivdp 3, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI3_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI3_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvdivdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -195,14 +195,14 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI4_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI4_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI4_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI4_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI4_2@toc@l ; PC64LE9-NEXT: xvdivdp 35, 1, 0 -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvdivdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -272,8 +272,8 @@ ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI6_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI6_2@toc@l(3) @@ -342,14 +342,14 @@ ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI7_2@toc@ha ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: addis 3, 2, .LCPI7_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: lfs 1, .LCPI7_2@toc@l(3) ; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI7_3@toc@ha ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: addis 3, 2, .LCPI7_3@toc@ha ; PC64LE-NEXT: fmr 29, 1 ; PC64LE-NEXT: lfs 1, .LCPI7_3@toc@l(3) ; PC64LE-NEXT: bl fmodf @@ -403,7 +403,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -436,16 +436,16 @@ ; PC64LE-NEXT: addis 4, 2, .LCPI8_1@toc@ha ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: lfs 31, .LCPI8_1@toc@l(4) ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI8_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI8_0@toc@l(3) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI8_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI8_2@toc@l(3) @@ -529,16 +529,16 @@ ; PC64LE-NEXT: addis 4, 2, .LCPI9_1@toc@ha ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: lfs 31, .LCPI9_1@toc@l(4) ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI9_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI9_0@toc@l(3) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI9_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI9_2@toc@l(3) @@ -554,8 +554,8 @@ ; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI9_4@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI9_4@toc@l(3) @@ -675,10 +675,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI11_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI11_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI11_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI11_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmuldp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -695,16 +695,16 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI12_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI12_3@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI12_2@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI12_1@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI12_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI12_3@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI12_2@toc@l(5) +; PC64LE-NEXT: lfs 2, .LCPI12_2@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; PC64LE-NEXT: xsmulsp 1, 0, 1 ; PC64LE-NEXT: lfs 3, .LCPI12_0@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI12_4@toc@ha -; PC64LE-NEXT: xsmulsp 2, 0, 2 +; PC64LE-NEXT: xsmulsp 1, 0, 1 ; PC64LE-NEXT: addi 3, 3, .LCPI12_4@toc@l +; PC64LE-NEXT: xsmulsp 2, 0, 2 ; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: xsmulsp 0, 0, 3 ; PC64LE-NEXT: xscvdpspn 1, 1 @@ -730,7 +730,7 @@ ; PC64LE9-NEXT: lfs 3, .LCPI12_3@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI12_4@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI12_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsmulsp 2, 1, 2 ; PC64LE9-NEXT: xsmulsp 1, 1, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 @@ -783,10 +783,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI13_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI13_2@toc@l ; PC64LE9-NEXT: xsmuldp 3, 0, 1 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI13_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI13_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmuldp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -825,14 +825,14 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI14_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI14_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI14_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI14_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI14_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI14_2@toc@l ; PC64LE9-NEXT: xvmuldp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvmuldp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -891,10 +891,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI16_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI16_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvadddp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -911,11 +911,11 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI17_2@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI17_1@toc@ha ; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: lfs 0, .LCPI17_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI17_1@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI17_2@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI17_1@toc@l(5) +; PC64LE-NEXT: lfs 2, .LCPI17_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI17_3@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI17_3@toc@l ; PC64LE-NEXT: xsaddsp 1, 0, 1 @@ -944,7 +944,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI17_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI17_3@toc@l ; PC64LE9-NEXT: xsaddsp 1, 0, 1 -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsaddsp 2, 0, 2 ; PC64LE9-NEXT: xsaddsp 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 @@ -995,10 +995,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI18_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI18_1@toc@l ; PC64LE9-NEXT: xsadddp 3, 0, 1 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI18_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI18_2@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvadddp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1037,14 +1037,14 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI19_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI19_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI19_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI19_2@toc@l ; PC64LE9-NEXT: xvadddp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvadddp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1103,10 +1103,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI21_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1123,11 +1123,11 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI22_2@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI22_1@toc@ha ; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: lfs 0, .LCPI22_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI22_1@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI22_2@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI22_1@toc@l(5) +; PC64LE-NEXT: lfs 2, .LCPI22_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI22_3@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI22_3@toc@l ; PC64LE-NEXT: xssubsp 1, 0, 1 @@ -1156,7 +1156,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI22_3@toc@l ; PC64LE9-NEXT: xssubsp 1, 0, 1 -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xssubsp 2, 0, 2 ; PC64LE9-NEXT: xssubsp 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 0 @@ -1207,10 +1207,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI23_1@toc@l ; PC64LE9-NEXT: xssubdp 3, 0, 1 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvsubdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1249,14 +1249,14 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI24_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI24_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI24_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI24_2@toc@l ; PC64LE9-NEXT: xvsubdp 35, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -1306,7 +1306,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI26_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI26_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvsqrtdp 34, 0 ; PC64LE9-NEXT: blr entry: @@ -1321,15 +1321,15 @@ ; PC64LE-LABEL: constrained_vector_sqrt_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI27_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI27_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI27_2@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI27_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LCPI27_1@toc@ha +; PC64LE-NEXT: lfs 1, .LCPI27_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PC64LE-NEXT: xssqrtsp 0, 0 ; PC64LE-NEXT: lfs 2, .LCPI27_0@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI27_3@toc@ha -; PC64LE-NEXT: xssqrtsp 1, 1 +; PC64LE-NEXT: xssqrtsp 0, 0 ; PC64LE-NEXT: addi 3, 3, .LCPI27_3@toc@l +; PC64LE-NEXT: xssqrtsp 1, 1 ; PC64LE-NEXT: xssqrtsp 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 @@ -1362,7 +1362,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: blr entry: @@ -1396,7 +1396,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI28_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI28_1@toc@l ; PC64LE9-NEXT: xssqrtdp 3, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvsqrtdp 2, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -1429,11 +1429,11 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI29_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI29_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI29_1@toc@l ; PC64LE9-NEXT: xvsqrtdp 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvsqrtdp 34, 0 ; PC64LE9-NEXT: blr entry: @@ -1501,8 +1501,8 @@ ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI31_2@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI31_2@toc@l(3) @@ -1571,14 +1571,14 @@ ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl powf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI32_2@toc@ha ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: addis 3, 2, .LCPI32_2@toc@ha ; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: lfs 1, .LCPI32_2@toc@l(3) ; PC64LE-NEXT: bl powf ; PC64LE-NEXT: nop -; PC64LE-NEXT: addis 3, 2, .LCPI32_3@toc@ha ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: addis 3, 2, .LCPI32_3@toc@ha ; PC64LE-NEXT: fmr 29, 1 ; PC64LE-NEXT: lfs 1, .LCPI32_3@toc@l(3) ; PC64LE-NEXT: bl powf @@ -1632,7 +1632,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -1665,16 +1665,16 @@ ; PC64LE-NEXT: addis 4, 2, .LCPI33_1@toc@ha ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: lfs 31, .LCPI33_1@toc@l(4) ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI33_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI33_0@toc@l(3) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI33_2@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI33_2@toc@l(3) @@ -1758,16 +1758,16 @@ ; PC64LE-NEXT: addis 4, 2, .LCPI34_1@toc@ha ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: li 3, 64 +; PC64LE-NEXT: lfs 31, .LCPI34_1@toc@l(4) ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PC64LE-NEXT: lfs 31, .LCPI34_1@toc@l(4) ; PC64LE-NEXT: lfd 1, .LCPI34_0@toc@l(3) ; PC64LE-NEXT: fmr 2, 31 ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI34_2@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI34_2@toc@l(3) @@ -1783,8 +1783,8 @@ ; PC64LE-NEXT: bl pow ; PC64LE-NEXT: nop ; PC64LE-NEXT: li 3, 48 -; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: fmr 2, 31 +; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: stxvd2x 1, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: addis 3, 2, .LCPI34_4@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI34_4@toc@l(3) @@ -2032,7 +2032,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 30 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -2403,7 +2403,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -2752,7 +2752,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -3101,7 +3101,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -3450,7 +3450,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -3799,7 +3799,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -4148,7 +4148,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -4497,7 +4497,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -4721,7 +4721,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI76_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI76_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvrdpic 34, 0 ; PC64LE9-NEXT: blr entry: @@ -4736,15 +4736,15 @@ ; PC64LE-LABEL: constrained_vector_rint_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI77_2@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI77_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI77_2@toc@l(3) -; PC64LE-NEXT: lfs 1, .LCPI77_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LCPI77_1@toc@ha +; PC64LE-NEXT: lfs 1, .LCPI77_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI77_0@toc@ha -; PC64LE-NEXT: xsrdpic 0, 0 ; PC64LE-NEXT: lfs 2, .LCPI77_0@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI77_3@toc@ha -; PC64LE-NEXT: xsrdpic 1, 1 +; PC64LE-NEXT: xsrdpic 0, 0 ; PC64LE-NEXT: addi 3, 3, .LCPI77_3@toc@l +; PC64LE-NEXT: xsrdpic 1, 1 ; PC64LE-NEXT: xsrdpic 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 @@ -4777,7 +4777,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3 ; PC64LE9-NEXT: xxsldwi 34, 2, 2, 3 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: blr entry: @@ -4811,7 +4811,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI78_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI78_1@toc@l ; PC64LE9-NEXT: xsrdpic 3, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvrdpic 2, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -4844,11 +4844,11 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI79_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI79_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI79_1@toc@l ; PC64LE9-NEXT: xvrdpic 34, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvrdpic 35, 0 ; PC64LE9-NEXT: blr entry: @@ -5021,7 +5021,7 @@ ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 31 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 @@ -5266,10 +5266,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI86_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI86_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI86_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmaxdp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5304,8 +5304,8 @@ ; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: nop ; PC64LE-NEXT: fmr 29, 1 -; PC64LE-NEXT: addis 3, 2, .LCPI87_4@toc@ha ; PC64LE-NEXT: fmr 1, 31 +; PC64LE-NEXT: addis 3, 2, .LCPI87_4@toc@ha ; PC64LE-NEXT: lfs 2, .LCPI87_4@toc@l(3) ; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: nop @@ -5359,7 +5359,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -5426,10 +5426,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI88_2@toc@ha ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI88_2@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI88_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI88_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmaxdp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -5473,17 +5473,17 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI89_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI89_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI89_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI89_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI89_2@toc@l ; PC64LE9-NEXT: xvmaxdp 34, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI89_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI89_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmaxdp 35, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5553,10 +5553,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI91_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI91_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI91_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmindp 34, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5591,8 +5591,8 @@ ; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: nop ; PC64LE-NEXT: fmr 29, 1 -; PC64LE-NEXT: addis 3, 2, .LCPI92_4@toc@ha ; PC64LE-NEXT: fmr 1, 31 +; PC64LE-NEXT: addis 3, 2, .LCPI92_4@toc@ha ; PC64LE-NEXT: lfs 2, .LCPI92_4@toc@l(3) ; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: nop @@ -5646,7 +5646,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 0, 29 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 @@ -5713,10 +5713,10 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI93_2@toc@ha ; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI93_2@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI93_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI93_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmindp 2, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 @@ -5760,17 +5760,17 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI94_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI94_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI94_1@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI94_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI94_2@toc@l ; PC64LE9-NEXT: xvmindp 34, 1, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI94_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI94_3@toc@l -; PC64LE9-NEXT: lxvx 1, 0, 3 +; PC64LE9-NEXT: lxv 1, 0(3) ; PC64LE9-NEXT: xvmindp 35, 1, 0 ; PC64LE9-NEXT: blr entry: @@ -5883,7 +5883,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI97_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI97_2@toc@l ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI97_3@toc@ha ; PC64LE9-NEXT: lfs 0, .LCPI97_3@toc@l(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 @@ -5912,7 +5912,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI98_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI98_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvspsxws 34, 0 ; PC64LE9-NEXT: blr entry: @@ -5986,10 +5986,10 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI101_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI101_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI101_2@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI101_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI101_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI101_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI101_2@toc@l(5) +; PC64LE-NEXT: lfs 2, .LCPI101_2@toc@l(3) ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 2, 2 @@ -6027,11 +6027,11 @@ ; PC64LE-NEXT: addis 3, 2, .LCPI102_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI102_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI102_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI102_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI102_1@toc@l(4) -; PC64LE-NEXT: addis 4, 2, .LCPI102_3@toc@ha +; PC64LE-NEXT: addis 3, 2, .LCPI102_2@toc@ha ; PC64LE-NEXT: lfs 2, .LCPI102_2@toc@l(3) -; PC64LE-NEXT: lfs 3, .LCPI102_3@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LCPI102_3@toc@ha +; PC64LE-NEXT: lfs 3, .LCPI102_3@toc@l(3) ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 2, 2 @@ -6178,7 +6178,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI105_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI105_2@toc@l ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI105_3@toc@ha ; PC64LE9-NEXT: lfd 0, .LCPI105_3@toc@l(3) ; PC64LE9-NEXT: xscvdpsxws 0, 0 @@ -6199,12 +6199,12 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI106_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI106_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI106_2@toc@ha ; PC64LE-NEXT: lfd 0, .LCPI106_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI106_3@toc@ha +; PC64LE-NEXT: addis 3, 2, .LCPI106_2@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI106_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI106_2@toc@l(5) -; PC64LE-NEXT: lfd 3, .LCPI106_3@toc@l(3) +; PC64LE-NEXT: addis 4, 2, .LCPI106_3@toc@ha +; PC64LE-NEXT: lfd 2, .LCPI106_2@toc@l(3) +; PC64LE-NEXT: lfd 3, .LCPI106_3@toc@l(4) ; PC64LE-NEXT: xscvdpsxws 0, 0 ; PC64LE-NEXT: xscvdpsxws 1, 1 ; PC64LE-NEXT: xscvdpsxws 2, 2 @@ -6287,7 +6287,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI108_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI108_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvdpsxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6302,10 +6302,10 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI109_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI109_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI109_2@toc@ha ; PC64LE-NEXT: lfd 0, .LCPI109_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI109_2@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI109_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI109_2@toc@l(5) +; PC64LE-NEXT: lfd 2, .LCPI109_2@toc@l(3) ; PC64LE-NEXT: xscvdpsxds 0, 0 ; PC64LE-NEXT: xscvdpsxds 1, 1 ; PC64LE-NEXT: xscvdpsxds 2, 2 @@ -6356,11 +6356,11 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI110_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI110_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI110_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI110_1@toc@l ; PC64LE9-NEXT: xvcvdpsxds 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvdpsxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6471,7 +6471,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI113_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI113_2@toc@l ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI113_3@toc@ha ; PC64LE9-NEXT: lfs 0, .LCPI113_3@toc@l(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 @@ -6500,7 +6500,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI114_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI114_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvspuxws 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6574,10 +6574,10 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI117_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI117_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI117_2@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI117_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI117_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI117_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI117_2@toc@l(5) +; PC64LE-NEXT: lfs 2, .LCPI117_2@toc@l(3) ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 2, 2 @@ -6615,11 +6615,11 @@ ; PC64LE-NEXT: addis 3, 2, .LCPI118_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI118_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI118_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI118_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI118_1@toc@l(4) -; PC64LE-NEXT: addis 4, 2, .LCPI118_3@toc@ha +; PC64LE-NEXT: addis 3, 2, .LCPI118_2@toc@ha ; PC64LE-NEXT: lfs 2, .LCPI118_2@toc@l(3) -; PC64LE-NEXT: lfs 3, .LCPI118_3@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LCPI118_3@toc@ha +; PC64LE-NEXT: lfs 3, .LCPI118_3@toc@l(3) ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 2, 2 @@ -6765,7 +6765,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI121_2@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI121_2@toc@l ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI121_3@toc@ha ; PC64LE9-NEXT: lfd 0, .LCPI121_3@toc@l(3) ; PC64LE9-NEXT: xscvdpuxws 0, 0 @@ -6786,12 +6786,12 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI122_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI122_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI122_2@toc@ha ; PC64LE-NEXT: lfd 0, .LCPI122_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI122_3@toc@ha +; PC64LE-NEXT: addis 3, 2, .LCPI122_2@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI122_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI122_2@toc@l(5) -; PC64LE-NEXT: lfd 3, .LCPI122_3@toc@l(3) +; PC64LE-NEXT: addis 4, 2, .LCPI122_3@toc@ha +; PC64LE-NEXT: lfd 2, .LCPI122_2@toc@l(3) +; PC64LE-NEXT: lfd 3, .LCPI122_3@toc@l(4) ; PC64LE-NEXT: xscvdpuxws 0, 0 ; PC64LE-NEXT: xscvdpuxws 1, 1 ; PC64LE-NEXT: xscvdpuxws 2, 2 @@ -6874,7 +6874,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI124_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI124_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvdpuxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6889,10 +6889,10 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI125_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI125_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI125_2@toc@ha ; PC64LE-NEXT: lfd 0, .LCPI125_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI125_2@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI125_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI125_2@toc@l(5) +; PC64LE-NEXT: lfd 2, .LCPI125_2@toc@l(3) ; PC64LE-NEXT: xscvdpuxds 0, 0 ; PC64LE-NEXT: xscvdpuxds 1, 1 ; PC64LE-NEXT: xscvdpuxds 2, 2 @@ -6943,11 +6943,11 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI126_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI126_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI126_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI126_1@toc@l ; PC64LE9-NEXT: xvcvdpuxds 35, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: xvcvdpuxds 34, 0 ; PC64LE9-NEXT: blr entry: @@ -6984,9 +6984,9 @@ ; PC64LE-LABEL: constrained_vector_fptrunc_v2f64: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI128_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI128_1@toc@ha ; PC64LE-NEXT: lfd 0, .LCPI128_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI128_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LCPI128_1@toc@ha +; PC64LE-NEXT: lfd 1, .LCPI128_1@toc@l(3) ; PC64LE-NEXT: xsrsp 0, 0 ; PC64LE-NEXT: xsrsp 1, 1 ; PC64LE-NEXT: xscvdpspn 0, 0 @@ -7022,15 +7022,15 @@ ; PC64LE-LABEL: constrained_vector_fptrunc_v3f64: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI129_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI129_1@toc@ha ; PC64LE-NEXT: lfd 0, .LCPI129_0@toc@l(3) -; PC64LE-NEXT: lfd 1, .LCPI129_1@toc@l(4) +; PC64LE-NEXT: addis 3, 2, .LCPI129_1@toc@ha +; PC64LE-NEXT: lfd 1, .LCPI129_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI129_3@toc@ha -; PC64LE-NEXT: xsrsp 0, 0 ; PC64LE-NEXT: lfd 2, .LCPI129_3@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI129_2@toc@ha -; PC64LE-NEXT: xsrsp 1, 1 +; PC64LE-NEXT: xsrsp 0, 0 ; PC64LE-NEXT: addi 3, 3, .LCPI129_2@toc@l +; PC64LE-NEXT: xsrsp 1, 1 ; PC64LE-NEXT: xsrsp 2, 2 ; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 1, 1 @@ -7058,7 +7058,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI129_3@toc@ha ; PC64LE9-NEXT: lfd 0, .LCPI129_3@toc@l(3) ; PC64LE9-NEXT: xsrsp 0, 0 @@ -7080,12 +7080,12 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI130_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI130_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI130_2@toc@ha -; PC64LE-NEXT: addis 6, 2, .LCPI130_3@toc@ha ; PC64LE-NEXT: lfd 0, .LCPI130_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI130_2@toc@ha ; PC64LE-NEXT: lfd 1, .LCPI130_1@toc@l(4) -; PC64LE-NEXT: lfd 2, .LCPI130_2@toc@l(5) -; PC64LE-NEXT: lfd 3, .LCPI130_3@toc@l(6) +; PC64LE-NEXT: addis 4, 2, .LCPI130_3@toc@ha +; PC64LE-NEXT: lfd 2, .LCPI130_2@toc@l(3) +; PC64LE-NEXT: lfd 3, .LCPI130_3@toc@l(4) ; PC64LE-NEXT: xxmrghd 0, 1, 0 ; PC64LE-NEXT: xxmrghd 1, 3, 2 ; PC64LE-NEXT: xvcvdpsp 34, 0 @@ -7167,10 +7167,10 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI133_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI133_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI133_2@toc@ha ; PC64LE-NEXT: lfs 3, .LCPI133_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI133_2@toc@ha ; PC64LE-NEXT: lfs 2, .LCPI133_1@toc@l(4) -; PC64LE-NEXT: lfs 1, .LCPI133_2@toc@l(5) +; PC64LE-NEXT: lfs 1, .LCPI133_2@toc@l(3) ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_fpext_v3f32: @@ -7195,12 +7195,12 @@ ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI134_0@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI134_1@toc@ha -; PC64LE-NEXT: addis 5, 2, .LCPI134_2@toc@ha -; PC64LE-NEXT: addis 6, 2, .LCPI134_3@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI134_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI134_2@toc@ha ; PC64LE-NEXT: lfs 1, .LCPI134_1@toc@l(4) -; PC64LE-NEXT: lfs 2, .LCPI134_2@toc@l(5) -; PC64LE-NEXT: lfs 3, .LCPI134_3@toc@l(6) +; PC64LE-NEXT: addis 4, 2, .LCPI134_3@toc@ha +; PC64LE-NEXT: lfs 2, .LCPI134_2@toc@l(3) +; PC64LE-NEXT: lfs 3, .LCPI134_3@toc@l(4) ; PC64LE-NEXT: xxmrghd 34, 1, 0 ; PC64LE-NEXT: xxmrghd 35, 3, 2 ; PC64LE-NEXT: blr @@ -7268,10 +7268,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI136_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI136_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI136_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI136_1@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xvrdpip 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7285,10 +7285,10 @@ ; PC64LE-LABEL: constrained_vector_ceil_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI137_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI137_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI137_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI137_1@toc@ha +; PC64LE-NEXT: lfs 1, .LCPI137_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI137_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI137_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI137_2@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI137_3@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI137_3@toc@l @@ -7310,7 +7310,7 @@ ; PC64LE9-NEXT: lfs 0, .LCPI137_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI137_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI137_3@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7343,7 +7343,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI138_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI138_1@toc@l ; PC64LE9-NEXT: xsrdpip 0, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI138_2@toc@ha ; PC64LE9-NEXT: lfs 1, .LCPI138_2@toc@l(3) ; PC64LE9-NEXT: xvrdpip 0, 0 @@ -7400,10 +7400,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI140_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI140_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI140_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI140_1@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xvrdpim 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7417,10 +7417,10 @@ ; PC64LE-LABEL: constrained_vector_floor_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI141_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI141_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI141_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI141_1@toc@ha +; PC64LE-NEXT: lfs 1, .LCPI141_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI141_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI141_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI141_2@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI141_3@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI141_3@toc@l @@ -7442,7 +7442,7 @@ ; PC64LE9-NEXT: lfs 0, .LCPI141_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI141_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI141_3@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7475,7 +7475,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI142_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI142_1@toc@l ; PC64LE9-NEXT: xsrdpim 0, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI142_2@toc@ha ; PC64LE9-NEXT: lfs 1, .LCPI142_2@toc@l(3) ; PC64LE9-NEXT: xvrdpim 0, 0 @@ -7531,10 +7531,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI144_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI144_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI144_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI144_1@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xvrdpi 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7548,10 +7548,10 @@ ; PC64LE-LABEL: constrained_vector_round_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI145_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI145_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI145_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI145_1@toc@ha +; PC64LE-NEXT: lfs 1, .LCPI145_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI145_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI145_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI145_2@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI145_3@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI145_3@toc@l @@ -7573,7 +7573,7 @@ ; PC64LE9-NEXT: lfs 0, .LCPI145_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI145_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI145_3@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7587,18 +7587,18 @@ define <3 x double> @constrained_vector_round_v3f64() #0 { ; PC64LE-LABEL: constrained_vector_round_v3f64: ; PC64LE: # %bb.0: # %entry -; PC64LE-NEXT: addis 4, 2, .LCPI146_1@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI146_0@toc@ha -; PC64LE-NEXT: addi 4, 4, .LCPI146_1@toc@l -; PC64LE-NEXT: lxvd2x 1, 0, 4 -; PC64LE-NEXT: addis 4, 2, .LCPI146_3@toc@ha +; PC64LE-NEXT: addis 4, 2, .LCPI146_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI146_0@toc@l(3) -; PC64LE-NEXT: addis 3, 2, .LCPI146_2@toc@ha +; PC64LE-NEXT: addi 3, 4, .LCPI146_1@toc@l +; PC64LE-NEXT: addis 4, 2, .LCPI146_3@toc@ha ; PC64LE-NEXT: lfs 2, .LCPI146_3@toc@l(4) +; PC64LE-NEXT: lxvd2x 1, 0, 3 +; PC64LE-NEXT: addis 3, 2, .LCPI146_2@toc@ha ; PC64LE-NEXT: xsrdpi 0, 0 +; PC64LE-NEXT: fmr 3, 2 ; PC64LE-NEXT: xvrdpi 0, 1 ; PC64LE-NEXT: lfs 1, .LCPI146_2@toc@l(3) -; PC64LE-NEXT: fmr 3, 2 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_round_v3f64: @@ -7608,7 +7608,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI146_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI146_1@toc@l ; PC64LE9-NEXT: xsrdpi 0, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI146_2@toc@ha ; PC64LE9-NEXT: lfs 1, .LCPI146_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI146_3@toc@ha @@ -7665,10 +7665,10 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI148_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI148_0@toc@l -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI148_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI148_1@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xvrdpiz 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7682,10 +7682,10 @@ ; PC64LE-LABEL: constrained_vector_trunc_v3f32: ; PC64LE: # %bb.0: # %entry ; PC64LE-NEXT: addis 3, 2, .LCPI149_0@toc@ha -; PC64LE-NEXT: addis 4, 2, .LCPI149_1@toc@ha ; PC64LE-NEXT: lfs 0, .LCPI149_0@toc@l(3) +; PC64LE-NEXT: addis 3, 2, .LCPI149_1@toc@ha +; PC64LE-NEXT: lfs 1, .LCPI149_1@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI149_2@toc@ha -; PC64LE-NEXT: lfs 1, .LCPI149_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI149_2@toc@l(3) ; PC64LE-NEXT: addis 3, 2, .LCPI149_3@toc@ha ; PC64LE-NEXT: addi 3, 3, .LCPI149_3@toc@l @@ -7707,7 +7707,7 @@ ; PC64LE9-NEXT: lfs 0, .LCPI149_2@toc@l(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI149_3@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI149_3@toc@l -; PC64LE9-NEXT: lxvx 34, 0, 3 +; PC64LE9-NEXT: lxv 34, 0(3) ; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: blr entry: @@ -7740,7 +7740,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI150_1@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI150_1@toc@l ; PC64LE9-NEXT: xsrdpiz 0, 0 -; PC64LE9-NEXT: lxvx 0, 0, 3 +; PC64LE9-NEXT: lxv 0, 0(3) ; PC64LE9-NEXT: addis 3, 2, .LCPI150_2@toc@ha ; PC64LE9-NEXT: lfs 1, .LCPI150_2@toc@l(3) ; PC64LE9-NEXT: xvrdpiz 0, 0 @@ -7854,7 +7854,7 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI155_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI155_0@toc@l -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: vperm 2, 2, 2, 3 ; PC64LE9-NEXT: vextsh2d 2, 2 ; PC64LE9-NEXT: xvcvsxddp 34, 34 @@ -8082,7 +8082,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 3, 4, 3 -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: mtfprwa 0, 3 ; PC64LE9-NEXT: xscvsxdsp 0, 0 @@ -8163,7 +8163,7 @@ ; PC64LE9-NEXT: mtfprd 0, 5 ; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 @@ -8438,7 +8438,7 @@ ; PC64LE9-NEXT: addis 3, 2, .LCPI173_0@toc@ha ; PC64LE9-NEXT: xxlxor 36, 36, 36 ; PC64LE9-NEXT: addi 3, 3, .LCPI173_0@toc@l -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: xvcvuxddp 34, 34 ; PC64LE9-NEXT: blr @@ -8665,7 +8665,7 @@ ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vmrghw 3, 4, 3 -; PC64LE9-NEXT: lxvx 36, 0, 3 +; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: mtfprwz 0, 3 ; PC64LE9-NEXT: xscvuxdsp 0, 0 @@ -8746,7 +8746,7 @@ ; PC64LE9-NEXT: mtfprd 0, 5 ; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: vmrghw 2, 3, 2 -; PC64LE9-NEXT: lxvx 35, 0, 3 +; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3 diff --git a/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll b/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll --- a/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll +++ b/llvm/test/CodeGen/PowerPC/vector-extend-sign.ll @@ -149,7 +149,7 @@ ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi 3, 3, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxvx 35, 0, 3 +; CHECK-P9-NEXT: lxv 35, 0(3) ; CHECK-P9-NEXT: vsld 2, 2, 3 ; CHECK-P9-NEXT: vsrad 2, 2, 3 ; CHECK-P9-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll --- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll +++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll @@ -12000,7 +12000,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI100_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI100_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12067,7 +12067,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI101_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI101_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12201,7 +12201,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI102_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI102_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12335,7 +12335,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI103_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI103_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12469,7 +12469,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI104_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI104_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12603,7 +12603,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI105_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI105_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12737,7 +12737,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI106_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI106_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -12871,7 +12871,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI107_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI107_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13005,7 +13005,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI108_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI108_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13139,7 +13139,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI109_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI109_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13273,7 +13273,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI110_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI110_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13407,7 +13407,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI111_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI111_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13541,7 +13541,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI112_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI112_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13675,7 +13675,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI113_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI113_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13809,7 +13809,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI114_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI114_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -13943,7 +13943,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI115_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI115_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14077,7 +14077,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI116_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI116_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14211,7 +14211,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI117_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI117_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14345,7 +14345,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI118_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI118_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14479,7 +14479,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI119_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI119_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14613,7 +14613,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI120_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI120_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14747,7 +14747,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI121_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI121_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -14881,7 +14881,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI122_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI122_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15015,7 +15015,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI123_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI123_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15149,7 +15149,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI124_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI124_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15283,7 +15283,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI125_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI125_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15417,7 +15417,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI126_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI126_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15551,7 +15551,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI127_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI127_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15685,7 +15685,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI128_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI128_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15819,7 +15819,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI129_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI129_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -15953,7 +15953,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI130_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI130_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16087,7 +16087,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI131_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI131_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16221,7 +16221,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI132_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI132_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16355,7 +16355,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI133_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI133_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16489,7 +16489,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI134_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI134_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16623,7 +16623,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI135_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI135_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16757,7 +16757,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI136_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI136_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -16891,7 +16891,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI137_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI137_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17025,7 +17025,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI138_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI138_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17159,7 +17159,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI139_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI139_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17293,7 +17293,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI140_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI140_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17427,7 +17427,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI141_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI141_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17561,7 +17561,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI142_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI142_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17695,7 +17695,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI143_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI143_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17829,7 +17829,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI144_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI144_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -17963,7 +17963,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI145_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI145_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18097,7 +18097,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI146_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI146_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18231,7 +18231,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI147_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI147_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18365,7 +18365,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI148_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI148_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18499,7 +18499,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI149_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI149_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18633,7 +18633,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI150_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI150_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18767,7 +18767,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI151_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI151_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -18901,7 +18901,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI152_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI152_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19035,7 +19035,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI153_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI153_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19169,7 +19169,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI154_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI154_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19303,7 +19303,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI155_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI155_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19437,7 +19437,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI156_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI156_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19571,7 +19571,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI157_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI157_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19705,7 +19705,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI158_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI158_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19839,7 +19839,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI159_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI159_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -19973,7 +19973,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI160_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI160_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20107,7 +20107,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI161_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI161_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20241,7 +20241,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI162_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI162_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20375,7 +20375,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI163_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI163_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20509,7 +20509,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI164_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI164_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20643,7 +20643,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI165_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI165_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20777,7 +20777,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI166_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI166_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -20911,7 +20911,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI167_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI167_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21045,7 +21045,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI168_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI168_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21179,7 +21179,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI169_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI169_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21313,7 +21313,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI170_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI170_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21447,7 +21447,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI171_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI171_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21581,7 +21581,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI172_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI172_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21715,7 +21715,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI173_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI173_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21849,7 +21849,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI174_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI174_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -21983,7 +21983,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI175_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI175_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22117,7 +22117,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI176_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI176_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22251,7 +22251,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI177_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI177_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22385,7 +22385,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI178_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI178_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22519,7 +22519,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI179_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI179_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22653,7 +22653,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI180_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI180_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22787,7 +22787,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI181_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI181_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -22921,7 +22921,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI182_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI182_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23055,7 +23055,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI183_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI183_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23189,7 +23189,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI184_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI184_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23323,7 +23323,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI185_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI185_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23457,7 +23457,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI186_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI186_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23591,7 +23591,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI187_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI187_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23725,7 +23725,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI188_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI188_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23859,7 +23859,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI189_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI189_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -23993,7 +23993,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI190_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI190_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24127,7 +24127,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI191_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI191_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24261,7 +24261,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI192_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI192_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24395,7 +24395,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI193_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI193_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24529,7 +24529,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI194_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI194_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24663,7 +24663,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI195_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI195_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24797,7 +24797,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI196_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI196_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -24931,7 +24931,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI197_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI197_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25065,7 +25065,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI198_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI198_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25199,7 +25199,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI199_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI199_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25333,7 +25333,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI200_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI200_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25467,7 +25467,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI201_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI201_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25601,7 +25601,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI202_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI202_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25735,7 +25735,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI203_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI203_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -25869,7 +25869,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI204_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI204_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26003,7 +26003,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI205_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI205_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26137,7 +26137,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI206_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI206_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26271,7 +26271,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI207_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI207_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26405,7 +26405,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI208_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI208_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26539,7 +26539,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI209_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI209_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26673,7 +26673,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI210_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI210_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26807,7 +26807,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI211_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI211_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -26941,7 +26941,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI212_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI212_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27075,7 +27075,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI213_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI213_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27209,7 +27209,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI214_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI214_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27343,7 +27343,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI215_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI215_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27477,7 +27477,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI216_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI216_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27611,7 +27611,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI217_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI217_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27745,7 +27745,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI218_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI218_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -27879,7 +27879,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI219_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI219_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -28013,7 +28013,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI220_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI220_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -28147,7 +28147,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI221_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI221_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -28281,7 +28281,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI222_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI222_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 2, 3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) @@ -28415,7 +28415,7 @@ ; PWR9-NEXT: addis 3, 2, .LCPI223_0@toc@ha ; PWR9-NEXT: vpopcntd 2, 2 ; PWR9-NEXT: addi 3, 3, .LCPI223_0@toc@l -; PWR9-NEXT: lxvx 35, 0, 3 +; PWR9-NEXT: lxv 35, 0(3) ; PWR9-NEXT: vcmpgtud 2, 3, 2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) diff --git a/llvm/test/CodeGen/PowerPC/vsx-p9.ll b/llvm/test/CodeGen/PowerPC/vsx-p9.ll --- a/llvm/test/CodeGen/PowerPC/vsx-p9.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-p9.ll @@ -36,8 +36,8 @@ %1 = load <16 x i8>, <16 x i8>* @ucb, align 16 %add.i = add <16 x i8> %1, %0 tail call void (...) @sink(<16 x i8> %add.i) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vaddubm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -45,8 +45,8 @@ %3 = load <16 x i8>, <16 x i8>* @scb, align 16 %add.i22 = add <16 x i8> %3, %2 tail call void (...) @sink(<16 x i8> %add.i22) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vaddubm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -54,8 +54,8 @@ %5 = load <8 x i16>, <8 x i16>* @usb, align 16 %add.i21 = add <8 x i16> %5, %4 tail call void (...) @sink(<8 x i16> %add.i21) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduhm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -63,8 +63,8 @@ %7 = load <8 x i16>, <8 x i16>* @ssb, align 16 %add.i20 = add <8 x i16> %7, %6 tail call void (...) @sink(<8 x i16> %add.i20) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduhm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -72,8 +72,8 @@ %9 = load <4 x i32>, <4 x i32>* @uib, align 16 %add.i19 = add <4 x i32> %9, %8 tail call void (...) @sink(<4 x i32> %add.i19) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduwm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -81,8 +81,8 @@ %11 = load <4 x i32>, <4 x i32>* @sib, align 16 %add.i18 = add <4 x i32> %11, %10 tail call void (...) @sink(<4 x i32> %add.i18) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduwm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -90,8 +90,8 @@ %13 = load <2 x i64>, <2 x i64>* @ullb, align 16 %add.i17 = add <2 x i64> %13, %12 tail call void (...) @sink(<2 x i64> %add.i17) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vaddudm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -99,8 +99,8 @@ %15 = load <2 x i64>, <2 x i64>* @sllb, align 16 %add.i16 = add <2 x i64> %15, %14 tail call void (...) @sink(<2 x i64> %add.i16) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vaddudm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -108,8 +108,8 @@ %17 = load <1 x i128>, <1 x i128>* @uxb, align 16 %add.i15 = add <1 x i128> %17, %16 tail call void (...) @sink(<1 x i128> %add.i15) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduqm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -117,8 +117,8 @@ %19 = load <1 x i128>, <1 x i128>* @sxb, align 16 %add.i14 = add <1 x i128> %19, %18 tail call void (...) @sink(<1 x i128> %add.i14) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 3 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(3) ; CHECK: vadduqm 2, 3, 2 ; CHECK: stxv 34, ; CHECK: bl sink @@ -126,8 +126,8 @@ %21 = load <4 x float>, <4 x float>* @vfb, align 16 %add.i13 = fadd <4 x float> %20, %21 tail call void (...) @sink(<4 x float> %add.i13) -; CHECK: lxvx 0, 0, 3 -; CHECK: lxvx 1, 0, 3 +; CHECK: lxv 0, 0(3) +; CHECK: lxv 1, 0(3) ; CHECK: xvaddsp 34, 0, 1 ; CHECK: stxv 34, ; CHECK: bl sink @@ -135,8 +135,8 @@ %23 = load <2 x double>, <2 x double>* @vdb, align 16 %add.i12 = fadd <2 x double> %22, %23 tail call void (...) @sink(<2 x double> %add.i12) -; CHECK: lxvx 0, 0, 3 -; CHECK: lxvx 1, 0, 3 +; CHECK: lxv 0, 0(3) +; CHECK: lxv 1, 0(3) ; CHECK: xvadddp 0, 0, 1 ; CHECK: stxv 0, ; CHECK: bl sink diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll --- a/llvm/test/CodeGen/PowerPC/vsx.ll +++ b/llvm/test/CodeGen/PowerPC/vsx.ll @@ -1308,12 +1308,12 @@ ; CHECK-NEXT: ld r3, -8(r1) ; CHECK-NEXT: std r3, -24(r1) ; CHECK-NEXT: ld r3, -16(r1) -; CHECK-NEXT: std r3, -32(r1) ; CHECK-NEXT: lfd f0, -24(r1) +; CHECK-NEXT: std r3, -32(r1) +; CHECK-NEXT: addi r3, r1, -48 ; CHECK-NEXT: fcfidus f0, f0 ; CHECK-NEXT: stfs f0, -48(r1) ; CHECK-NEXT: lfd f0, -32(r1) -; CHECK-NEXT: addi r3, r1, -48 ; CHECK-NEXT: fcfidus f0, f0 ; CHECK-NEXT: stfs f0, -64(r1) ; CHECK-NEXT: lxvw4x v2, 0, r3 @@ -1329,12 +1329,12 @@ ; CHECK-REG-NEXT: ld r3, -8(r1) ; CHECK-REG-NEXT: std r3, -24(r1) ; CHECK-REG-NEXT: ld r3, -16(r1) -; CHECK-REG-NEXT: std r3, -32(r1) ; CHECK-REG-NEXT: lfd f0, -24(r1) +; CHECK-REG-NEXT: std r3, -32(r1) +; CHECK-REG-NEXT: addi r3, r1, -48 ; CHECK-REG-NEXT: fcfidus f0, f0 ; CHECK-REG-NEXT: stfs f0, -48(r1) ; CHECK-REG-NEXT: lfd f0, -32(r1) -; CHECK-REG-NEXT: addi r3, r1, -48 ; CHECK-REG-NEXT: fcfidus f0, f0 ; CHECK-REG-NEXT: stfs f0, -64(r1) ; CHECK-REG-NEXT: lxvw4x v2, 0, r3 @@ -1390,12 +1390,12 @@ ; CHECK-NEXT: ld r3, -8(r1) ; CHECK-NEXT: std r3, -24(r1) ; CHECK-NEXT: ld r3, -16(r1) -; CHECK-NEXT: std r3, -32(r1) ; CHECK-NEXT: lfd f0, -24(r1) +; CHECK-NEXT: std r3, -32(r1) +; CHECK-NEXT: addi r3, r1, -48 ; CHECK-NEXT: fcfids f0, f0 ; CHECK-NEXT: stfs f0, -48(r1) ; CHECK-NEXT: lfd f0, -32(r1) -; CHECK-NEXT: addi r3, r1, -48 ; CHECK-NEXT: fcfids f0, f0 ; CHECK-NEXT: stfs f0, -64(r1) ; CHECK-NEXT: lxvw4x v2, 0, r3 @@ -1411,12 +1411,12 @@ ; CHECK-REG-NEXT: ld r3, -8(r1) ; CHECK-REG-NEXT: std r3, -24(r1) ; CHECK-REG-NEXT: ld r3, -16(r1) -; CHECK-REG-NEXT: std r3, -32(r1) ; CHECK-REG-NEXT: lfd f0, -24(r1) +; CHECK-REG-NEXT: std r3, -32(r1) +; CHECK-REG-NEXT: addi r3, r1, -48 ; CHECK-REG-NEXT: fcfids f0, f0 ; CHECK-REG-NEXT: stfs f0, -48(r1) ; CHECK-REG-NEXT: lfd f0, -32(r1) -; CHECK-REG-NEXT: addi r3, r1, -48 ; CHECK-REG-NEXT: fcfids f0, f0 ; CHECK-REG-NEXT: stfs f0, -64(r1) ; CHECK-REG-NEXT: lxvw4x v2, 0, r3 @@ -1472,10 +1472,10 @@ ; CHECK-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: stfd f0, -32(r1) ; CHECK-NEXT: lfs f0, -48(r1) -; CHECK-NEXT: xscvdpuxds f0, f0 -; CHECK-NEXT: stfd f0, -24(r1) ; CHECK-NEXT: ld r3, -32(r1) +; CHECK-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: std r3, -8(r1) +; CHECK-NEXT: stfd f0, -24(r1) ; CHECK-NEXT: ld r3, -24(r1) ; CHECK-NEXT: std r3, -16(r1) ; CHECK-NEXT: addi r3, r1, -16 @@ -1490,10 +1490,10 @@ ; CHECK-REG-NEXT: xscvdpuxds f0, f0 ; CHECK-REG-NEXT: stfd f0, -32(r1) ; CHECK-REG-NEXT: lfs f0, -48(r1) -; CHECK-REG-NEXT: xscvdpuxds f0, f0 -; CHECK-REG-NEXT: stfd f0, -24(r1) ; CHECK-REG-NEXT: ld r3, -32(r1) +; CHECK-REG-NEXT: xscvdpuxds f0, f0 ; CHECK-REG-NEXT: std r3, -8(r1) +; CHECK-REG-NEXT: stfd f0, -24(r1) ; CHECK-REG-NEXT: ld r3, -24(r1) ; CHECK-REG-NEXT: std r3, -16(r1) ; CHECK-REG-NEXT: addi r3, r1, -16 @@ -1539,10 +1539,10 @@ ; CHECK-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: stfd f0, -32(r1) ; CHECK-NEXT: lfs f0, -48(r1) -; CHECK-NEXT: xscvdpsxds f0, f0 -; CHECK-NEXT: stfd f0, -24(r1) ; CHECK-NEXT: ld r3, -32(r1) +; CHECK-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: std r3, -8(r1) +; CHECK-NEXT: stfd f0, -24(r1) ; CHECK-NEXT: ld r3, -24(r1) ; CHECK-NEXT: std r3, -16(r1) ; CHECK-NEXT: addi r3, r1, -16 @@ -1557,10 +1557,10 @@ ; CHECK-REG-NEXT: xscvdpsxds f0, f0 ; CHECK-REG-NEXT: stfd f0, -32(r1) ; CHECK-REG-NEXT: lfs f0, -48(r1) -; CHECK-REG-NEXT: xscvdpsxds f0, f0 -; CHECK-REG-NEXT: stfd f0, -24(r1) ; CHECK-REG-NEXT: ld r3, -32(r1) +; CHECK-REG-NEXT: xscvdpsxds f0, f0 ; CHECK-REG-NEXT: std r3, -8(r1) +; CHECK-REG-NEXT: stfd f0, -24(r1) ; CHECK-REG-NEXT: ld r3, -24(r1) ; CHECK-REG-NEXT: std r3, -16(r1) ; CHECK-REG-NEXT: addi r3, r1, -16 diff --git a/llvm/test/CodeGen/PowerPC/vsx_builtins.ll b/llvm/test/CodeGen/PowerPC/vsx_builtins.ll --- a/llvm/test/CodeGen/PowerPC/vsx_builtins.ll +++ b/llvm/test/CodeGen/PowerPC/vsx_builtins.ll @@ -1,7 +1,28 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr9 \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefixes=CHECK,CHECK-P9 +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefixes=CHECK,CHECK-NOINTRIN +; RUN: llc -verify-machineinstrs -mcpu=pwr9 \ +; RUN: -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefixes=CHECK,CHECK-P9 +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \ +; RUN: -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefixes=CHECK,CHECK-INTRIN +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \ +; RUN: -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefixes=CHECK,CHECK-INTRIN ; Function Attrs: nounwind readnone define <4 x i32> @test1(i8* %a) { @@ -140,3 +161,51 @@ %.lobit = and i32 %1, 1 ret i32 %.lobit } + +; Function Attrs: nounwind readnone +define <2 x double> @test_lxvd2x(i8* %a) { +; CHECK-P9-LABEL: test_lxvd2x: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: lxv v2, 0(r3) +; CHECK-P9-NEXT: blr +; +; CHECK-NOINTRIN-LABEL: test_lxvd2x: +; CHECK-NOINTRIN: # %bb.0: # %entry +; CHECK-NOINTRIN-NEXT: lxvd2x vs0, 0, r3 +; CHECK-NOINTRIN-NEXT: xxswapd v2, vs0 +; CHECK-NOINTRIN-NEXT: blr +; +; CHECK-INTRIN-LABEL: test_lxvd2x: +; CHECK-INTRIN: # %bb.0: # %entry +; CHECK-INTRIN-NEXT: lxvd2x v2, 0, r3 +; CHECK-INTRIN-NEXT: blr +entry: + %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %a) + ret <2 x double> %0 +} +; Function Attrs: nounwind readnone +declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*) + +; Function Attrs: nounwind readnone +define void @test_stxvd2x(<2 x double> %a, i8* %b) { +; CHECK-P9-LABEL: test_stxvd2x: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: stxv v2, 0(r5) +; CHECK-P9-NEXT: blr +; +; CHECK-NOINTRIN-LABEL: test_stxvd2x: +; CHECK-NOINTRIN: # %bb.0: # %entry +; CHECK-NOINTRIN-NEXT: xxswapd vs0, v2 +; CHECK-NOINTRIN-NEXT: stxvd2x vs0, 0, r5 +; CHECK-NOINTRIN-NEXT: blr +; +; CHECK-INTRIN-LABEL: test_stxvd2x: +; CHECK-INTRIN: # %bb.0: # %entry +; CHECK-INTRIN-NEXT: stxvd2x v2, 0, r5 +; CHECK-INTRIN-NEXT: blr +entry: + tail call void @llvm.ppc.vsx.stxvd2x(<2 x double> %a, i8* %b) + ret void +} +; Function Attrs: nounwind readnone +declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*) diff --git a/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll --- a/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll +++ b/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll @@ -123,7 +123,7 @@ store volatile float %conv, float* %ff, align 4 ret void ; CHECK-LABEL: @dblToFloat -; CHECK: lfdx [[REGLD5:[0-9]+]], +; CHECK: lfd [[REGLD5:[0-9]+]], ; CHECK: stfs [[REGLD5]], ; CHECK-P9-LABEL: @dblToFloat ; CHECK-P9: lfd [[REGLD5:[0-9]+]], @@ -139,7 +139,7 @@ store volatile double %conv, double* %dd, align 8 ret void ; CHECK-LABEL: @floatToDbl -; CHECK: lfsx [[REGLD5:[0-9]+]], +; CHECK: lfs [[REGLD5:[0-9]+]], ; CHECK: stfd [[REGLD5]], ; CHECK-P9-LABEL: @floatToDbl ; CHECK-P9: lfs [[REGLD5:[0-9]+]],