diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -997,8 +997,8 @@ int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { using namespace AMDGPU::EncValues; - unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN; - unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX; + unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; + unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; } diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -247,8 +247,8 @@ SGPR_MAX_GFX10 = 105, TTMP_VI_MIN = 112, TTMP_VI_MAX = 123, - TTMP_GFX9_GFX10_MIN = 108, - TTMP_GFX9_GFX10_MAX = 123, + TTMP_GFX9PLUS_MIN = 108, + TTMP_GFX9PLUS_MAX = 123, INLINE_INTEGER_C_MIN = 128, INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 INLINE_INTEGER_C_MAX = 208, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -246,9 +246,9 @@ } foreach Index = 0...15 in { - defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>; - defm TTMP#Index#_gfx9_gfx10 : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>; - defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>; + defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>; + defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>; + defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>; } multiclass FLAT_SCR_LOHI_m ci_e, bits<16> vi_e> { @@ -419,8 +419,8 @@ getSubRegs.ret>; foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { - def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; - def TTMP#Index#_TTMP#!add(Index,1)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 2, Index>; + def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; + def TTMP#Index#_TTMP#!add(Index,1)#_gfx9plus : TmpRegTuples<"_gfx9plus", 2, Index>; } foreach Index = {0, 4, 8, 12} in { @@ -429,7 +429,7 @@ _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; def TTMP#Index#_TTMP#!add(Index,1)# _TTMP#!add(Index,2)# - _TTMP#!add(Index,3)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 4, Index>; + _TTMP#!add(Index,3)#_gfx9plus : TmpRegTuples<"_gfx9plus", 4, Index>; } foreach Index = {0, 4, 8} in { @@ -446,7 +446,7 @@ _TTMP#!add(Index,4)# _TTMP#!add(Index,5)# _TTMP#!add(Index,6)# - _TTMP#!add(Index,7)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 8, Index>; + _TTMP#!add(Index,7)#_gfx9plus : TmpRegTuples<"_gfx9plus", 8, Index>; } def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : @@ -456,12 +456,12 @@ TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; -def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9_gfx10 : +def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus : TmpRegTuplesBase<0, 16, - [TTMP0_gfx9_gfx10, TTMP1_gfx9_gfx10, TTMP2_gfx9_gfx10, TTMP3_gfx9_gfx10, - TTMP4_gfx9_gfx10, TTMP5_gfx9_gfx10, TTMP6_gfx9_gfx10, TTMP7_gfx9_gfx10, - TTMP8_gfx9_gfx10, TTMP9_gfx9_gfx10, TTMP10_gfx9_gfx10, TTMP11_gfx9_gfx10, - TTMP12_gfx9_gfx10, TTMP13_gfx9_gfx10, TTMP14_gfx9_gfx10, TTMP15_gfx9_gfx10]>; + [TTMP0_gfx9plus, TTMP1_gfx9plus, TTMP2_gfx9plus, TTMP3_gfx9plus, + TTMP4_gfx9plus, TTMP5_gfx9plus, TTMP6_gfx9plus, TTMP7_gfx9plus, + TTMP8_gfx9plus, TTMP9_gfx9plus, TTMP10_gfx9plus, TTMP11_gfx9plus, + TTMP12_gfx9plus, TTMP13_gfx9plus, TTMP14_gfx9plus, TTMP15_gfx9plus]>; class RegisterTypes reg_types> { list types = reg_types; diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -1138,46 +1138,46 @@ CASE_CI_VI(FLAT_SCR) \ CASE_CI_VI(FLAT_SCR_LO) \ CASE_CI_VI(FLAT_SCR_HI) \ - CASE_VI_GFX9_GFX10(TTMP0) \ - CASE_VI_GFX9_GFX10(TTMP1) \ - CASE_VI_GFX9_GFX10(TTMP2) \ - CASE_VI_GFX9_GFX10(TTMP3) \ - CASE_VI_GFX9_GFX10(TTMP4) \ - CASE_VI_GFX9_GFX10(TTMP5) \ - CASE_VI_GFX9_GFX10(TTMP6) \ - CASE_VI_GFX9_GFX10(TTMP7) \ - CASE_VI_GFX9_GFX10(TTMP8) \ - CASE_VI_GFX9_GFX10(TTMP9) \ - CASE_VI_GFX9_GFX10(TTMP10) \ - CASE_VI_GFX9_GFX10(TTMP11) \ - CASE_VI_GFX9_GFX10(TTMP12) \ - CASE_VI_GFX9_GFX10(TTMP13) \ - CASE_VI_GFX9_GFX10(TTMP14) \ - CASE_VI_GFX9_GFX10(TTMP15) \ - CASE_VI_GFX9_GFX10(TTMP0_TTMP1) \ - CASE_VI_GFX9_GFX10(TTMP2_TTMP3) \ - CASE_VI_GFX9_GFX10(TTMP4_TTMP5) \ - CASE_VI_GFX9_GFX10(TTMP6_TTMP7) \ - CASE_VI_GFX9_GFX10(TTMP8_TTMP9) \ - CASE_VI_GFX9_GFX10(TTMP10_TTMP11) \ - CASE_VI_GFX9_GFX10(TTMP12_TTMP13) \ - CASE_VI_GFX9_GFX10(TTMP14_TTMP15) \ - CASE_VI_GFX9_GFX10(TTMP0_TTMP1_TTMP2_TTMP3) \ - CASE_VI_GFX9_GFX10(TTMP4_TTMP5_TTMP6_TTMP7) \ - CASE_VI_GFX9_GFX10(TTMP8_TTMP9_TTMP10_TTMP11) \ - CASE_VI_GFX9_GFX10(TTMP12_TTMP13_TTMP14_TTMP15) \ - CASE_VI_GFX9_GFX10(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \ - CASE_VI_GFX9_GFX10(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \ - CASE_VI_GFX9_GFX10(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \ - CASE_VI_GFX9_GFX10(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \ + CASE_VI_GFX9PLUS(TTMP0) \ + CASE_VI_GFX9PLUS(TTMP1) \ + CASE_VI_GFX9PLUS(TTMP2) \ + CASE_VI_GFX9PLUS(TTMP3) \ + CASE_VI_GFX9PLUS(TTMP4) \ + CASE_VI_GFX9PLUS(TTMP5) \ + CASE_VI_GFX9PLUS(TTMP6) \ + CASE_VI_GFX9PLUS(TTMP7) \ + CASE_VI_GFX9PLUS(TTMP8) \ + CASE_VI_GFX9PLUS(TTMP9) \ + CASE_VI_GFX9PLUS(TTMP10) \ + CASE_VI_GFX9PLUS(TTMP11) \ + CASE_VI_GFX9PLUS(TTMP12) \ + CASE_VI_GFX9PLUS(TTMP13) \ + CASE_VI_GFX9PLUS(TTMP14) \ + CASE_VI_GFX9PLUS(TTMP15) \ + CASE_VI_GFX9PLUS(TTMP0_TTMP1) \ + CASE_VI_GFX9PLUS(TTMP2_TTMP3) \ + CASE_VI_GFX9PLUS(TTMP4_TTMP5) \ + CASE_VI_GFX9PLUS(TTMP6_TTMP7) \ + CASE_VI_GFX9PLUS(TTMP8_TTMP9) \ + CASE_VI_GFX9PLUS(TTMP10_TTMP11) \ + CASE_VI_GFX9PLUS(TTMP12_TTMP13) \ + CASE_VI_GFX9PLUS(TTMP14_TTMP15) \ + CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \ + CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \ + CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \ + CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \ + CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \ + CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \ + CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \ + CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \ } #define CASE_CI_VI(node) \ assert(!isSI(STI)); \ case node: return isCI(STI) ? node##_ci : node##_vi; -#define CASE_VI_GFX9_GFX10(node) \ - case node: return (isGFX9(STI) || isGFX10(STI)) ? node##_gfx9_gfx10 : node##_vi; +#define CASE_VI_GFX9PLUS(node) \ + case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi; unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) { if (STI.getTargetTriple().getArch() == Triple::r600) @@ -1186,17 +1186,17 @@ } #undef CASE_CI_VI -#undef CASE_VI_GFX9_GFX10 +#undef CASE_VI_GFX9PLUS #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node; -#define CASE_VI_GFX9_GFX10(node) case node##_vi: case node##_gfx9_gfx10: return node; +#define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node; unsigned mc2PseudoReg(unsigned Reg) { MAP_REG2REG } #undef CASE_CI_VI -#undef CASE_VI_GFX9_GFX10 +#undef CASE_VI_GFX9PLUS #undef MAP_REG2REG bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {