diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -101,6 +101,13 @@
   VLEFF_MASK,
   // read vl CSR
   READ_VL,
+  // Matches the semantics of vslideup/vslidedown. The first operand is the
+  // pass-thru operand, the second is the source vector, and the third is the
+  // XLenVT index (either constant or non-constant).
+  VSLIDEUP,
+  VSLIDEDOWN,
+  // Matches the semantics of the unmasked vid.v instruction.
+  VID,
 };
 } // namespace RISCVISD
 
@@ -298,6 +305,8 @@
   SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
                              int64_t ExtTrueVal) const;
   SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -403,12 +403,20 @@
         // 2. Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR"
         // nodes which truncate by one power of two at a time.
         setOperationAction(ISD::TRUNCATE, VT, Custom);
+
+        // Custom-lower insert/extract operations to simplify patterns.
+        setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
+        setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
       }
     }
 
-    // We must custom-lower SPLAT_VECTOR vXi64 on RV32
-    if (!Subtarget.is64Bit())
+    // We must custom-lower certain vXi64 operations on RV32 due to the vector
+    // element type being illegal.
+    if (!Subtarget.is64Bit()) {
       setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom);
+      setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::i64, Custom);
+      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i64, Custom);
+    }
 
     // Expand various CCs to best match the RVV ISA, which natively supports UNE
     // but no other unordered comparisons, and supports all ordered comparisons
@@ -423,33 +431,34 @@
         ISD::SETGT,  ISD::SETOGT, ISD::SETGE,  ISD::SETOGE,
     };
 
+    // Sets common operation actions on RVV floating-point vector types.
+    const auto SetCommonVFPActions = [&](MVT VT) {
+      setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
+      // Custom-lower insert/extract operations to simplify patterns.
+      setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
+      setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
+      for (auto CC : VFPCCToExpand)
+        setCondCodeAction(CC, VT, Expand);
+    };
+
     if (Subtarget.hasStdExtZfh()) {
       for (auto VT : {RISCVVMVTs::vfloat16mf4_t, RISCVVMVTs::vfloat16mf2_t,
                       RISCVVMVTs::vfloat16m1_t, RISCVVMVTs::vfloat16m2_t,
-                      RISCVVMVTs::vfloat16m4_t, RISCVVMVTs::vfloat16m8_t}) {
-        setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
-        for (auto CC : VFPCCToExpand)
-          setCondCodeAction(CC, VT, Expand);
-      }
+                      RISCVVMVTs::vfloat16m4_t, RISCVVMVTs::vfloat16m8_t})
+        SetCommonVFPActions(VT);
     }
 
     if (Subtarget.hasStdExtF()) {
       for (auto VT : {RISCVVMVTs::vfloat32mf2_t, RISCVVMVTs::vfloat32m1_t,
                       RISCVVMVTs::vfloat32m2_t, RISCVVMVTs::vfloat32m4_t,
-                      RISCVVMVTs::vfloat32m8_t}) {
-        setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
-        for (auto CC : VFPCCToExpand)
-          setCondCodeAction(CC, VT, Expand);
-      }
+                      RISCVVMVTs::vfloat32m8_t})
+        SetCommonVFPActions(VT);
     }
 
     if (Subtarget.hasStdExtD()) {
       for (auto VT : {RISCVVMVTs::vfloat64m1_t, RISCVVMVTs::vfloat64m2_t,
-                      RISCVVMVTs::vfloat64m4_t, RISCVVMVTs::vfloat64m8_t}) {
-        setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
-        for (auto CC : VFPCCToExpand)
-          setCondCodeAction(CC, VT, Expand);
-      }
+                      RISCVVMVTs::vfloat64m4_t, RISCVVMVTs::vfloat64m8_t})
+        SetCommonVFPActions(VT);
     }
   }
 
@@ -761,6 +770,10 @@
     return lowerVectorMaskExt(Op, DAG, /*ExtVal*/ -1);
   case ISD::SPLAT_VECTOR:
     return lowerSPLATVECTOR(Op, DAG);
+  case ISD::INSERT_VECTOR_ELT:
+    return lowerINSERT_VECTOR_ELT(Op, DAG);
+  case ISD::EXTRACT_VECTOR_ELT:
+    return lowerEXTRACT_VECTOR_ELT(Op, DAG);
   case ISD::VSCALE: {
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
@@ -1209,6 +1222,12 @@
                          DAG.getConstant(CVal->getSExtValue(), DL, MVT::i32));
   }
 
+  if (SplatVal.getOpcode() == ISD::SIGN_EXTEND &&
+      SplatVal.getOperand(0).getValueType() == MVT::i32) {
+    return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT,
+                       SplatVal.getOperand(0));
+  }
+
   // Else, on RV32 we lower an i64-element SPLAT_VECTOR thus, being careful not
   // to accidentally sign-extend the 32-bit halves to the e64 SEW:
   // vmv.v.x vX, hi
@@ -1306,6 +1325,72 @@
   return DAG.getSetCC(DL, MaskVT, Trunc, SplatZero, ISD::SETNE);
 }
 
+SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
+                                                    SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  EVT VecVT = Op.getValueType();
+  SDValue Vec = Op.getOperand(0);
+  SDValue Val = Op.getOperand(1);
+  SDValue Idx = Op.getOperand(2);
+
+  // Custom-legalize INSERT_VECTOR_ELT where XLEN>=SEW, so that the vector is
+  // first slid down into position, the value is inserted into the first
+  // position, and the vector is slid back up. We do this to simplify patterns.
+  //   (slideup vec, (insertelt (slidedown impdef, vec, idx), val, 0), idx),
+  if (Subtarget.is64Bit() || VecVT.getVectorElementType() != MVT::i64) {
+    if (isNullConstant(Idx))
+      return Op;
+    SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT,
+                                    DAG.getUNDEF(VecVT), Vec, Idx);
+    SDValue InsertElt0 =
+        DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecVT, Slidedown, Val,
+                    DAG.getConstant(0, DL, Subtarget.getXLenVT()));
+
+    return DAG.getNode(RISCVISD::VSLIDEUP, DL, VecVT, Vec, InsertElt0, Idx);
+  }
+
+  // Custom-legalize INSERT_VECTOR_ELT where XLEN<SEW, as the SEW element type
+  // is illegal (currently only vXi64 RV32).
+  // Since there is no easy way of getting a single element into a vector when
+  // XLEN<SEW, we lower the operation to the following sequence:
+  //   splat      vVal, rVal
+  //   vid.v      vVid
+  //   vmseq.vx   mMask, vVid, rIdx
+  //   vmerge.vvm vDest, vSrc, vVal, mMask
+  // This essentially merges the original vector with the inserted element by
+  // using a mask whose only set bit is that corresponding to the insert
+  // index.
+  SDValue SplattedVal = DAG.getSplatVector(VecVT, DL, Val);
+  SDValue SplattedIdx = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Idx);
+
+  SDValue VID = DAG.getNode(RISCVISD::VID, DL, VecVT);
+  auto SetCCVT =
+      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VecVT);
+  SDValue Mask = DAG.getSetCC(DL, SetCCVT, VID, SplattedIdx, ISD::SETEQ);
+
+  return DAG.getNode(ISD::VSELECT, DL, VecVT, Mask, SplattedVal, Vec);
+}
+
+// Custom-lower EXTRACT_VECTOR_ELT operations to slide the vector down, then
+// extract the first element: (extractelt (slidedown vec, idx), 0). This is
+// done to maintain partity with the legalization of RV32 vXi64 legalization.
+SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
+                                                     SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  SDValue Idx = Op.getOperand(1);
+  if (isNullConstant(Idx))
+    return Op;
+
+  SDValue Vec = Op.getOperand(0);
+  EVT EltVT = Op.getValueType();
+  EVT VecVT = Vec.getValueType();
+  SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT,
+                                  DAG.getUNDEF(VecVT), Vec, Idx);
+
+  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Slidedown,
+                     DAG.getConstant(0, DL, Subtarget.getXLenVT()));
+}
+
 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
@@ -1640,6 +1725,44 @@
     Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewOp));
     break;
   }
+  case ISD::EXTRACT_VECTOR_ELT: {
+    // Custom-legalize an EXTRACT_VECTOR_ELT where XLEN<SEW, as the SEW element
+    // type is illegal (currently only vXi64 RV32).
+    // With vmv.x.s, when SEW > XLEN, only the least-significant XLEN bits are
+    // transferred to the destination register. We issue two of these from the
+    // upper- and lower- halves of the SEW-bit vector element, slid down to the
+    // first element.
+    SDLoc DL(N);
+    SDValue Vec = N->getOperand(0);
+    SDValue Idx = N->getOperand(1);
+    EVT VecVT = Vec.getValueType();
+    assert(!Subtarget.is64Bit() && N->getValueType(0) == MVT::i64 &&
+           VecVT.getVectorElementType() == MVT::i64 &&
+           "Unexpected EXTRACT_VECTOR_ELT legalization");
+
+    SDValue Slidedown = Vec;
+    // Unless the index is known to be 0, we must slide the vector down to get
+    // the desired element into index 0.
+    if (!isNullConstant(Idx))
+      Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT,
+                              DAG.getUNDEF(VecVT), Vec, Idx);
+
+    MVT XLenVT = Subtarget.getXLenVT();
+    // Extract the lower XLEN bits of the correct vector element.
+    SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Slidedown, Idx);
+
+    // To extract the upper XLEN bits of the vector element, shift the first
+    // element right by 32 bits and re-extract the lower XLEN bits.
+    SDValue ThirtyTwoV =
+        DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT,
+                    DAG.getConstant(32, DL, Subtarget.getXLenVT()));
+    SDValue LShr32 = DAG.getNode(ISD::SRL, DL, VecVT, Slidedown, ThirtyTwoV);
+
+    SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32, Idx);
+
+    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi));
+    break;
+  }
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
     switch (IntNo) {
@@ -2231,8 +2354,12 @@
     return 33;
   case RISCVISD::VMV_X_S:
     // The number of sign bits of the scalar result is computed by obtaining the
-    // element type of the input vector operand, substracting its width from the
-    // XLEN, and then adding one (sign bit within the element type).
+    // element type of the input vector operand, subtracting its width from the
+    // XLEN, and then adding one (sign bit within the element type). If the
+    // element type is wider than XLen, the least-significant XLEN bits are
+    // taken.
+    if (Op.getOperand(0).getScalarValueSizeInBits() > Subtarget.getXLen())
+      return 1;
     return Subtarget.getXLen() - Op.getOperand(0).getScalarValueSizeInBits() + 1;
   }
 
@@ -3893,6 +4020,9 @@
   NODE_NAME_CASE(VLEFF)
   NODE_NAME_CASE(VLEFF_MASK)
   NODE_NAME_CASE(READ_VL)
+  NODE_NAME_CASE(VSLIDEUP)
+  NODE_NAME_CASE(VSLIDEDOWN)
+  NODE_NAME_CASE(VID)
   }
   // clang-format on
   return nullptr;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -32,6 +32,15 @@
                                 SDTypeProfile<1, 1,
                                  [SDTCisVec<0>, SDTCisVec<1>]>>;
 
+class FromFPR32<DAGOperand operand, dag input_dag> {
+  dag ret = !cond(!eq(!cast<string>(operand), !cast<string>(FPR64)):
+                     (INSERT_SUBREG (IMPLICIT_DEF), input_dag, sub_32),
+                  !eq(!cast<string>(operand), !cast<string>(FPR16)):
+                      (EXTRACT_SUBREG input_dag, sub_16),
+                  !eq(1, 1):
+                    input_dag);
+}
+
 // Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants
 // precedence
 def SplatPat       : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
@@ -538,3 +547,101 @@
               0, fvti.AVL, fvti.SEW)>;
 }
 } // Predicates = [HasStdExtV, HasStdExtF]
+
+//===----------------------------------------------------------------------===//
+// Vector Element Inserts/Extracts
+//===----------------------------------------------------------------------===//
+
+// The built-in TableGen 'extractelt' and 'insertelt' nodes must return the
+// same type as the vector element type. On RISC-V, XLenVT is the only legal
+// integer type, so for integer inserts/extracts we use a custom node which
+// returns XLenVT.
+def riscv_insert_vector_elt
+    : SDNode<"ISD::INSERT_VECTOR_ELT",
+             SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, XLenVT>,
+                                  SDTCisPtrTy<3>]>, []>;
+def riscv_extract_vector_elt
+    : SDNode<"ISD::EXTRACT_VECTOR_ELT",
+             SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisPtrTy<2>]>, []>;
+
+multiclass VPatInsertExtractElt_XI_Idx<bit IsFloat> {
+  defvar vtilist = !if(IsFloat, AllFloatVectors, AllIntegerVectors);
+  defvar insertelt_node = !if(IsFloat, insertelt, riscv_insert_vector_elt);
+  defvar extractelt_node = !if(IsFloat, extractelt, riscv_extract_vector_elt);
+  foreach vti = vtilist in {
+    defvar MX = vti.LMul.MX;
+    defvar vmv_xf_s_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_F_S_",
+                                                           "PseudoVMV_X_S_")#MX);
+    defvar vmv_s_xf_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_S_F_",
+                                                           "PseudoVMV_S_X_")#MX);
+    // Only pattern-match insert/extract-element operations where the index is
+    // 0. Any other index will have been custom-lowered to slide the vector
+    // correctly into place (and, in the case of insert, slide it back again
+    // afterwards).
+    def : Pat<(vti.Scalar (extractelt_node (vti.Vector vti.RegClass:$rs2), 0)),
+              FromFPR32<vti.ScalarRegClass,
+                       (vmv_xf_s_inst vti.RegClass:$rs2, vti.SEW)>.ret>;
+
+    def : Pat<(vti.Vector (insertelt_node (vti.Vector vti.RegClass:$merge),
+                                          vti.ScalarRegClass:$rs1, 0)),
+              (vmv_s_xf_inst vti.RegClass:$merge,
+                      ToFPR32<vti.Scalar, vti.ScalarRegClass, "rs1">.ret,
+                      vti.AVL, vti.SEW)>;
+  }
+}
+
+let Predicates = [HasStdExtV] in
+defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/0>;
+let Predicates = [HasStdExtV, HasStdExtF] in
+defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/1>;
+
+//===----------------------------------------------------------------------===//
+// Miscellaneous RISCVISD SDNodes
+//===----------------------------------------------------------------------===//
+
+def riscv_vid
+    : SDNode<"RISCVISD::VID", SDTypeProfile<1, 0, [SDTCisVec<0>]>, []>;
+
+def SDTRVVSlide : SDTypeProfile<1, 3, [
+  SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>
+]>;
+
+def riscv_slideup : SDNode<"RISCVISD::VSLIDEUP", SDTRVVSlide, []>;
+def riscv_slidedown : SDNode<"RISCVISD::VSLIDEDOWN", SDTRVVSlide, []>;
+
+let Predicates = [HasStdExtV] in {
+
+foreach vti = AllIntegerVectors in
+  def : Pat<(vti.Vector riscv_vid),
+            (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) vti.AVL, vti.SEW)>;
+
+foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in {
+    def : Pat<(vti.Vector (riscv_slideup (vti.Vector vti.RegClass:$rs3),
+                                         (vti.Vector vti.RegClass:$rs1),
+                                         uimm5:$rs2)),
+              (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX)
+                  vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2,
+                  vti.AVL, vti.SEW)>;
+
+    def : Pat<(vti.Vector (riscv_slideup (vti.Vector vti.RegClass:$rs3),
+                                         (vti.Vector vti.RegClass:$rs1),
+                                         GPR:$rs2)),
+              (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX)
+                  vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2,
+                  vti.AVL, vti.SEW)>;
+
+    def : Pat<(vti.Vector (riscv_slidedown (vti.Vector vti.RegClass:$rs3),
+                                           (vti.Vector vti.RegClass:$rs1),
+                                           uimm5:$rs2)),
+              (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX)
+                  vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2,
+                  vti.AVL, vti.SEW)>;
+
+    def : Pat<(vti.Vector (riscv_slidedown (vti.Vector vti.RegClass:$rs3),
+                                           (vti.Vector vti.RegClass:$rs1),
+                                           GPR:$rs2)),
+              (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX)
+                  vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2,
+                  vti.AVL, vti.SEW)>;
+}
+} // Predicates = [HasStdExtV]
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
@@ -0,0 +1,502 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) {
+; CHECK-LABEL: extractelt_nxv1f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
+; CHECK-LABEL: extractelt_nxv1f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv1f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) {
+; CHECK-LABEL: extractelt_nxv2f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
+; CHECK-LABEL: extractelt_nxv2f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv2f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) {
+; CHECK-LABEL: extractelt_nxv4f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
+; CHECK-LABEL: extractelt_nxv4f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv4f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) {
+; CHECK-LABEL: extractelt_nxv8f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
+; CHECK-LABEL: extractelt_nxv8f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv8f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) {
+; CHECK-LABEL: extractelt_nxv16f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
+; CHECK-LABEL: extractelt_nxv16f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv16f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) {
+; CHECK-LABEL: extractelt_nxv32f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) {
+; CHECK-LABEL: extractelt_nxv32f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv32f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x half> %v, i32 %idx
+  ret half %r
+}
+
+define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) {
+; CHECK-LABEL: extractelt_nxv1f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv1f32_imm(<vscale x 1 x float> %v) {
+; CHECK-LABEL: extractelt_nxv1f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv1f32_idx(<vscale x 1 x float> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv1f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x float> %v, i32 %idx
+  ret float %r
+}
+
+define float @extractelt_nxv2f32_0(<vscale x 2 x float> %v) {
+; CHECK-LABEL: extractelt_nxv2f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv2f32_imm(<vscale x 2 x float> %v) {
+; CHECK-LABEL: extractelt_nxv2f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv2f32_idx(<vscale x 2 x float> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv2f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x float> %v, i32 %idx
+  ret float %r
+}
+
+define float @extractelt_nxv4f32_0(<vscale x 4 x float> %v) {
+; CHECK-LABEL: extractelt_nxv4f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv4f32_imm(<vscale x 4 x float> %v) {
+; CHECK-LABEL: extractelt_nxv4f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv4f32_idx(<vscale x 4 x float> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv4f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x float> %v, i32 %idx
+  ret float %r
+}
+
+define float @extractelt_nxv8f32_0(<vscale x 8 x float> %v) {
+; CHECK-LABEL: extractelt_nxv8f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv8f32_imm(<vscale x 8 x float> %v) {
+; CHECK-LABEL: extractelt_nxv8f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv8f32_idx(<vscale x 8 x float> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv8f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x float> %v, i32 %idx
+  ret float %r
+}
+
+define float @extractelt_nxv16f32_0(<vscale x 16 x float> %v) {
+; CHECK-LABEL: extractelt_nxv16f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv16f32_imm(<vscale x 16 x float> %v) {
+; CHECK-LABEL: extractelt_nxv16f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv16f32_idx(<vscale x 16 x float> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv16f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x float> %v, i32 %idx
+  ret float %r
+}
+
+define double @extractelt_nxv1f64_0(<vscale x 1 x double> %v) {
+; CHECK-LABEL: extractelt_nxv1f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x double> %v, i32 0
+  ret double %r
+}
+
+define double @extractelt_nxv1f64_imm(<vscale x 1 x double> %v) {
+; CHECK-LABEL: extractelt_nxv1f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x double> %v, i32 2
+  ret double %r
+}
+
+define double @extractelt_nxv1f64_idx(<vscale x 1 x double> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv1f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x double> %v, i32 %idx
+  ret double %r
+}
+
+define double @extractelt_nxv2f64_0(<vscale x 2 x double> %v) {
+; CHECK-LABEL: extractelt_nxv2f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x double> %v, i32 0
+  ret double %r
+}
+
+define double @extractelt_nxv2f64_imm(<vscale x 2 x double> %v) {
+; CHECK-LABEL: extractelt_nxv2f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x double> %v, i32 2
+  ret double %r
+}
+
+define double @extractelt_nxv2f64_idx(<vscale x 2 x double> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv2f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x double> %v, i32 %idx
+  ret double %r
+}
+
+define double @extractelt_nxv4f64_0(<vscale x 4 x double> %v) {
+; CHECK-LABEL: extractelt_nxv4f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x double> %v, i32 0
+  ret double %r
+}
+
+define double @extractelt_nxv4f64_imm(<vscale x 4 x double> %v) {
+; CHECK-LABEL: extractelt_nxv4f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x double> %v, i32 2
+  ret double %r
+}
+
+define double @extractelt_nxv4f64_idx(<vscale x 4 x double> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv4f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x double> %v, i32 %idx
+  ret double %r
+}
+
+define double @extractelt_nxv8f64_0(<vscale x 8 x double> %v) {
+; CHECK-LABEL: extractelt_nxv8f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x double> %v, i32 0
+  ret double %r
+}
+
+define double @extractelt_nxv8f64_imm(<vscale x 8 x double> %v) {
+; CHECK-LABEL: extractelt_nxv8f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x double> %v, i32 2
+  ret double %r
+}
+
+define double @extractelt_nxv8f64_idx(<vscale x 8 x double> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv8f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x double> %v, i32 %idx
+  ret double %r
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
@@ -0,0 +1,502 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) {
+; CHECK-LABEL: extractelt_nxv1f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
+; CHECK-LABEL: extractelt_nxv1f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv1f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) {
+; CHECK-LABEL: extractelt_nxv2f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
+; CHECK-LABEL: extractelt_nxv2f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv2f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) {
+; CHECK-LABEL: extractelt_nxv4f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
+; CHECK-LABEL: extractelt_nxv4f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv4f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) {
+; CHECK-LABEL: extractelt_nxv8f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
+; CHECK-LABEL: extractelt_nxv8f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv8f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) {
+; CHECK-LABEL: extractelt_nxv16f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
+; CHECK-LABEL: extractelt_nxv16f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv16f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x half> %v, i32 %idx
+  ret half %r
+}
+
+define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) {
+; CHECK-LABEL: extractelt_nxv32f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x half> %v, i32 0
+  ret half %r
+}
+
+define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) {
+; CHECK-LABEL: extractelt_nxv32f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x half> %v, i32 2
+  ret half %r
+}
+
+define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv32f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h killed $f10_f
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x half> %v, i32 %idx
+  ret half %r
+}
+
+define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) {
+; CHECK-LABEL: extractelt_nxv1f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv1f32_imm(<vscale x 1 x float> %v) {
+; CHECK-LABEL: extractelt_nxv1f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv1f32_idx(<vscale x 1 x float> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv1f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x float> %v, i32 %idx
+  ret float %r
+}
+
+define float @extractelt_nxv2f32_0(<vscale x 2 x float> %v) {
+; CHECK-LABEL: extractelt_nxv2f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv2f32_imm(<vscale x 2 x float> %v) {
+; CHECK-LABEL: extractelt_nxv2f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv2f32_idx(<vscale x 2 x float> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv2f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x float> %v, i32 %idx
+  ret float %r
+}
+
+define float @extractelt_nxv4f32_0(<vscale x 4 x float> %v) {
+; CHECK-LABEL: extractelt_nxv4f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv4f32_imm(<vscale x 4 x float> %v) {
+; CHECK-LABEL: extractelt_nxv4f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv4f32_idx(<vscale x 4 x float> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv4f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x float> %v, i32 %idx
+  ret float %r
+}
+
+define float @extractelt_nxv8f32_0(<vscale x 8 x float> %v) {
+; CHECK-LABEL: extractelt_nxv8f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv8f32_imm(<vscale x 8 x float> %v) {
+; CHECK-LABEL: extractelt_nxv8f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv8f32_idx(<vscale x 8 x float> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv8f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x float> %v, i32 %idx
+  ret float %r
+}
+
+define float @extractelt_nxv16f32_0(<vscale x 16 x float> %v) {
+; CHECK-LABEL: extractelt_nxv16f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x float> %v, i32 0
+  ret float %r
+}
+
+define float @extractelt_nxv16f32_imm(<vscale x 16 x float> %v) {
+; CHECK-LABEL: extractelt_nxv16f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x float> %v, i32 2
+  ret float %r
+}
+
+define float @extractelt_nxv16f32_idx(<vscale x 16 x float> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv16f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x float> %v, i32 %idx
+  ret float %r
+}
+
+define double @extractelt_nxv1f64_0(<vscale x 1 x double> %v) {
+; CHECK-LABEL: extractelt_nxv1f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x double> %v, i32 0
+  ret double %r
+}
+
+define double @extractelt_nxv1f64_imm(<vscale x 1 x double> %v) {
+; CHECK-LABEL: extractelt_nxv1f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x double> %v, i32 2
+  ret double %r
+}
+
+define double @extractelt_nxv1f64_idx(<vscale x 1 x double> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv1f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x double> %v, i32 %idx
+  ret double %r
+}
+
+define double @extractelt_nxv2f64_0(<vscale x 2 x double> %v) {
+; CHECK-LABEL: extractelt_nxv2f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x double> %v, i32 0
+  ret double %r
+}
+
+define double @extractelt_nxv2f64_imm(<vscale x 2 x double> %v) {
+; CHECK-LABEL: extractelt_nxv2f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x double> %v, i32 2
+  ret double %r
+}
+
+define double @extractelt_nxv2f64_idx(<vscale x 2 x double> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv2f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x double> %v, i32 %idx
+  ret double %r
+}
+
+define double @extractelt_nxv4f64_0(<vscale x 4 x double> %v) {
+; CHECK-LABEL: extractelt_nxv4f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x double> %v, i32 0
+  ret double %r
+}
+
+define double @extractelt_nxv4f64_imm(<vscale x 4 x double> %v) {
+; CHECK-LABEL: extractelt_nxv4f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x double> %v, i32 2
+  ret double %r
+}
+
+define double @extractelt_nxv4f64_idx(<vscale x 4 x double> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv4f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x double> %v, i32 %idx
+  ret double %r
+}
+
+define double @extractelt_nxv8f64_0(<vscale x 8 x double> %v) {
+; CHECK-LABEL: extractelt_nxv8f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x double> %v, i32 0
+  ret double %r
+}
+
+define double @extractelt_nxv8f64_imm(<vscale x 8 x double> %v) {
+; CHECK-LABEL: extractelt_nxv8f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x double> %v, i32 2
+  ret double %r
+}
+
+define double @extractelt_nxv8f64_idx(<vscale x 8 x double> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv8f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x double> %v, i32 %idx
+  ret double %r
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
@@ -0,0 +1,744 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv1i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv1i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv2i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv2i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv4i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv4i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv8i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv8i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv16i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv16i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv32i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv32i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 64 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv64i8_imm(<vscale x 64 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv64i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 64 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv64i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 64 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv1i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv1i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv2i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv2i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv4i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv4i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv8i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv8i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv16i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv16i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv32i16_imm(<vscale x 32 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv32i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv32i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv1i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv1i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv2i32_0(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv2i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv2i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv4i32_0(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv4i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv4i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv8i32_0(<vscale x 8 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv8i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv8i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv16i32_0(<vscale x 16 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv16i32_imm(<vscale x 16 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv16i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv16i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i64 @extractelt_nxv1i64_0(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i64> %v, i32 0
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv1i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i64> %v, i32 2
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv1i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v25, v25, a1
+; CHECK-NEXT:    vmv.x.s a1, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i64> %v, i32 %idx
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv2i64_0(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a1, v26
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i64> %v, i32 0
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv2i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vmv.x.s a1, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i64> %v, i32 2
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv2i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vmv.x.s a1, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i64> %v, i32 %idx
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv4i64_0(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a1, v28
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i64> %v, i32 0
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv4i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vmv.x.s a1, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i64> %v, i32 2
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv4i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vmv.x.s a1, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i64> %v, i32 %idx
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv8i64_0(<vscale x 8 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v8, a0
+; CHECK-NEXT:    vmv.x.s a1, v16
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i64> %v, i32 0
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv8i64_imm(<vscale x 8 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv8i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v8, v8, a1
+; CHECK-NEXT:    vmv.x.s a1, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i64> %v, i32 2
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 %idx) {
+; CHECK-LABEL: extractelt_nxv8i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsrl.vx v8, v8, a1
+; CHECK-NEXT:    vmv.x.s a1, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i64> %v, i32 %idx
+  ret i64 %r
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
@@ -0,0 +1,708 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv1i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv1i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv2i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv2i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv4i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv4i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv8i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv8i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv16i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv16i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv32i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv32i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 64 x i8> %v, i32 0
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv64i8_imm(<vscale x 64 x i8> %v) {
+; CHECK-LABEL: extractelt_nxv64i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 64 x i8> %v, i32 2
+  ret i8 %r
+}
+
+define i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv64i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 64 x i8> %v, i32 %idx
+  ret i8 %r
+}
+
+define i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv1i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv1i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv2i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv2i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv4i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv4i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv8i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv8i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv16i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv16i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i16> %v, i32 0
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv32i16_imm(<vscale x 32 x i16> %v) {
+; CHECK-LABEL: extractelt_nxv32i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i16> %v, i32 2
+  ret i16 %r
+}
+
+define i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv32i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 32 x i16> %v, i32 %idx
+  ret i16 %r
+}
+
+define i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv1i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv1i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv2i32_0(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv2i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv2i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv4i32_0(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv4i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv4i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv8i32_0(<vscale x 8 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv8i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv8i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv16i32_0(<vscale x 16 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i32> %v, i32 0
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv16i32_imm(<vscale x 16 x i32> %v) {
+; CHECK-LABEL: extractelt_nxv16i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i32> %v, i32 2
+  ret i32 %r
+}
+
+define i32 @extractelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv16i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 16 x i32> %v, i32 %idx
+  ret i32 %r
+}
+
+define i64 @extractelt_nxv1i64_0(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i64> %v, i32 0
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv1i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i64> %v, i32 2
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv1i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v25
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 1 x i64> %v, i32 %idx
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv2i64_0(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i64> %v, i32 0
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv2i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i64> %v, i32 2
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv2i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v26
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 2 x i64> %v, i32 %idx
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv4i64_0(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i64> %v, i32 0
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv4i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i64> %v, i32 2
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv4i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v28
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 4 x i64> %v, i32 %idx
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv8i64_0(<vscale x 8 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i64> %v, i32 0
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv8i64_imm(<vscale x 8 x i64> %v) {
+; CHECK-LABEL: extractelt_nxv8i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v8, v8, 2
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i64> %v, i32 2
+  ret i64 %r
+}
+
+define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 signext %idx) {
+; CHECK-LABEL: extractelt_nxv8i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v8, v8, a0
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %r = extractelement <vscale x 8 x i64> %v, i32 %idx
+  ret i64 %r
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
@@ -0,0 +1,562 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv1f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x half> %v, half %elt, i32 0
+  ret <vscale x 1 x half> %r
+}
+
+define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv1f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
+  ret <vscale x 1 x half> %r
+}
+
+define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
+  ret <vscale x 1 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv2f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
+  ret <vscale x 2 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv2f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
+  ret <vscale x 2 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
+  ret <vscale x 2 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv4f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
+  ret <vscale x 4 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv4f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
+  ret <vscale x 4 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
+  ret <vscale x 4 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv8f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
+  ret <vscale x 8 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv8f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
+  ret <vscale x 8 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
+  ret <vscale x 8 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv16f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
+  ret <vscale x 16 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv16f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
+  ret <vscale x 16 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv16f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
+  ret <vscale x 16 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv32f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
+  ret <vscale x 32 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv32f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x half> %v, half %elt, i32 3
+  ret <vscale x 32 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv32f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
+  ret <vscale x 32 x half> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv1f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x float> %v, float %elt, i32 0
+  ret <vscale x 1 x float> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv1f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x float> %v, float %elt, i32 3
+  ret <vscale x 1 x float> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
+  ret <vscale x 1 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv2f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x float> %v, float %elt, i32 0
+  ret <vscale x 2 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv2f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x float> %v, float %elt, i32 3
+  ret <vscale x 2 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
+  ret <vscale x 2 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv4f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x float> %v, float %elt, i32 0
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv4f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x float> %v, float %elt, i32 3
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, float %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv8f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x float> %v, float %elt, i32 0
+  ret <vscale x 8 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv8f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x float> %v, float %elt, i32 3
+  ret <vscale x 8 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, float %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
+  ret <vscale x 8 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv16f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x float> %v, float %elt, i32 0
+  ret <vscale x 16 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv16f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x float> %v, float %elt, i32 3
+  ret <vscale x 16 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_idx(<vscale x 16 x float> %v, float %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv16f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx
+  ret <vscale x 16 x float> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv1f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x double> %v, double %elt, i32 0
+  ret <vscale x 1 x double> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv1f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x double> %v, double %elt, i32 3
+  ret <vscale x 1 x double> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
+  ret <vscale x 1 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv2f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x double> %v, double %elt, i32 0
+  ret <vscale x 2 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv2f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x double> %v, double %elt, i32 3
+  ret <vscale x 2 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, double %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
+  ret <vscale x 2 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv4f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x double> %v, double %elt, i32 0
+  ret <vscale x 4 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv4f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x double> %v, double %elt, i32 3
+  ret <vscale x 4 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, double %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
+  ret <vscale x 4 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv8f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x double> %v, double %elt, i32 0
+  ret <vscale x 8 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv8f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x double> %v, double %elt, i32 3
+  ret <vscale x 8 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_idx(<vscale x 8 x double> %v, double %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x double> %v, double %elt, i32 %idx
+  ret <vscale x 8 x double> %r
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
@@ -0,0 +1,562 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv1f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x half> %v, half %elt, i32 0
+  ret <vscale x 1 x half> %r
+}
+
+define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv1f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
+  ret <vscale x 1 x half> %r
+}
+
+define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
+  ret <vscale x 1 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv2f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
+  ret <vscale x 2 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv2f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
+  ret <vscale x 2 x half> %r
+}
+
+define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
+  ret <vscale x 2 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv4f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
+  ret <vscale x 4 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv4f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
+  ret <vscale x 4 x half> %r
+}
+
+define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
+  ret <vscale x 4 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv8f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
+  ret <vscale x 8 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv8f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
+  ret <vscale x 8 x half> %r
+}
+
+define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
+  ret <vscale x 8 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv16f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
+  ret <vscale x 16 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv16f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
+  ret <vscale x 16 x half> %r
+}
+
+define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
+  ret <vscale x 16 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv32f16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
+  ret <vscale x 32 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
+; CHECK-LABEL: insertelt_nxv32f16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x half> %v, half %elt, i32 3
+  ret <vscale x 32 x half> %r
+}
+
+define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv32f16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $f10_h killed $f10_h def $f10_f
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
+  ret <vscale x 32 x half> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv1f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x float> %v, float %elt, i32 0
+  ret <vscale x 1 x float> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv1f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x float> %v, float %elt, i32 3
+  ret <vscale x 1 x float> %r
+}
+
+define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
+  ret <vscale x 1 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv2f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x float> %v, float %elt, i32 0
+  ret <vscale x 2 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv2f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x float> %v, float %elt, i32 3
+  ret <vscale x 2 x float> %r
+}
+
+define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
+  ret <vscale x 2 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv4f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x float> %v, float %elt, i32 0
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv4f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x float> %v, float %elt, i32 3
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, float %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv8f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x float> %v, float %elt, i32 0
+  ret <vscale x 8 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv8f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x float> %v, float %elt, i32 3
+  ret <vscale x 8 x float> %r
+}
+
+define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, float %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
+  ret <vscale x 8 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv16f32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x float> %v, float %elt, i32 0
+  ret <vscale x 16 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) {
+; CHECK-LABEL: insertelt_nxv16f32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x float> %v, float %elt, i32 3
+  ret <vscale x 16 x float> %r
+}
+
+define <vscale x 16 x float> @insertelt_nxv16f32_idx(<vscale x 16 x float> %v, float %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16f32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx
+  ret <vscale x 16 x float> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv1f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x double> %v, double %elt, i32 0
+  ret <vscale x 1 x double> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv1f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x double> %v, double %elt, i32 3
+  ret <vscale x 1 x double> %r
+}
+
+define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a0
+; CHECK-NEXT:    vfmv.s.f v25, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
+  ret <vscale x 1 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv2f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x double> %v, double %elt, i32 0
+  ret <vscale x 2 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv2f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x double> %v, double %elt, i32 3
+  ret <vscale x 2 x double> %r
+}
+
+define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, double %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a0
+; CHECK-NEXT:    vfmv.s.f v26, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
+  ret <vscale x 2 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv4f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x double> %v, double %elt, i32 0
+  ret <vscale x 4 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv4f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x double> %v, double %elt, i32 3
+  ret <vscale x 4 x double> %r
+}
+
+define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, double %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a0
+; CHECK-NEXT:    vfmv.s.f v28, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
+  ret <vscale x 4 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv8f64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vfmv.s.f v8, fa0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x double> %v, double %elt, i32 0
+  ret <vscale x 8 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) {
+; CHECK-LABEL: insertelt_nxv8f64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x double> %v, double %elt, i32 3
+  ret <vscale x 8 x double> %r
+}
+
+define <vscale x 8 x double> @insertelt_nxv8f64_idx(<vscale x 8 x double> %v, double %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8f64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a0
+; CHECK-NEXT:    vfmv.s.f v16, fa0
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x double> %v, double %elt, i32 %idx
+  ret <vscale x 8 x double> %r
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
@@ -0,0 +1,952 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a1
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv32i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a1
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv64i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv64i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a1
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a1
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a1
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv32i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a1
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv1i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv2i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv4i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a1
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv8i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a1
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 %elt) {
+; CHECK-LABEL: insertelt_nxv16i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv16i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a1
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vi v0, v26, 0
+; CHECK-NEXT:    vmerge.vvm v8, v8, v25, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv1i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vi v0, v26, 3
+; CHECK-NEXT:    vmerge.vvm v8, v8, v25, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vx v0, v26, a2
+; CHECK-NEXT:    vmerge.vvm v8, v8, v25, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vid.v v28
+; CHECK-NEXT:    vmseq.vi v0, v28, 0
+; CHECK-NEXT:    vmerge.vvm v8, v8, v26, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv2i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vid.v v28
+; CHECK-NEXT:    vmseq.vi v0, v28, 3
+; CHECK-NEXT:    vmerge.vvm v8, v8, v26, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vid.v v28
+; CHECK-NEXT:    vmseq.vx v0, v28, a2
+; CHECK-NEXT:    vmerge.vvm v8, v8, v26, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vsll.vx v12, v12, a1
+; CHECK-NEXT:    vsrl.vx v12, v12, a1
+; CHECK-NEXT:    vor.vv v28, v12, v28
+; CHECK-NEXT:    vid.v v12
+; CHECK-NEXT:    vmseq.vi v0, v12, 0
+; CHECK-NEXT:    vmerge.vvm v8, v8, v28, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv4i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vsll.vx v12, v12, a1
+; CHECK-NEXT:    vsrl.vx v12, v12, a1
+; CHECK-NEXT:    vor.vv v28, v12, v28
+; CHECK-NEXT:    vid.v v12
+; CHECK-NEXT:    vmseq.vi v0, v12, 3
+; CHECK-NEXT:    vmerge.vvm v8, v8, v28, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    vsll.vx v12, v12, a1
+; CHECK-NEXT:    vsrl.vx v12, v12, a1
+; CHECK-NEXT:    vor.vv v28, v12, v28
+; CHECK-NEXT:    vid.v v12
+; CHECK-NEXT:    vmseq.vx v0, v12, a2
+; CHECK-NEXT:    vmerge.vvm v8, v8, v28, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v16, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v16, v16, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v16, v24, v16
+; CHECK-NEXT:    vid.v v24
+; CHECK-NEXT:    vmseq.vi v0, v24, 0
+; CHECK-NEXT:    vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0
+  ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv8i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v16, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v16, v16, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v16, v24, v16
+; CHECK-NEXT:    vid.v v24
+; CHECK-NEXT:    vmseq.vi v0, v24, 3
+; CHECK-NEXT:    vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3
+  ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v16, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v16, v16, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v16, v24, v16
+; CHECK-NEXT:    vid.v v24
+; CHECK-NEXT:    vmseq.vx v0, v24, a2
+; CHECK-NEXT:    vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx
+  ret <vscale x 8 x i64> %r
+}
+
+; Extra tests to check lowering of constant values
+define <vscale x 2 x i64> @insertelt_nxv2i64_0_c10(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: insertelt_nxv2i64_0_c10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vi v0, v26, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 10, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 0
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_imm_c10(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: insertelt_nxv2i64_imm_c10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vi v0, v26, 3
+; CHECK-NEXT:    vmerge.vim v8, v8, 10, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 3
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_idx_c10(<vscale x 2 x i64> %v, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i64_idx_c10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vx v0, v26, a0
+; CHECK-NEXT:    vmerge.vim v8, v8, 10, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 %idx
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_0_cn1(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: insertelt_nxv2i64_0_cn1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vi v0, v26, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 0
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_imm_cn1(<vscale x 2 x i64> %v) {
+; CHECK-LABEL: insertelt_nxv2i64_imm_cn1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vi v0, v26, 3
+; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 3
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_idx_cn1(<vscale x 2 x i64> %v, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i64_idx_cn1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vid.v v26
+; CHECK-NEXT:    vmseq.vx v0, v26, a0
+; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 %idx
+  ret <vscale x 2 x i64> %r
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
@@ -0,0 +1,800 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 1 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 2 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 4 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 8 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a1
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv32i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a1
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 32 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {
+; CHECK-LABEL: insertelt_nxv64i8_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv64i8_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a1
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx
+  ret <vscale x 64 x i8> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 1 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 2 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 4 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a1
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a1
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 16 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {
+; CHECK-LABEL: insertelt_nxv32i16_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv32i16_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a1
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx
+  ret <vscale x 32 x i16> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv1i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv1i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 1 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv2i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv2i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 2 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv4i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv4i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a1
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv8i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv8i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a1
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 8 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 signext %elt) {
+; CHECK-LABEL: insertelt_nxv16i32_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 signext %elt, i32 signext %idx) {
+; CHECK-LABEL: insertelt_nxv16i32_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a1
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx
+  ret <vscale x 16 x i32> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv1i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v8, 3
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v25, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv1i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sext.w a1, a1
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vx v25, v8, a1
+; CHECK-NEXT:    vmv.s.x v25, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v25, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
+  ret <vscale x 1 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv2i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vi v26, v8, 3
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v26, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv2i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sext.w a1, a1
+; CHECK-NEXT:    vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vslidedown.vx v26, v8, a1
+; CHECK-NEXT:    vmv.s.x v26, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v26, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
+  ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv4i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vi v28, v8, 3
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v28, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv4i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sext.w a1, a1
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vslidedown.vx v28, v8, a1
+; CHECK-NEXT:    vmv.s.x v28, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v28, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
+  ret <vscale x 4 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.s.x v8, a0
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0
+  ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {
+; CHECK-LABEL: insertelt_nxv8i64_imm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vi v16, v8, 3
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,tu,mu
+; CHECK-NEXT:    vslideup.vi v8, v16, 3
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3
+  ret <vscale x 8 x i64> %r
+}
+
+define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) {
+; CHECK-LABEL: insertelt_nxv8i64_idx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sext.w a1, a1
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vslidedown.vx v16, v8, a1
+; CHECK-NEXT:    vmv.s.x v16, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,tu,mu
+; CHECK-NEXT:    vslideup.vx v8, v16, a1
+; CHECK-NEXT:    ret
+  %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx
+  ret <vscale x 8 x i64> %r
+}
+