[RISCV] Update V extension to v1.0-draft 08a0b464.

[HsiangKai]

Summary

D93611, D93612, D93613, and D93614 have been reviewed and accepted. I change the version number of vector extension to v1.020201218, i.e., append the date of commit 08a0b464 in riscv-v-spec to v1.0.

Currently, there is no v1.0 tag in riscv-v-spec. That is why I use the date of the commit as the draft version number. We hope v1.0 could be merged into LLVM 12. I am not sure whether it is an acceptable way to do it or not.

[HsiangKai]

Use v1.0 instead of strange version number. It is under -enable-experimental-extensions. So, I think it should be ok to do this.

[craig.topper]

LGTM

[jrtc27]

There are a lot of "Resolve for v1.0" issues open against the spec still. Are we sure we want to brand this as 1.0? It will end up as such in the ELF attributes and thus be deemed compatible with future "real" 1.0 binaries.

[HsiangKai]

In D94583#2513070, @jrtc27 wrote:

There are a lot of "Resolve for v1.0" issues open against the spec still. Are we sure we want to brand this as 1.0? It will end up as such in the ELF attributes and thus be deemed compatible with future "real" 1.0 binaries.

We could keep the version number as v0.9 or do you think it is better to keep it as v1.020201218.

[jrtc27]

In D94583#2513915, @HsiangKai wrote:

In D94583#2513070, @jrtc27 wrote:

There are a lot of "Resolve for v1.0" issues open against the spec still. Are we sure we want to brand this as 1.0? It will end up as such in the ELF attributes and thus be deemed compatible with future "real" 1.0 binaries.

We could keep the version number as v0.9 or do you think it is better to keep it as v1.020201218.

You don't want it to be higher than 1.0 either as that would be newer than the future actual 1.0.

[jrtc27]

(Their problem stems from having 1.0 drafts before they've resolved all the outstanding issues and frozen the instruction set; if they didn't jump the gun then things would be saner for people implementing it)

[kito-cheng]

@jrtc27 just let you know I have same concern too, that's one major reason why we don't upstream those extension on GNU toolchain... we are intend to introduce an internal revision number on ELF attribute in near future, e.g. v-ext 0.9.1 / v0p9p1 to prevent compatible issue here.

[HsiangKai]

In D94583#2514434, @jrtc27 wrote:

In D94583#2513915, @HsiangKai wrote:

In D94583#2513070, @jrtc27 wrote:

There are a lot of "Resolve for v1.0" issues open against the spec still. Are we sure we want to brand this as 1.0? It will end up as such in the ELF attributes and thus be deemed compatible with future "real" 1.0 binaries.

We could keep the version number as v0.9 or do you think it is better to keep it as v1.020201218.

You don't want it to be higher than 1.0 either as that would be newer than the future actual 1.0.

Vector extension is under -enable-experimental-extensions in LLVM. Could we change the version number to v1.0 to align with current V specification? "Experimental v1.0" should be more consistent with "v1.0-draft" V specification. What do you think?

[kito-cheng]

Could you also update macros and attributes which implemented in https://reviews.llvm.org/D94403 and https://reviews.llvm.org/D94931

[HsiangKai]

Rebase.

[evandro]

Also, when the V spec becomes official, it'll be labeled v2.0. Therefore, as long as v0.9 or v1.0 is implemented, V is only available as an experimental feature.

clang/lib/Basic/Targets/RISCV.cpp

void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
   }
 
   if (HasB) {
     Builder.defineMacro("__riscv_b", "93000");
     Builder.defineMacro("__riscv_bitmanip");
   }
 
   if (HasV) {
-    Builder.defineMacro("__riscv_v", "9000");
+    Builder.defineMacro("__riscv_v", "1000000");
     Builder.defineMacro("__riscv_vector");
   }
 
   if (HasZba)
     Builder.defineMacro("__riscv_zba", "93000");
 
   if (HasZbb)
     Builder.defineMacro("__riscv_zbb", "93000");
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
 
   if (HasZbt)
     Builder.defineMacro("__riscv_zbt", "93000");
 
   if (HasZfh)
     Builder.defineMacro("__riscv_zfh", "1000");
 
   if (HasZvamo)
-    Builder.defineMacro("__riscv_zvamo", "9000");
+    Builder.defineMacro("__riscv_zvamo", "1000000");
 
   if (HasZvlsseg)
-    Builder.defineMacro("__riscv_zvlsseg", "9000");
+    Builder.defineMacro("__riscv_zvlsseg", "1000000");
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   return llvm::StringSwitch<bool>(Feature)
       .Case("riscv", true)
       .Case("riscv32", !Is64Bit)

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

 // extension that the compiler currently supports.
 static Optional<RISCVExtensionVersion>
 isExperimentalExtension(StringRef Ext) {
   if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
       Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
       Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
     return RISCVExtensionVersion{"0", "93"};
   if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
-    return RISCVExtensionVersion{"0", "9"};
+    return RISCVExtensionVersion{"1", "0"};
   if (Ext == "zfh")
     return RISCVExtensionVersion{"0", "1"};
   return None;
 }
 
 static bool isSupportedExtension(StringRef Ext) {
   // LLVM supports "z" extensions which are marked as experimental.
   if (isExperimentalExtension(Ext))

clang/test/Driver/riscv-arch.c

 // RV32-EXPERIMENTAL-V-NOVERS: error: invalid arch name 'rv32iv'
 // RV32-EXPERIMENTAL-V-NOVERS: experimental extension requires explicit version number
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-BADVERS %s
 // RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
 // RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
 // RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izfh -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH-NOFLAG %s
 // RV32-EXPERIMENTAL-ZFH-NOFLAG: error: invalid arch name 'rv32izfh'
 // RV32-EXPERIMENTAL-ZFH-NOFLAG: requires '-menable-experimental-extensions'
 

 // RV32-EXPERIMENTAL-ZVAMO-NOVERS: error: invalid arch name 'rv32izvamo'
 // RV32-EXPERIMENTAL-ZVAMO-NOVERS: experimental extension requires explicit version number
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-BADVERS %s
 // RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izvamo0p1'
 // RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s
 // RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
 // RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32izvlsseg'
 // RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires '-menable-experimental-extensions'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s
 // RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32izvlsseg'
 // RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit version number
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
 // RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32izvlsseg0p1'
 // RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
 // RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"

clang/test/Preprocessor/riscv-target-features.c

 // RUN: -o - | FileCheck --check-prefix=CHECK-DOUBLE %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-DOUBLE %s
 // CHECK-DOUBLE: __riscv_float_abi_double 1
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv32iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv32iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN:   -march=rv64iv0p9 -x c -E -dM %s \
+// RUN:   -march=rv64iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p9 -x c -E -dM %s \
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p9 -x c -E -dM %s \
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p9 -x c -E -dM %s \
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p9 -x c -E -dM %s \
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
-// CHECK-V-EXT: __riscv_v 9000
+// CHECK-V-EXT: __riscv_v 1000000
 // CHECK-V-EXT: __riscv_vector 1
-// CHECK-V-EXT: __riscv_zvamo 9000
-// CHECK-V-EXT: __riscv_zvlsseg 9000
+// CHECK-V-EXT: __riscv_zvamo 1000000
+// CHECK-V-EXT: __riscv_zvlsseg 1000000
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izba0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64izba0p93 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
 // CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 93000
 

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

if (Tag != RISCVAttrs::ARCH) {
         formalArchStr = (Twine(formalArchStr) + "_f2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtD))
         formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtC))
         formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtB))
         formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtV))
-        formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
+        formalArchStr = (Twine(formalArchStr) + "_v1p0").str();
       if (getFeatureBits(RISCV::FeatureExtZfh))
         formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
       if (getFeatureBits(RISCV::FeatureExtZba))
         formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZbb))
         formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZbc))
         formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str();
if (Tag != RISCVAttrs::ARCH) {
         formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZbr))
         formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZbs))
         formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZbt))
         formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZvamo))
-        formalArchStr = (Twine(formalArchStr) + "_zvamo0p9").str();
+        formalArchStr = (Twine(formalArchStr) + "_zvamo1p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
-        formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p9").str();
+        formalArchStr = (Twine(formalArchStr) + "_zvlsseg1p0").str();
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
   }
 
   return false;
 }
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

if (STI.hasFeature(RISCV::FeatureStdExtF))
     Arch += "_f2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtD))
     Arch += "_d2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtC))
     Arch += "_c2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtB))
     Arch += "_b0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
-    Arch += "_v0p9";
+    Arch += "_v1p0";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
     Arch += "_zfh0p1";
   if (STI.hasFeature(RISCV::FeatureExtZba))
     Arch += "_zba0p93";
   if (STI.hasFeature(RISCV::FeatureExtZbb))
     Arch += "_zbb0p93";
   if (STI.hasFeature(RISCV::FeatureExtZbc))
     Arch += "_zbc0p93";
if (STI.hasFeature(RISCV::FeatureExtZbproposedc))
     Arch += "_zbproposedc0p93";
   if (STI.hasFeature(RISCV::FeatureExtZbr))
     Arch += "_zbr0p93";
   if (STI.hasFeature(RISCV::FeatureExtZbs))
     Arch += "_zbs0p93";
   if (STI.hasFeature(RISCV::FeatureExtZbt))
     Arch += "_zbt0p93";
   if (STI.hasFeature(RISCV::FeatureExtZvamo))
-    Arch += "_zvamo0p9";
+    Arch += "_zvamo1p0";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
-    Arch += "_zvlsseg0p9";
+    Arch += "_zvlsseg1p0";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
 
 // This part is for ascii assembly output
 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
                                                formatted_raw_ostream &OS)
     : RISCVTargetStreamer(S), OS(OS) {}

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
 ; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93"
 ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
 ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
 ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
 ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
 ; RV32ZBPROPOSEDC: .attribute 5, "rv32i2p0_zbproposedc0p93"
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64B: .attribute 5, "rv64i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93"
 ; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93"
 ; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93"
 ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
 ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
 ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
 ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
 ; RV64ZBPROPOSEDC: .attribute 5, "rv64i2p0_zbproposedc0p93"
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
+; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
 
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 
 .attribute arch, "rv32ima2p_fdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ib"
 # CHECK: attribute      5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute      5, "rv32i2p0_v0p9"
+# CHECK: attribute      5, "rv32i2p0_v1p0"
 
 .attribute arch, "rv32izba"
 # CHECK: attribute      5, "rv32i2p0_zba0p93"
 
 .attribute arch, "rv32izbb"
 # CHECK: attribute      5, "rv32i2p0_zbb0p93"
 
 .attribute arch, "rv32izbc"

 
 .attribute arch, "rv32izbt"
 # CHECK: attribute      5, "rv32i2p0_zbt0p93"
 
 .attribute arch, "rv32ifzfh"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zfh0p1"
 
 .attribute arch, "rv32ivzvamo_zvlsseg"
-# CHECK: attribute      5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+# CHECK: attribute      5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
 
-.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
-# CHECK: attribute      5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
+.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
+# CHECK: attribute      5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"