Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -505,6 +505,33 @@ return (isRV64() && isUInt<5>(Imm)) || isUInt<4>(Imm); } + bool isUImm2() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + + bool isUImm3() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + + bool isUImm4() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<4>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + bool isUImm5() const { int64_t Imm; RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; @@ -514,6 +541,15 @@ return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; } + bool isUImm6() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<6>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + bool isSImm5() const { if (!isImm()) return false; @@ -1021,11 +1057,19 @@ if (isRV64()) return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1); + case Match_InvalidUImm2: + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1); + case Match_InvalidUImm3: + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1); + case Match_InvalidUImm4: + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1); case Match_InvalidUImm5: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); case Match_InvalidSImm5: return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4), (1 << 4) - 1); + case Match_InvalidUImm6: + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1); case Match_InvalidSImm6: return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5), (1 << 5) - 1); Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp =================================================================== --- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -161,6 +161,23 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeGPRPRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + const FeatureBitset &FeatureBits = + static_cast(Decoder) + ->getSubtargetInfo() + .getFeatureBits(); + bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; + + if (RegNo >= 32 || (IsRV32E && RegNo >= 16)) + return MCDisassembler::Fail; + + MCRegister Reg = RISCV::X0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { @@ -367,6 +384,18 @@ return MCDisassembler::Fail; } Insn = support::endian::read32le(Bytes.data()); + + if (STI.getFeatureBits()[RISCV::FeatureStdExtP]) { + LLVM_DEBUG(dbgs() << "Trying RVP32D table (p-ext):\n"); + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTableRVP32D32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); Size = 4; Index: llvm/lib/Target/RISCV/RISCV.td =================================================================== --- llvm/lib/Target/RISCV/RISCV.td +++ llvm/lib/Target/RISCV/RISCV.td @@ -158,6 +158,13 @@ AssemblerPredicate<(all_of(not FeatureNoRVCHints)), "RVC Hint Instructions">; +def FeatureStdExtP + : SubtargetFeature<"experimental-p", "HasStdExtP", "true", + "'P' (Packed SIMD Instructions)">; +def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">, + AssemblerPredicate<(all_of FeatureStdExtP), + "'P' (Packed SIMD Instructions)">; + def FeatureStdExtV : SubtargetFeature<"experimental-v", "HasStdExtV", "true", "'V' (Vector Instructions)">; Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -135,6 +135,7 @@ def OPC_NMADD : RISCVOpcode<0b1001111>; def OPC_OP_FP : RISCVOpcode<0b1010011>; def OPC_OP_V : RISCVOpcode<0b1010111>; +def OPC_OP_P : RISCVOpcode<0b1111111>; def OPC_BRANCH : RISCVOpcode<0b1100011>; def OPC_JALR : RISCVOpcode<0b1100111>; def OPC_JAL : RISCVOpcode<0b1101111>; Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -609,12 +609,21 @@ switch (OpType) { default: llvm_unreachable("Unexpected operand type"); + case RISCVOp::OPERAND_UIMM2: + Ok = isUInt<2>(Imm); + break; + case RISCVOp::OPERAND_UIMM3: + Ok = isUInt<3>(Imm); + break; case RISCVOp::OPERAND_UIMM4: Ok = isUInt<4>(Imm); break; case RISCVOp::OPERAND_UIMM5: Ok = isUInt<5>(Imm); break; + case RISCVOp::OPERAND_UIMM6: + Ok = isUInt<6>(Imm); + break; case RISCVOp::OPERAND_UIMM12: Ok = isUInt<12>(Imm); break; Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -128,6 +128,27 @@ let OperandNamespace = "RISCVOp"; } +def uimm2 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<2>; + let DecoderMethod = "decodeUImmOperand<2>"; + let OperandType = "OPERAND_UIMM2"; + let OperandNamespace = "RISCVOp"; +} + +def uimm3 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<3>; + let DecoderMethod = "decodeUImmOperand<3>"; + let OperandType = "OPERAND_UIMM3"; + let OperandNamespace = "RISCVOp"; +} + +def uimm4 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<4>; + let DecoderMethod = "decodeUImmOperand<4>"; + let OperandType = "OPERAND_UIMM4"; + let OperandNamespace = "RISCVOp"; +} + def uimm5 : Operand, ImmLeaf(Imm);}]> { let ParserMatchClass = UImmAsmOperand<5>; let DecoderMethod = "decodeUImmOperand<5>"; @@ -135,6 +156,13 @@ let OperandNamespace = "RISCVOp"; } +def uimm6 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<6>; + let DecoderMethod = "decodeUImmOperand<6>"; + let OperandType = "OPERAND_UIMM6"; + let OperandNamespace = "RISCVOp"; +} + def simm12 : Operand, ImmLeaf(Imm);}]> { let ParserMatchClass = SImmAsmOperand<12>; let EncoderMethod = "getImmOpValue"; @@ -1230,5 +1258,6 @@ include "RISCVInstrInfoD.td" include "RISCVInstrInfoC.td" include "RISCVInstrInfoB.td" +include "RISCVInstrInfoP.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZfh.td" Index: llvm/lib/Target/RISCV/RISCVInstrInfoP.td =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -0,0 +1,554 @@ +//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions from the standard 'P' Packed +/// SIMD extension +/// This version is still experimental as the 'P' extension hasn't been +/// ratified yet. +/// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// op rd +class ALU_P funct12, bits<5> funct5, bits<3> funct3, string opcodestr> + : RVInstR { + let rs1 = funct5; + let rs2 = funct12{4-0}; +} + +// op rd rs1 +class ALU_P_r funct7, bits<5> funct5, bits<3> funct3, string opcodestr> + : RVInstR { + let Inst{24-20} = funct5; +} + +// op rd rs1 rs2 +class ALU_P_rr funct7, bits<3> funct3, string opcodestr> + : RVInstR; + +// (rd as input operand)op rd rs1 rs2 +class ALU_P_drr funct7, bits<3> funct3, string opcodestr> + : RVInstR{ + let Constraints = "$rd = $rd_in"; +} + +// (RVP32D only) op rd rs1 rs2 +class ALU_P_rrP funct7, bits<3> funct3, string opcodestr> + : RVInstR; + +// op rd rs1 rs2 rs3 +class ALU_P_rrr funct2, bits<3> funct3, string opcodestr> + : RVInstR4 { + let Inst{14-12} = funct3; +} + +// op rd rs1 uimm2 +class ALU_P_ri2 funct10, bits<3> funct3, string opcodestr> + : RVInstI { + bits<2> uimm; + + let Inst{31-22} = funct10; + let Inst{21-20} = uimm; +} + +// op rd rs1 uimm3 +class ALU_P_ri3 funct9, bits<3> funct3, string opcodestr> + : RVInstI { + bits<3> uimm; + + let Inst{31-23} = funct9; + let Inst{22-20} = uimm; +} + +// op rd rs1 uimm4 +class ALU_P_ri4 funct8, bits<3> funct3, string opcodestr> + : RVInstI { + bits<4> uimm; + + let Inst{31-24} = funct8; + let Inst{23-20} = uimm; +} + +// op rd rs1 uimm5 +class ALU_P_ri5 funct7, bits<3> funct3, string opcodestr> + : RVInstI { + bits<5> uimm; + + let Inst{31-25} = funct7; + let Inst{24-20} = uimm; +} + +// op rd rs1 uimm6 +class ALU_P_ri6 funct6, bits<3> funct3, string opcodestr> + : RVInstI { + bits<6> uimm; + + let Inst{31-26} = funct6; + let Inst{25-20} = uimm; +} +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +// Combination of instruction classes +multiclass ALU_P_rrU funct7, bits<3> funct3, string opcodestr> { + def : ALU_P_rr; + def _U : ALU_P_rr; +} + +// Count leading instructions +class CL_P_r funct5, string opcodestr> + : ALU_P_r<0b1010111, funct5, 0b000, opcodestr>; + +// Unpacked +class UNPKD_P funct5, string opcodestr> + : ALU_P_r<0b1010110, funct5, 0b000, opcodestr>; + +class PKxy16_P zz, string opcodestr> + : ALU_P_rr<{0b00,zz,0b111}, 0b001, opcodestr>; + +class PKxy32_P zz, string opcodestr> + : ALU_P_rr<{0b00,zz,0b111}, 0b010, opcodestr>; + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +// Instructions on RV32/64 +let Predicates = [HasStdExtP] in { +// SIMD 16-bit Add/Subtract Instructions +def ADD16 : ALU_P_rr<0b0100000, 0b000, "add16">; +def RADD16 : ALU_P_rr<0b0000000, 0b000, "radd16">; +def URADD16 : ALU_P_rr<0b0010000, 0b000, "uradd16">; +def KADD16 : ALU_P_rr<0b0001000, 0b000, "kadd16">; +def UKADD16 : ALU_P_rr<0b0011000, 0b000, "ukadd16">; + +def SUB16 : ALU_P_rr<0b0100001, 0b000, "sub16">; +def RSUB16 : ALU_P_rr<0b0000001, 0b000, "rsub16">; +def URSUB16 : ALU_P_rr<0b0010001, 0b000, "ursub16">; +def KSUB16 : ALU_P_rr<0b0001001, 0b000, "ksub16">; +def UKSUB16 : ALU_P_rr<0b0011001, 0b000, "uksub16">; + +def CRAS16 : ALU_P_rr<0b0100010, 0b000, "cras16">; +def RCRAS16 : ALU_P_rr<0b0000010, 0b000, "rcras16">; +def URCRAS16 : ALU_P_rr<0b0010010, 0b000, "urcras16">; +def KCRAS16 : ALU_P_rr<0b0001010, 0b000, "kcras16">; +def UKCRAS16 : ALU_P_rr<0b0011010, 0b000, "ukcras16">; + +def CRSA16 : ALU_P_rr<0b0100011, 0b000, "crsa16">; +def RCRSA16 : ALU_P_rr<0b0000011, 0b000, "rcrsa16">; +def URCRSA16 : ALU_P_rr<0b0010011, 0b000, "urcrsa16">; +def KCRSA16 : ALU_P_rr<0b0001011, 0b000, "kcrsa16">; +def UKCRSA16 : ALU_P_rr<0b0011011, 0b000, "ukcrsa16">; + +def STAS16 : ALU_P_rr<0b1111010, 0b010, "stas16">; +def RSTAS16 : ALU_P_rr<0b1011010, 0b010, "rstas16">; +def URSTAS16 : ALU_P_rr<0b1101010, 0b010, "urstas16">; +def KSTAS16 : ALU_P_rr<0b1100010, 0b010, "kstas16">; +def UKSTAS16 : ALU_P_rr<0b1110010, 0b010, "ukstas16">; + +def STSA16 : ALU_P_rr<0b1111011, 0b010, "stsa16">; +def RSTSA16 : ALU_P_rr<0b1011011, 0b010, "rstsa16">; +def URSTSA16 : ALU_P_rr<0b1101011, 0b010, "urstsa16">; +def KSTSA16 : ALU_P_rr<0b1100011, 0b010, "kstsa16">; +def UKSTSA16 : ALU_P_rr<0b1110011, 0b010, "ukstsa16">; + +// SIMD 8-bit Add/Subtract Instructions +def ADD8 : ALU_P_rr<0b0100100, 0b000, "add8">; +def RADD8 : ALU_P_rr<0b0000100, 0b000, "radd8">; +def URADD8 : ALU_P_rr<0b0010100, 0b000, "uradd8">; +def KADD8 : ALU_P_rr<0b0001100, 0b000, "kadd8">; +def UKADD8 : ALU_P_rr<0b0011100, 0b000, "ukadd8">; + +def SUB8 : ALU_P_rr<0b0100101, 0b000, "sub8">; +def RSUB8 : ALU_P_rr<0b0000101, 0b000, "rsub8">; +def URSUB8 : ALU_P_rr<0b0010101, 0b000, "ursub8">; +def KSUB8 : ALU_P_rr<0b0001101, 0b000, "ksub8">; +def UKSUB8 : ALU_P_rr<0b0011101, 0b000, "uksub8">; + +// SIMD 16-bit Shift Instructions +defm SRA16 : ALU_P_rrU<0b0101000, 0b000, "sra16">; +def SRAI16 : ALU_P_ri4<0b01110000, 0b000, "srai16">; +def SRAI16_U : ALU_P_ri4<0b01110001, 0b000, "srai16.u">; +defm SRL16 : ALU_P_rrU<0b0101001, 0b000, "srl16">; +def SRLI16 : ALU_P_ri4<0b01110010, 0b000, "srli16">; +def SRLI16_U : ALU_P_ri4<0b01110011, 0b000, "srli16.u">; +def SLL16 : ALU_P_rr<0b0101010, 0b000, "sll16">; +def SLLI16 : ALU_P_ri4<0b01110100, 0b000, "slli16">; +def KSLL16 : ALU_P_rr<0b0110010, 0b000, "ksll16">; +def KSLLI16 : ALU_P_ri4<0b01110101, 0b000, "kslli16">; +defm KSLRA16 : ALU_P_rrU<0b0101011, 0b000, "kslra16">; + +// SIMD 8-bit Shift Instructions +defm SRA8 : ALU_P_rrU<0b0101100, 0b000, "sra8">; +def SRAI8 : ALU_P_ri3<0b011110000, 0b000, "srai8">; +def SRAI8_U : ALU_P_ri3<0b011110001, 0b000, "srai8.u">; +defm SRL8 : ALU_P_rrU<0b0101101, 0b000, "srl8">; +def SRLI8 : ALU_P_ri3<0b011110100, 0b000, "srli8">; +def SRLI8_U : ALU_P_ri3<0b011110101, 0b000, "srli8.u">; +def SLL8 : ALU_P_rr<0b0101110, 0b000, "sll8">; +def SLLI8 : ALU_P_ri3<0b011111000, 0b000, "slli8">; +def KSLL8 : ALU_P_rr<0b0110110, 0b000, "ksll8">; +def KSLLI8 : ALU_P_ri3<0b011111001, 0b000, "kslli8">; +defm KSLRA8 : ALU_P_rrU<0b0101111, 0b000, "kslra8">; + +// SIMD 16-bit Compare Instructions +def CMPEQ16 : ALU_P_rr<0b0100110, 0b000, "cmpeq16">; +def SCMPLT16 : ALU_P_rr<0b0000110, 0b000, "scmplt16">; +def SCMPLE16 : ALU_P_rr<0b0001110, 0b000, "scmple16">; +def UCMPLT16 : ALU_P_rr<0b0010110, 0b000, "ucmplt16">; +def UCMPLE16 : ALU_P_rr<0b0011110, 0b000, "ucmple16">; + +// SIMD 8-bit Compare Instructions +def CMPEQ8 : ALU_P_rr<0b0100111, 0b000, "cmpeq8">; +def SCMPLT8 : ALU_P_rr<0b0000111, 0b000, "scmplt8">; +def SCMPLE8 : ALU_P_rr<0b0001111, 0b000, "scmple8">; +def UCMPLT8 : ALU_P_rr<0b0010111, 0b000, "ucmplt8">; +def UCMPLE8 : ALU_P_rr<0b0011111, 0b000, "ucmple8">; + +// SIMD 16-bit Multiply Instructions +def SMUL16 : ALU_P_rr<0b1010000, 0b000, "smul16">; +def SMULX16 : ALU_P_rr<0b1010001, 0b000, "smulx16">; +def UMUL16 : ALU_P_rr<0b1011000, 0b000, "umul16">; +def UMULX16 : ALU_P_rr<0b1011001, 0b000, "umulx16">; +def KHM16 : ALU_P_rr<0b1000011, 0b000, "khm16">; +def KHMX16 : ALU_P_rr<0b1001011, 0b000, "khmx16">; + +// SIMD 8-bit Multiply Instructions +def SMUL8 : ALU_P_rr<0b1010100, 0b000, "smul8">; +def SMULX8 : ALU_P_rr<0b1010101, 0b000, "smulx8">; +def UMUL8 : ALU_P_rr<0b1011100, 0b000, "umul8">; +def UMULX8 : ALU_P_rr<0b1011101, 0b000, "umulx8">; +def KHM8 : ALU_P_rr<0b1000111, 0b000, "khm8">; +def KHMX8 : ALU_P_rr<0b1001111, 0b000, "khmx8">; + +// SIMD 16-bit Miscellaneous Instructions +def SMIN16 : ALU_P_rr<0b1000000, 0b000, "smin16">; +def UMIN16 : ALU_P_rr<0b1001000, 0b000, "umin16">; +def SMAX16 : ALU_P_rr<0b1000001, 0b000, "smax16">; +def UMAX16 : ALU_P_rr<0b1001001, 0b000, "umax16">; +def SCLIP16 : ALU_P_ri4<0b10000100, 0b000, "sclip16">; +def UCLIP16 : ALU_P_ri4<0b10000101, 0b000, "uclip16">; +def KABS16 : UNPKD_P<0b10001, "kabs16">; +def CLRS16 : CL_P_r<0b01000, "clrs16">; +def CLZ16 : CL_P_r<0b01001, "clz16">; +def CLO16 : CL_P_r<0b01011, "clo16">; +def SWAP16 : UNPKD_P<0b11001, "swap16">; + +// SIMD 8-bit Miscellaneous Instructions +def SMIN8 : ALU_P_rr<0b1000100, 0b000, "smin8">; +def UMIN8 : ALU_P_rr<0b1001100, 0b000, "umin8">; +def SMAX8 : ALU_P_rr<0b1000101, 0b000, "smax8">; +def UMAX8 : ALU_P_rr<0b1001101, 0b000, "umax8">; +def KABS8 : UNPKD_P<0b10000, "kabs8">; +def SCLIP8 : ALU_P_ri3<0b100011000, 0b000, "sclip8">; +def UCLIP8 : ALU_P_ri3<0b100011010, 0b000, "uclip8">; +def CLRS8 : CL_P_r<0b00000, "clrs8">; +def CLZ8 : CL_P_r<0b00001, "clz8">; +def CLO8 : CL_P_r<0b00011, "clo8">; +def SWAP8 : UNPKD_P<0b11000, "swap8">; + +// 8-bit Unpacking Instructions +def SUNPKD810 : UNPKD_P<0b01000, "sunpkd810">; +def SUNPKD820 : UNPKD_P<0b01001, "sunpkd820">; +def SUNPKD830 : UNPKD_P<0b01010, "sunpkd830">; +def SUNPKD831 : UNPKD_P<0b01011, "sunpkd831">; +def SUNPKD832 : UNPKD_P<0b10011, "sunpkd832">; +def ZUNPKD810 : UNPKD_P<0b01100, "zunpkd810">; +def ZUNPKD820 : UNPKD_P<0b01101, "zunpkd820">; +def ZUNPKD830 : UNPKD_P<0b01110, "zunpkd830">; +def ZUNPKD831 : UNPKD_P<0b01111, "zunpkd831">; +def ZUNPKD832 : UNPKD_P<0b10111, "zunpkd832">; + +// 16-bit Packing Instructions +def PKBB16 : PKxy16_P<0b00, "pkbb16">; +def PKBT16 : PKxy16_P<0b01, "pkbt16">; +def PKTB16 : PKxy16_P<0b11, "pktb16">; +def PKTT16 : PKxy16_P<0b10, "pktt16">; + +// Signed MSW 32x32 Multiply and Add Instructions +defm SMMUL : ALU_P_rrU<0b0100000, 0b001, "smmul">; +defm KMMAC : ALU_P_rrU<0b0110000, 0b001, "kmmac">; +defm KMMSB : ALU_P_rrU<0b0100001, 0b001, "kmmsb">; +defm KWMMUL : ALU_P_rrU<0b0110001, 0b001, "kwmmul">; + +// Signed MSW 32x16 Multiply and Add Instructions +defm SMMWB : ALU_P_rrU<0b0100010, 0b001, "smmwb">; +defm SMMWT : ALU_P_rrU<0b0110010, 0b001, "smmwt">; +defm KMMAWB : ALU_P_rrU<0b0100011, 0b001, "kmmawb">; +defm KMMAWT : ALU_P_rrU<0b0110011, 0b001, "kmmawt">; +defm KMMWB2 : ALU_P_rrU<0b1000111, 0b001, "kmmwb2">; +defm KMMWT2 : ALU_P_rrU<0b1010111, 0b001, "kmmwt2">; +defm KMMAWB2 : ALU_P_rrU<0b1100111, 0b001, "kmmawb2">; +defm KMMAWT2 : ALU_P_rrU<0b1110111, 0b001, "kmmawt2">; + +// Signed 16-bit Multiply 32-bit Add/Subtract Instructions +def SMBB16 : ALU_P_rr<0b0000100, 0b001, "smbb16">; +def SMBT16 : ALU_P_rr<0b0001100, 0b001, "smbt16">; +def SMTT16 : ALU_P_rr<0b0010100, 0b001, "smtt16">; +def KMDA : ALU_P_rr<0b0011100, 0b001, "kmda">; +def KMXDA : ALU_P_rr<0b0011101, 0b001, "kmxda">; +def SMDS : ALU_P_rr<0b0101100, 0b001, "smds">; +def SMDRS : ALU_P_rr<0b0110100, 0b001, "smdrs">; +def SMXDS : ALU_P_rr<0b0111100, 0b001, "smxds">; +def KMABB : ALU_P_rr<0b0101101, 0b001, "kmabb">; +def KMABT : ALU_P_rr<0b0110101, 0b001, "kmabt">; +def KMATT : ALU_P_rr<0b0111101, 0b001, "kmatt">; +def KMADA : ALU_P_rr<0b0100100, 0b001, "kmada">; +def KMAXDA : ALU_P_rr<0b0100101, 0b001, "kmaxda">; +def KMADS : ALU_P_rr<0b0101110, 0b001, "kmads">; +def KMADRS : ALU_P_rr<0b0110110, 0b001, "kmadrs">; +def KMAXDS : ALU_P_rr<0b0111110, 0b001, "kmaxds">; +def KMSDA : ALU_P_rr<0b0100110, 0b001, "kmsda">; +def KMSXDA : ALU_P_rr<0b0100111, 0b001, "kmsxda">; + +// Signed 16-bit Multiply 64-bit Add/Subtract Instructions +def SMAL : ALU_P_rr<0b0101111, 0b001, "smal">; + +// Partial-SIMD Miscellaneous Instructions +def SCLIP32 : ALU_P_ri5<0b1110010, 0b000, "sclip32">; +def UCLIP32 : ALU_P_ri5<0b1111010, 0b000, "uclip32">; +def CLRS32 : CL_P_r<0b11000, "clrs32">; +def CLZ32 : CL_P_r<0b11001, "clz32">; +def CLO32 : CL_P_r<0b11011, "clo32">; +def PBSAD : ALU_P_rr<0b1111110, 0b000, "pbsad">; +def PBSADA : ALU_P_rr<0b1111111, 0b000, "pbsada">; + +// 8-bit Multiply with 32-bit Add Instructions +def SMAQA : ALU_P_rr<0b1100100, 0b000, "smaqa">; +def UMAQA : ALU_P_rr<0b1100110, 0b000, "umaqa">; +def SMAQA_SU : ALU_P_rr<0b1100101, 0b000, "smaqa.su">; + +// 32-bit Multiply 64-bit Add/Subtract Instructions +def SMAR64 : ALU_P_rr<0b1000010, 0b001, "smar64">; +def SMSR64 : ALU_P_rr<0b1000011, 0b001, "smsr64">; +def UMAR64 : ALU_P_rr<0b1010010, 0b001, "umar64">; +def UMSR64 : ALU_P_rr<0b1010011, 0b001, "umsr64">; +def KMAR64 : ALU_P_rr<0b1001010, 0b001, "kmar64">; +def KMSR64 : ALU_P_rr<0b1001011, 0b001, "kmsr64">; +def UKMAR64 : ALU_P_rr<0b1011010, 0b001, "ukmar64">; +def UKMSR64 : ALU_P_rr<0b1011011, 0b001, "ukmsr64">; + +// Signed 16-bit Multiply 64-bit Add/Subtract Instructions +def SMALBB : ALU_P_rr<0b1000100, 0b001, "smalbb">; +def SMALBT : ALU_P_rr<0b1001100, 0b001, "smalbt">; +def SMALTT : ALU_P_rr<0b1010100, 0b001, "smaltt">; +def SMALDA : ALU_P_rr<0b1000110, 0b001, "smalda">; +def SMALXDA : ALU_P_rr<0b1001110, 0b001, "smalxda">; +def SMALDS : ALU_P_rr<0b1000101, 0b001, "smalds">; +def SMALDRS : ALU_P_rr<0b1001101, 0b001, "smaldrs">; +def SMALXDS : ALU_P_rr<0b1010101, 0b001, "smalxds">; +def SMSLDA : ALU_P_rr<0b1010110, 0b001, "smslda">; +def SMSLXDA : ALU_P_rr<0b1011110, 0b001, "smslxda">; + +// Non-SIMD Q15 saturation ALU Instructions +def KADDH : ALU_P_rr<0b0000010, 0b001, "kaddh">; +def KSUBH : ALU_P_rr<0b0000011, 0b001, "ksubh">; +def KHMBB : ALU_P_rr<0b0000110, 0b001, "khmbb">; +def KHMBT : ALU_P_rr<0b0001110, 0b001, "khmbt">; +def KHMTT : ALU_P_rr<0b0010110, 0b001, "khmtt">; +def UKADDH : ALU_P_rr<0b0001010, 0b001, "ukaddh">; +def UKSUBH : ALU_P_rr<0b0001011, 0b001, "uksubh">; + +// Non-SIMD Q31 saturation ALU Instructions +def KADDW : ALU_P_rr<0b0000000, 0b001, "kaddw">; +def UKADDW : ALU_P_rr<0b0001000, 0b001, "ukaddw">; +def KSUBW : ALU_P_rr<0b0000001, 0b001, "ksubw">; +def UKSUBW : ALU_P_rr<0b0001001, 0b001, "uksubw">; +def KDMBB : ALU_P_rr<0b0000101, 0b001, "kdmbb">; +def KDMBT : ALU_P_rr<0b0001101, 0b001, "kdmbt">; +def KDMTT : ALU_P_rr<0b0010101, 0b001, "kdmtt">; +defm KSLRAW : ALU_P_rrU<0b0110111, 0b001, "kslraw">; +def KSLLW : ALU_P_rr<0b0010011, 0b001, "ksllw">; +def KSLLIW : ALU_P_ri5<0b0011011, 0b001, "kslliw">; +def KDMABB : ALU_P_drr<0b1101001, 0b001, "kdmabb">; +def KDMABT : ALU_P_drr<0b1110001, 0b001, "kdmabt">; +def KDMATT : ALU_P_drr<0b1111001, 0b001, "kdmatt">; +def KABSW : UNPKD_P<0b10100, "kabsw">; + +// 32-bit Computation Instructions +def RADDW : ALU_P_rr<0b0010000, 0b001, "raddw">; +def URADDW : ALU_P_rr<0b0011000, 0b001, "uraddw">; +def RSUBW : ALU_P_rr<0b0010001, 0b001, "rsubw">; +def URSUBW : ALU_P_rr<0b0011001, 0b001, "ursubw">; +def MAXW : ALU_P_rr<0b1111001, 0b000, "maxw">; +def MINW : ALU_P_rr<0b1111000, 0b000, "minw">; +def MULR64 : ALU_P_rr<0b1111000, 0b001, "mulr64">; +def MULSR64 : ALU_P_rr<0b1110000, 0b001, "mulsr64">; +def MSUBR32 : ALU_P_rr<0b1100011, 0b001, "msubr32">; + +// OV (Overflow) flag Set/Clear Instructions +def RDOV : ALU_P<0b000000001001, 0b00000, 0b000, "rdov">; +def CLROV : ALU_P<0b000000001001, 0b00001, 0b111, "clrov">; + +// Non-SIMD Miscellaneous Instructions +def AVE : ALU_P_rr<0b1110000, 0b000, "ave">; +def SRA_U : ALU_P_rr<0b0010010, 0b001, "sra.u">; +def BITREV : ALU_P_rr<0b1110011, 0b000, "bitrev">; +def WEXT : ALU_P_rr<0b1100111, 0b000, "wext">; +def WEXTI : ALU_P_ri5<0b1101111, 0b000, "wexti">; +def BPICK : ALU_P_rrr<0b00, 0b011, "bpick">; +def MADDR32 : ALU_P_rr<0b1100010, 0b001, "maddr32">; +} // Predicates = [HasStdExtP] + +// Instructions on RV32 +let Predicates = [HasStdExtP, IsRV32] in { +let DecoderNamespace = "RVP32D" in { +// 64-bit Add/Subtract Instructions +def ADD64_32 : ALU_P_rrP<0b1100000, 0b001, "add64">; +def RADD64_32 : ALU_P_rrP<0b1000000, 0b001, "radd64">; +def URADD64_32 : ALU_P_rrP<0b1010000, 0b001, "uradd64">; +def KADD64_32 : ALU_P_rrP<0b1001000, 0b001, "kadd64">; +def UKADD64_32 : ALU_P_rrP<0b1011000, 0b001, "ukadd64">; +def SUB64_32 : ALU_P_rrP<0b1100001, 0b001, "sub64">; +def RSUB64_32 : ALU_P_rrP<0b1000001, 0b001, "rsub64">; +def URSUB64_32 : ALU_P_rrP<0b1010001, 0b001, "ursub64">; +def KSUB64_32 : ALU_P_rrP<0b1001001, 0b001, "ksub64">; +def UKSUB64_32 : ALU_P_rrP<0b1011001, 0b001, "uksub64">; +} +// Non-SIMD Miscellaneous Instructions +def SRAI_U_32 : ALU_P_ri5<0b1101010, 0b001, "srai.u">; +def BITREVI_32 : ALU_P_ri5<0b1110100, 0b000, "bitrevi">; +def INSB_32 : ALU_P_ri2<0b1010110000, 0b000, "insb">; +} // Predicates = [HasStdExtP, IsRV32] + +// Instructions on RV64 +let Predicates = [HasStdExtP, IsRV64] in { +// 64-bit Add/Subtract Instructions +def ADD64_64 : ALU_P_rr<0b1100000, 0b001, "add64">; +def RADD64_64 : ALU_P_rr<0b1000000, 0b001, "radd64">; +def URADD64_64 : ALU_P_rr<0b1010000, 0b001, "uradd64">; +def KADD64_64 : ALU_P_rr<0b1001000, 0b001, "kadd64">; +def UKADD64_64 : ALU_P_rr<0b1011000, 0b001, "ukadd64">; +def SUB64_64 : ALU_P_rr<0b1100001, 0b001, "sub64">; +def RSUB64_64 : ALU_P_rr<0b1000001, 0b001, "rsub64">; +def URSUB64_64 : ALU_P_rr<0b1010001, 0b001, "ursub64">; +def KSUB64_64 : ALU_P_rr<0b1001001, 0b001, "ksub64">; +def UKSUB64_64 : ALU_P_rr<0b1011001, 0b001, "uksub64">; + +// Non-SIMD Miscellaneous Instructions +def BITREVI_64 : ALU_P_ri6<0b111010, 0b000, "bitrevi">; +def INSB_64 : ALU_P_ri3<0b101011000, 0b000, "insb">; +def SRAI_U_64 : ALU_P_ri6<0b110101, 0b001, "srai.u">; + +// SIMD 32-bit Add/Subtract Instructions +def ADD32 : ALU_P_rr<0b0100000, 0b010, "add32">; +def RADD32 : ALU_P_rr<0b0000000, 0b010, "radd32">; +def URADD32 : ALU_P_rr<0b0010000, 0b010, "uradd32">; +def KADD32 : ALU_P_rr<0b0001000, 0b010, "kadd32">; +def UKADD32 : ALU_P_rr<0b0011000, 0b010, "ukadd32">; + +def SUB32 : ALU_P_rr<0b0100001, 0b010, "sub32">; +def RSUB32 : ALU_P_rr<0b0000001, 0b010, "rsub32">; +def URSUB32 : ALU_P_rr<0b0010001, 0b010, "ursub32">; +def KSUB32 : ALU_P_rr<0b0001001, 0b010, "ksub32">; +def UKSUB32 : ALU_P_rr<0b0011001, 0b010, "uksub32">; + +def CRAS32 : ALU_P_rr<0b0100010, 0b010, "cras32">; +def RCRAS32 : ALU_P_rr<0b0000010, 0b010, "rcras32">; +def URCRAS32 : ALU_P_rr<0b0010010, 0b010, "urcras32">; +def KCRAS32 : ALU_P_rr<0b0001010, 0b010, "kcras32">; +def UKCRAS32 : ALU_P_rr<0b0011010, 0b010, "ukcras32">; + +def CRSA32 : ALU_P_rr<0b0100011, 0b010, "crsa32">; +def RCRSA32 : ALU_P_rr<0b0000011, 0b010, "rcrsa32">; +def URCRSA32 : ALU_P_rr<0b0010011, 0b010, "urcrsa32">; +def KCRSA32 : ALU_P_rr<0b0001011, 0b010, "kcrsa32">; +def UKCRSA32 : ALU_P_rr<0b0011011, 0b010, "ukcrsa32">; + +def STAS32 : ALU_P_rr<0b1111000, 0b010, "stas32">; +def RSTAS32 : ALU_P_rr<0b1011000, 0b010, "rstas32">; +def URSTAS32 : ALU_P_rr<0b1101000, 0b010, "urstas32">; +def KSTAS32 : ALU_P_rr<0b1100000, 0b010, "kstas32">; +def UKSTAS32 : ALU_P_rr<0b1110000, 0b010, "ukstas32">; + +def STSA32 : ALU_P_rr<0b1111001, 0b010, "stsa32">; +def RSTSA32 : ALU_P_rr<0b1011001, 0b010, "rstsa32">; +def URSTSA32 : ALU_P_rr<0b1101001, 0b010, "urstsa32">; +def KSTSA32 : ALU_P_rr<0b1100001, 0b010, "kstsa32">; +def UKSTSA32 : ALU_P_rr<0b1110001, 0b010, "ukstsa32">; + +// SIMD 32-bit Shift Instructions +defm SRA32 : ALU_P_rrU<0b0101000, 0b010, "sra32">; +def SRAI32 : ALU_P_ri5<0b0111000, 0b010, "srai32">; +def SRAI32_U : ALU_P_ri5<0b1000000, 0b010, "srai32.u">; +defm SRL32 : ALU_P_rrU<0b0101001, 0b010, "srl32">; +def SRLI32 : ALU_P_ri5<0b0111001, 0b010, "srli32">; +def SRLI32_U : ALU_P_ri5<0b1000001, 0b010, "srli32.u">; +def SLL32 : ALU_P_rr<0b0101010, 0b010, "sll32">; +def SLLI32 : ALU_P_ri5<0b0111010, 0b010, "slli32">; +def KSLL32 : ALU_P_rr<0b0110010, 0b010, "ksll32">; +def KSLLI32 : ALU_P_ri5<0b1000010, 0b010, "kslli32">; +defm KSLRA32 : ALU_P_rrU<0b0101011, 0b010, "kslra32">; + +// SIMD 32-bit Miscellaneous Instructions +def SMIN32 : ALU_P_rr<0b1001000, 0b010, "smin32">; +def UMIN32 : ALU_P_rr<0b1010000, 0b010, "umin32">; +def SMAX32 : ALU_P_rr<0b1001001, 0b010, "smax32">; +def UMAX32 : ALU_P_rr<0b1010001, 0b010, "umax32">; +def KABS32 : UNPKD_P<0b10010, "kabs32">; + +// SIMD Q15 saturating Multiply Instructions +def KHMBB16 : ALU_P_rr<0b1101110, 0b001, "khmbb16">; +def KHMBT16 : ALU_P_rr<0b1110110, 0b001, "khmbt16">; +def KHMTT16 : ALU_P_rr<0b1111110, 0b001, "khmtt16">; +def KDMBB16 : ALU_P_rr<0b1101101, 0b001, "kdmbb16">; +def KDMBT16 : ALU_P_rr<0b1110101, 0b001, "kdmbt16">; +def KDMTT16 : ALU_P_rr<0b1111101, 0b001, "kdmtt16">; +def KDMABB16 : ALU_P_rr<0b1101100, 0b001, "kdmabb16">; +def KDMABT16 : ALU_P_rr<0b1110100, 0b001, "kdmabt16">; +def KDMATT16 : ALU_P_rr<0b1111100, 0b001, "kdmatt16">; + +// 32-bit Multiply Instructions +def : InstAlias<"smbb32 $rd, $rs1, $rs2", + (MULSR64 GPR:$rd, GPR:$rs1, GPR:$rs2), 0>; +def SMBT32 : ALU_P_rr<0b0001100, 0b010, "smbt32">; +def SMTT32 : ALU_P_rr<0b0010100, 0b010, "smtt32">; + +// 32-bit Multiply Instructions +def KMABB32 : ALU_P_rr<0b0101101, 0b010, "kmabb32">; +def KMABT32 : ALU_P_rr<0b0110101, 0b010, "kmabt32">; +def KMATT32 : ALU_P_rr<0b0111101, 0b010, "kmatt32">; + +// 32-bit Multiply & Add Instructions +def KMDA32 : ALU_P_rr<0b0011100, 0b010, "kmda32">; +def KMAXDA32 : ALU_P_rr<0b0100101, 0b010, "kmaxda32">; +def : InstAlias<"kmada32 $rd, $rs1, $rs2", + (KMAR64 GPR:$rd, GPR:$rs1, GPR:$rs2), 0>; +def KMXDA32 : ALU_P_rr<0b0011101, 0b010, "kmxda32">; +def KMADS32 : ALU_P_rr<0b0101110, 0b010, "kmads32">; +def KMADRS32 : ALU_P_rr<0b0110110, 0b010, "kmadrs32">; +def KMAXDS32 : ALU_P_rr<0b0111110, 0b010, "kmaxds32">; +def KMSDA32 : ALU_P_rr<0b0100110, 0b010, "kmsda32">; +def KMSXDA32 : ALU_P_rr<0b0100111, 0b010, "kmsxda32">; +def SMDS32 : ALU_P_rr<0b0101100, 0b010, "smds32">; +def SMDRS32 : ALU_P_rr<0b0110100, 0b010, "smdrs32">; +def SMXDS32 : ALU_P_rr<0b0111100, 0b010, "smxds32">; + +// Non-SIMD 32-bit Shift Instructions +def SRAIW_U : ALU_P_ri5<0b0011010, 0b001, "sraiw.u">; + +// 32-bit Packing Instructions +def PKBB32 : PKxy32_P<0b00, "pkbb32">; +def PKBT32 : PKxy32_P<0b01, "pkbt32">; +def PKTB32 : PKxy32_P<0b10, "pktb32">; +def PKTT32 : PKxy32_P<0b11, "pktt32">; +} // Predicates = [HasStdExtP, IsRV64] Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td =================================================================== --- llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -180,6 +180,19 @@ [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } +def GPRP : RegisterClass<"RISCV", [XLenVT], 32, (add + X10, X12, X14, X16, + X6, + X28, X30, + X8, + X18, X20, X22, X24, X26, + X0, X2, X4 + )> { + let RegInfos = RegInfoByHwMode< + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; +} + def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { let RegInfos = RegInfoByHwMode< [RV32, RV64], Index: llvm/lib/Target/RISCV/RISCVSchedRocket.td =================================================================== --- llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -16,7 +16,7 @@ let IssueWidth = 1; // 1 micro-op is dispatched per cycle. let LoadLatency = 3; let MispredictPenalty = 3; - let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg]; + let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg, HasStdExtP]; } //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td =================================================================== --- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -15,7 +15,7 @@ let LoadLatency = 3; let MispredictPenalty = 3; let CompleteModel = 0; - let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg]; + let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg, HasStdExtP]; } // The SiFive7 microarchitecure has two pipelines: A and B. Index: llvm/lib/Target/RISCV/RISCVSubtarget.h =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.h +++ llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -50,6 +50,7 @@ bool HasStdExtZbs = false; bool HasStdExtZbt = false; bool HasStdExtZbproposedc = false; + bool HasStdExtP = false; bool HasStdExtV = false; bool HasStdExtZvlsseg = false; bool HasStdExtZvamo = false; @@ -116,6 +117,7 @@ bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZbt() const { return HasStdExtZbt; } bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; } + bool hasStdExtP() const { return HasStdExtP; } bool hasStdExtV() const { return HasStdExtV; } bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } bool hasStdExtZvamo() const { return HasStdExtZvamo; } Index: llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h =================================================================== --- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -85,8 +85,11 @@ namespace RISCVOp { enum OperandType : unsigned { OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, - OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM, + OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM, + OPERAND_UIMM3, + OPERAND_UIMM4, OPERAND_UIMM5, + OPERAND_UIMM6, OPERAND_UIMM12, OPERAND_SIMM12, OPERAND_UIMM20, Index: llvm/test/MC/RISCV/rv32p-invalid.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rv32p-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-p < %s 2>&1 | FileCheck %s + +# Instructions on RV64 +srai.u a0, a1, 32 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +bitrevi a0, a1, 32 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +insb a0, a1, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set + +# Instructions use regs pair +add64 a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set Index: llvm/test/MC/RISCV/rv32p-valid.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rv32p-valid.s @@ -0,0 +1,1002 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-p -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \ +# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ,CHECK-32-ASM %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-p < %s \ +# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: add8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x48] +add8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: add16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x40] +add16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: add64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0xc0] +add64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: ave a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xe0] +ave a0, a1, a2 + +# CHECK-ASM-AND-OBJ: bitrev a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xe6] +bitrev a0, a1, a2 + +# CHECK-ASM-AND-OBJ: bitrevi a0, a1, 7 +# CHECK-ASM: encoding: [0x7f,0x85,0x75,0xe8] +bitrevi a0, a1, 7 + +# CHECK-ASM-AND-OBJ: bpick t0, a1, a2, a3 +# CHECK-ASM: encoding: [0xff,0xd2,0xc5,0x68] +bpick t0, a1, a2, a3 + +# CHECK-ASM-AND-OBJ: clrov a0 +# CHECK-ASM: encoding: [0x73,0xf5,0x90,0x00] +clrov a0 + +# CHECK-ASM-AND-OBJ: clrs8 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x05,0xae] +clrs8 a0, a1 + +# CHECK-ASM-AND-OBJ: clrs16 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x85,0xae] +clrs16 a0, a1 + +# CHECK-ASM-AND-OBJ: clrs32 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x85,0xaf] +clrs32 a0, a1 + +# CHECK-ASM-AND-OBJ: clo8 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x35,0xae] +clo8 a0, a1 + +# CHECK-ASM-AND-OBJ: clo16 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0xb5,0xae] +clo16 a0, a1 + +# CHECK-ASM-AND-OBJ: clo32 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0xb5,0xaf] +clo32 a0, a1 + +# CHECK-ASM-AND-OBJ: clz8 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x15,0xae] +clz8 a0, a1 + +# CHECK-ASM-AND-OBJ: clz16 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x95,0xae] +clz16 a0, a1 + +# CHECK-ASM-AND-OBJ: clz32 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x95,0xaf] +clz32 a0, a1 + +# CHECK-ASM-AND-OBJ: cmpeq8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x4e] +cmpeq8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: cmpeq16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x4c] +cmpeq16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: cras16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x44] +cras16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: crsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x46] +crsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: insb a0, a1, 3 +# CHECK-ASM: encoding: [0x7f,0x85,0x35,0xac] +insb a0, a1, 3 + +# CHECK-ASM-AND-OBJ: kabs8 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x05,0xad] +kabs8 a0, a1 + +# CHECK-ASM-AND-OBJ: kabs16 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x15,0xad] +kabs16 a0, a1 + +# CHECK-ASM-AND-OBJ: kabsw a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x45,0xad] +kabsw a0, a1 + +# CHECK-ASM-AND-OBJ: kadd8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x18] +kadd8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kadd16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x10] +kadd16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kadd64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0x90] +kadd64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: kaddh a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x04] +kaddh a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kaddw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x00] +kaddw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kcras16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x14] +kcras16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kcrsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x16] +kcrsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmbb a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x0a] +kdmbb a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmbt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x1a] +kdmbt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmtt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x2a] +kdmtt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmabb a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xd2] +kdmabb a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmabt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xe2] +kdmabt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmatt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xf2] +kdmatt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khm8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x8e] +khm8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khmx8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x9e] +khmx8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khm16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x86] +khm16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khmx16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x96] +khmx16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khmbb a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x0c] +khmbb a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khmbt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x1c] +khmbt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khmtt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x2c] +khmtt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmabb a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x5a] +kmabb a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmabt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x6a] +kmabt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmatt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x7a] +kmatt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmada a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x48] +kmada a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmaxda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x4a] +kmaxda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmads a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x5c] +kmads a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmadrs a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x6c] +kmadrs a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmaxds a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x7c] +kmaxds a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmar64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x94] +kmar64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x38] +kmda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmxda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x3a] +kmxda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmac a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x60] +kmmac a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmac.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x70] +kmmac.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmawb a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x46] +kmmawb a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmawb.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x56] +kmmawb.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmawb2 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xce] +kmmawb2 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmawb2.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xde] +kmmawb2.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmawt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x66] +kmmawt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmawt.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x76] +kmmawt.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmawt2 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xee] +kmmawt2 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmawt2.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xfe] +kmmawt2.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmsb a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x42] +kmmsb a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmsb.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x52] +kmmsb.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmwb2 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x8e] +kmmwb2 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmwb2.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x9e] +kmmwb2.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmwt2 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xae] +kmmwt2 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmmwt2.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xbe] +kmmwt2.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmsda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x4c] +kmsda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmsxda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x4e] +kmsxda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmsr64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x96] +kmsr64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ksllw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x26] +ksllw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslliw a0, a1, 7 +# CHECK-ASM: encoding: [0x7f,0x95,0x75,0x36] +kslliw a0, a1, 7 + +# CHECK-ASM-AND-OBJ: ksll8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x6c] +ksll8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslli8 a0, a1, 7 +# CHECK-ASM: encoding: [0x7f,0x85,0xf5,0x7c] +kslli8 a0, a1, 7 + +# CHECK-ASM-AND-OBJ: ksll16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x64] +ksll16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslli16 a0, a1, 7 +# CHECK-ASM: encoding: [0x7f,0x85,0x75,0x75] +kslli16 a0, a1, 7 + +# CHECK-ASM-AND-OBJ: kslra8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x5e] +kslra8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslra8.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x6e] +kslra8.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslra16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x56] +kslra16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslra16.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x66] +kslra16.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslraw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x6e] +kslraw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslraw.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x7e] +kslraw.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kstas16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xc4] +kstas16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kstsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xc6] +kstsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ksub8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x1a] +ksub8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ksub16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x12] +ksub16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ksub64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0x92] +ksub64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: ksubh a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x06] +ksubh a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ksubw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x02] +ksubw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kwmmul a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x62] +kwmmul a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kwmmul.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x72] +kwmmul.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: maddr32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xc4] +maddr32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: maxw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xf2] +maxw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: minw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xf0] +minw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: msubr32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xc6] +msubr32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: mulr64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xf0] +mulr64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pbsad a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xfc] +pbsad a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pbsada a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xfe] +pbsada a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pkbb16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x0e] +pkbb16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pkbt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x1e] +pkbt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pktt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x2e] +pktt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pktb16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x3e] +pktb16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: radd8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x08] +radd8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: radd16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x00] +radd16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: radd64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0x80] +radd64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: raddw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x20] +raddw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rcras16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x04] +rcras16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rcrsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x06] +rcrsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rdov a0 +# CHECK-ASM: encoding: [0x73,0x05,0x90,0x00] +rdov a0 + +# CHECK-ASM-AND-OBJ: rstas16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xb4] +rstas16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rstsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xb6] +rstsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rsub8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x0a] +rsub8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rsub16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x02] +rsub16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rsub64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0x82] +rsub64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: rsubw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x22] +rsubw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sclip8 a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0x8c] +sclip8 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: sclip16 a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0x84] +sclip16 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: sclip32 a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0xe4] +sclip32 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: scmple8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x1e] +scmple8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: scmple16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x1c] +scmple16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: scmplt8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x0e] +scmplt8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: scmplt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x0c] +scmplt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sll8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x5c] +sll8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: slli8 a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0x7c] +slli8 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: sll16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x54] +sll16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: slli16 a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0x74] +slli16 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: smal a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x5e] +smal a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smalbb a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x88] +smalbb a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smalbt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x98] +smalbt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smaltt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xa8] +smaltt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smalda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x8c] +smalda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smalxda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x9c] +smalxda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smalds a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x8a] +smalds a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smaldrs a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x9a] +smaldrs a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smalxds a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xaa] +smalxds a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smar64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x84] +smar64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smaqa a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xc8] +smaqa a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smaqa.su a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xca] +smaqa.su a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smax8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x8a] +smax8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smax16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x82] +smax16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smbb16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x08] +smbb16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smbt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x18] +smbt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smtt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x28] +smtt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smds a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x58] +smds a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smdrs a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x68] +smdrs a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smxds a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x78] +smxds a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smin8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x88] +smin8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smin16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x80] +smin16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smmul a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x40] +smmul a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smmul.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x50] +smmul.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smmwb a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x44] +smmwb a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smmwb.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x54] +smmwb.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smmwt a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x64] +smmwt a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smmwt.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x74] +smmwt.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smslda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xac] +smslda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smslxda a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xbc] +smslxda a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smsr64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x86] +smsr64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smul8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xa8] +smul8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smulx8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xaa] +smulx8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smul16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xa0] +smul16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smulx16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xa2] +smulx16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sra.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x24] +sra.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: srai.u a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x95,0x55,0xd4] +srai.u a0, a1, 5 + +# CHECK-ASM-AND-OBJ: sra8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x58] +sra8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sra8.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x68] +sra8.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: srai8 a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0x78] +srai8 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: srai8.u a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0xd5,0x78] +srai8.u a0, a1, 5 + +# CHECK-ASM-AND-OBJ: sra16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x50] +sra16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sra16.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x60] +sra16.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: srai16 a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0x70] +srai16 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: srai16.u a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0x71] +srai16.u a0, a1, 5 + +# CHECK-ASM-AND-OBJ: srl8 t0, a0, a1 +# CHECK-ASM: encoding: [0xff,0x02,0xb5,0x5a] +srl8 t0, a0, a1 + +# CHECK-ASM-AND-OBJ: srl8.u t0, a0, a1 +# CHECK-ASM: encoding: [0xff,0x02,0xb5,0x6a] +srl8.u t0, a0, a1 + +# CHECK-ASM-AND-OBJ: srli8 t0, a0, 3 +# CHECK-ASM: encoding: [0xff,0x02,0x35,0x7a] +srli8 t0, a0, 3 + +# CHECK-ASM-AND-OBJ: srli8.u t0, a0, 3 +# CHECK-ASM: encoding: [0xff,0x02,0xb5,0x7a] +srli8.u t0, a0, 3 + +# CHECK-ASM-AND-OBJ: srl16 t0, a0, a1 +# CHECK-ASM: encoding: [0xff,0x02,0xb5,0x52] +srl16 t0, a0, a1 + +# CHECK-ASM-AND-OBJ: srl16.u t0, a0, a1 +# CHECK-ASM: encoding: [0xff,0x02,0xb5,0x62] +srl16.u t0, a0, a1 + +# CHECK-ASM-AND-OBJ: srli16 t0, a0, 4 +# CHECK-ASM: encoding: [0xff,0x02,0x45,0x72] +srli16 t0, a0, 4 + +# CHECK-ASM-AND-OBJ: srli16.u t0, a0, 4 +# CHECK-ASM: encoding: [0xff,0x02,0x45,0x73] +srli16.u t0, a0, 4 + +# CHECK-ASM-AND-OBJ: stsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xf6] +stsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sub8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x4a] +sub8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sub16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x42] +sub16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sub64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0xc2] +sub64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: sunpkd810 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x85,0xac] +sunpkd810 a0, a1 + +# CHECK-ASM-AND-OBJ: sunpkd820 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x95,0xac] +sunpkd820 a0, a1 + +# CHECK-ASM-AND-OBJ: sunpkd830 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0xa5,0xac] +sunpkd830 a0, a1 + +# CHECK-ASM-AND-OBJ: sunpkd831 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0xb5,0xac] +sunpkd831 a0, a1 + +# CHECK-ASM-AND-OBJ: sunpkd832 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x35,0xad] +sunpkd832 a0, a1 + +# CHECK-ASM-AND-OBJ: swap8 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x85,0xad] +swap8 a0, a1 + +# CHECK-ASM-AND-OBJ: swap16 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x95,0xad] +swap16 a0, a1 + +# CHECK-ASM-AND-OBJ: uclip8 t0, a0, 3 +# CHECK-ASM: encoding: [0xff,0x02,0x35,0x8d] +uclip8 t0, a0, 3 + +# CHECK-ASM-AND-OBJ: uclip16 t0, a0, 4 +# CHECK-ASM: encoding: [0xff,0x02,0x45,0x85] +uclip16 t0, a0, 4 + +# CHECK-ASM-AND-OBJ: uclip32 a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0xf4] +uclip32 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: ucmple8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x3e] +ucmple8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ucmple16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x3c] +ucmple16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ucmplt8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x2e] +ucmplt8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ucmplt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x2c] +ucmplt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukadd8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x38] +ukadd8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukadd16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x30] +ukadd16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukadd64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0xb0] +ukadd64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: ukaddh a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x14] +ukaddh a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukaddw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x10] +ukaddw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukcras16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x34] +ukcras16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukcrsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x36] +ukcrsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukmar64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xb4] +ukmar64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukmsr64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xb6] +ukmsr64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukstas16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xe4] +ukstas16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukstsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xe6] +ukstsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uksub8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x3a] +uksub8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uksub16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x32] +uksub16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uksub64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0xb2] +uksub64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: uksubh a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x16] +uksubh a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uksubw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x12] +uksubw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umar64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xa4] +umar64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umaqa a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xcc] +umaqa a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umax8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x9a] +umax8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umax16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x92] +umax16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umin8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x98] +umin8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umin16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x90] +umin16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umsr64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xa6] +umsr64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umul8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xb8] +umul8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umulx8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xba] +umulx8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umul16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xb0] +umul16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umulx16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xb2] +umulx16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uradd8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x28] +uradd8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uradd8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x28] +uradd8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uradd64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0xa0] +uradd64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: uraddw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x30] +uraddw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: urcras16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x24] +urcras16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: urcrsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x26] +urcrsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: urstas16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xd4] +urstas16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: urcrsa16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x26] +urcrsa16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ursub8 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x2a] +ursub8 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ursub16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0x22] +ursub16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ursub64 a0, a2, a4 +# CHECK-ASM: encoding: [0x7f,0x15,0xe6,0xa2] +ursub64 a0, a2, a4 + +# CHECK-ASM-AND-OBJ: ursubw a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x32] +ursubw a0, a1, a2 + +# CHECK-ASM-AND-OBJ: wexti a0, a1, 5 +# CHECK-ASM: encoding: [0x7f,0x85,0x55,0xde] +wexti a0, a1, 5 + +# CHECK-ASM-AND-OBJ: wext a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xce] +wext a0, a1, a2 + +# CHECK-ASM-AND-OBJ: zunpkd810 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0xc5,0xac] +zunpkd810 a0, a1 + +# CHECK-ASM-AND-OBJ: zunpkd820 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0xd5,0xac] +zunpkd820 a0, a1 + +# CHECK-ASM-AND-OBJ: zunpkd830 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0xe5,0xac] +zunpkd830 a0, a1 + +# CHECK-ASM-AND-OBJ: zunpkd831 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0xf5,0xac] +zunpkd831 a0, a1 + +# CHECK-ASM-AND-OBJ: zunpkd832 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x75,0xad] +zunpkd832 a0, a1 Index: llvm/test/MC/RISCV/rv64p-invalid.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rv64p-invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-p < %s 2>&1 | FileCheck %s + +# Invalid immediates +srai.u a0, a1, 64 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 63] +bitrevi a0, a1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63] +insb a0, a1, 8 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 7] Index: llvm/test/MC/RISCV/rv64p-valid.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rv64p-valid.s @@ -0,0 +1,464 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-p < %s \ +# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-p < %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-RV32 %s + +# CHECK-ASM-AND-OBJ: add64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xc0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +add64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: radd64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x80] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +radd64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uradd64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xa0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +uradd64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kadd64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x90] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kadd64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukadd64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xb0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ukadd64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sub64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xc2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +sub64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rsub64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x82] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +rsub64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ursub64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xa2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ursub64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ksub64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x92] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ksub64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uksub64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xb2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +uksub64 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: bitrevi a0, a1, 63 +# CHECK-ASM: encoding: [0x7f,0x85,0xf5,0xeb] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +bitrevi a0, a1, 63 + +# CHECK-ASM-AND-OBJ: insb a0, a1, 7 +# CHECK-ASM: encoding: [0x7f,0x85,0x75,0xac] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +insb a0, a1, 7 + +# CHECK-ASM-AND-OBJ: srai.u a0, a1, 63 +# CHECK-ASM: encoding: [0x7f,0x95,0xf5,0xd7] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +srai.u a0, a1, 63 + + +# CHECK-ASM-AND-OBJ: add32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x40] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +add32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: cras32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x44] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +cras32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: crsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x46] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +crsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kabs32 a0, a1 +# CHECK-ASM: encoding: [0x7f,0x85,0x25,0xad] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kabs32 a0, a1 + +# CHECK-ASM-AND-OBJ: kadd32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x10] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kadd32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kcras32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x14] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kcras32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kcrsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x16] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kcrsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmbb16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xda] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kdmbb16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmbt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xea] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kdmbt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmtt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xfa] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kdmtt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmabb16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xd8] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kdmabb16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmabt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xe8] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kdmabt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kdmatt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xf8] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kdmatt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khmbb16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xdc] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +khmbb16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khmbt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xec] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +khmbt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: khmtt16 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xfc] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +khmtt16 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmabb32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x5a] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmabb32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmabt32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x6a] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmabt32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmatt32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x7a] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmatt32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmar64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0x94] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmada32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmaxda32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x4a] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmaxda32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmda32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x38] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmda32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmxda32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x3a] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmxda32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmads32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x5c] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmads32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmadrs32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x6c] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmadrs32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmaxds32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x7c] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmaxds32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmsda32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x4c] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmsda32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kmsxda32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x4e] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kmsxda32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ksll32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x64] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ksll32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslli32 a0, a1, 5 +# CHECK-ASM: encoding: +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kslli32 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: kslra32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x56] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kslra32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kslra32.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x66] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kslra32.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kstas32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xc0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kstas32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: kstsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xc2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +kstsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ksub32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x12] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ksub32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pkbb32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x0e] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +pkbb32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pkbt32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x1e] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +pkbt32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pktt32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x3e] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +pktt32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: pktb32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x2e] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +pktb32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: radd32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x00] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +radd32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rcras32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x04] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +rcras32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rcrsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x06] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +rcrsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rstas32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xb0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +rstas32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rstsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xb2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +rstsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: rsub32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x02] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +rsub32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sll32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x54] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +sll32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: slli32 a0, a1, 5 +# CHECK-ASM: encoding: +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +slli32 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: smax32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x92] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +smax32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: mulsr64 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0x95,0xc5,0xe0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +smbb32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smbt32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x18] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +smbt32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smtt32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x28] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +smtt32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: smin32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x90] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +smin32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sra32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x50] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +sra32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sra32.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x60] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +sra32.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: srai32 a0, a1, 5 +# CHECK-ASM: encoding: +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +srai32 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: srai32.u a0, a1, 5 +# CHECK-ASM: encoding: +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +srai32.u a0, a1, 5 + +# CHECK-ASM-AND-OBJ: sraiw.u a0, a1, 5 +# CHECK-ASM: encoding: +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +sraiw.u a0, a1, 5 + +# CHECK-ASM-AND-OBJ: srl32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x52] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +srl32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: srl32.u a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x62] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +srl32.u a0, a1, a2 + +# CHECK-ASM-AND-OBJ: srli32 a0, a1, 5 +# CHECK-ASM: encoding: +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +srli32 a0, a1, 5 + +# CHECK-ASM-AND-OBJ: srli32.u a0, a1, 5 +# CHECK-ASM: encoding: +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +srli32.u a0, a1, 5 + +# CHECK-ASM-AND-OBJ: stas32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xf0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +stas32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: stsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xf2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +stsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: sub32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x42] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +sub32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukadd32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x30] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ukadd32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukcras32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x34] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ukcras32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukcrsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x36] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ukcrsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukstas32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xe0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ukstas32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ukstsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xe2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ukstsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uksub32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x32] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +uksub32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umax32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xa2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +umax32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: umin32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xa0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +umin32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: uradd32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x20] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +uradd32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: urcras32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x24] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +urcras32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: urcrsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x26] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +urcrsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: urstas32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xd0] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +urstas32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: urstsa32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0xd2] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +urstsa32 a0, a1, a2 + +# CHECK-ASM-AND-OBJ: ursub32 a0, a1, a2 +# CHECK-ASM: encoding: [0x7f,0xa5,0xc5,0x22] +# CHECK-RV32: error: instruction requires the following: RV64I Base Instruction Set +ursub32 a0, a1, a2