Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1648,6 +1648,9 @@
     def : Pat<(vscale (sve_cntd_imm_neg i32:$imm)), (SUBXrs XZR, (CNTD_XPiI 31, $imm), 0)>;
   }
 
+  def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
+            (ADDVL_XXI GPR64:$op, $imm)>;
+
   // FIXME: BigEndian requires an additional REV instruction to satisfy the
   // constraint that none of the bits change when stored to memory as one
   // type, and and reloaded as another type.
Index: llvm/test/CodeGen/AArch64/split-vector-insert.ll
===================================================================
--- llvm/test/CodeGen/AArch64/split-vector-insert.ll
+++ llvm/test/CodeGen/AArch64/split-vector-insert.ll
@@ -29,27 +29,27 @@
 ; CHECK-NEXT:    lsl x10, x10, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
 ; CHECK-NEXT:    str q1, [x9, x10]
-; CHECK-NEXT:    addvl x10, sp, #1
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; CHECK-NEXT:    mov w9, #2
 ; CHECK-NEXT:    cmp x8, #2 // =2
 ; CHECK-NEXT:    csel x9, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #1
 ; CHECK-NEXT:    lsl x9, x9, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    str q2, [x10, x9]
-; CHECK-NEXT:    addvl x10, sp, #2
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    mov w9, #4
 ; CHECK-NEXT:    cmp x8, #4 // =4
 ; CHECK-NEXT:    csel x9, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #2
 ; CHECK-NEXT:    lsl x9, x9, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    str q3, [x10, x9]
-; CHECK-NEXT:    addvl x10, sp, #3
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #2, mul vl]
 ; CHECK-NEXT:    mov w9, #6
 ; CHECK-NEXT:    cmp x8, #6 // =6
 ; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #3
 ; CHECK-NEXT:    lsl x8, x8, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #3, mul vl]
 ; CHECK-NEXT:    str q4, [x10, x8]
@@ -82,27 +82,27 @@
 ; CHECK-NEXT:    lsl x10, x10, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
 ; CHECK-NEXT:    str q1, [x9, x10]
-; CHECK-NEXT:    addvl x10, sp, #1
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; CHECK-NEXT:    mov w9, #2
 ; CHECK-NEXT:    cmp x8, #2 // =2
 ; CHECK-NEXT:    csel x9, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #1
 ; CHECK-NEXT:    lsl x9, x9, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    str q2, [x10, x9]
-; CHECK-NEXT:    addvl x10, sp, #2
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    mov w9, #4
 ; CHECK-NEXT:    cmp x8, #4 // =4
 ; CHECK-NEXT:    csel x9, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #2
 ; CHECK-NEXT:    lsl x9, x9, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    str q3, [x10, x9]
-; CHECK-NEXT:    addvl x10, sp, #3
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp, #2, mul vl]
 ; CHECK-NEXT:    mov w9, #6
 ; CHECK-NEXT:    cmp x8, #6 // =6
 ; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    addvl x10, sp, #3
 ; CHECK-NEXT:    lsl x8, x8, #3
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp, #3, mul vl]
 ; CHECK-NEXT:    str q4, [x10, x8]
Index: llvm/test/CodeGen/AArch64/sve-gep.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-gep.ll
+++ llvm/test/CodeGen/AArch64/sve-gep.ll
@@ -8,8 +8,7 @@
 define <vscale x 2 x i64>* @scalar_of_scalable_1(<vscale x 2 x i64>* %base) {
 ; CHECK-LABEL: scalar_of_scalable_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #4
-; CHECK-NEXT:    add x0, x0, x8
+; CHECK-NEXT:    addvl x0, x0, #4
 ; CHECK-NEXT:    ret
   %d = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 4
   ret <vscale x 2 x i64>* %d
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
@@ -10,18 +11,19 @@
 
 define <vscale x 16 x i8> @ldnf1b(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %a)
   ret <vscale x 16 x i8> %load
 }
 
 define <vscale x 16 x i8> @ldnf1b_out_of_lower_bound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_out_of_lower_bound:
-; CHECK:       rdvl    x[[OFFSET:[0-9]+]], #-9
-; CHECK-NEXT:  add     x[[BASE:[0-9]+]], x0, x[[OFFSET]]
-; CHECK-NEXT:  ldnf1b { z0.b }, p0/z, [x[[BASE]]]
-; CHECK-NEXT:  ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    addvl x8, x0, #-9
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x8]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 -9
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
@@ -31,8 +33,9 @@
 
 define <vscale x 16 x i8> @ldnf1b_lower_bound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_lower_bound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 -8
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
@@ -42,8 +45,9 @@
 
 define <vscale x 16 x i8> @ldnf1b_inbound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_inbound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
@@ -53,8 +57,9 @@
 
 define <vscale x 16 x i8> @ldnf1b_upper_bound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_upper_bound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
@@ -64,10 +69,10 @@
 
 define <vscale x 16 x i8> @ldnf1b_out_of_upper_bound(<vscale x 16 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_out_of_upper_bound:
-; CHECK:       rdvl    x[[OFFSET:[0-9]+]], #8
-; CHECK-NEXT:  add     x[[BASE:[0-9]+]], x0, x[[OFFSET]]
-; CHECK-NEXT:  ldnf1b { z0.b }, p0/z, [x[[BASE]]]
-; CHECK-NEXT:  ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    addvl x8, x0, #8
+; CHECK-NEXT:    ldnf1b { z0.b }, p0/z, [x8]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 16 x i8>*
   %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 8
   %base_scalar = bitcast <vscale x 16 x i8>* %base to i8*
@@ -77,8 +82,9 @@
 
 define <vscale x 8 x i16> @ldnf1b_h(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_h:
-; CHECK: ldnf1b { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %a)
   %res = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %res
@@ -86,8 +92,9 @@
 
 define <vscale x 8 x i16> @ldnf1b_h_inbound(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_h_inbound:
-; CHECK: ldnf1b { z0.h }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.h }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 8 x i8>*
   %base = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 8 x i8>* %base to i8*
@@ -98,8 +105,9 @@
 
 define <vscale x 8 x i16> @ldnf1sb_h(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_h:
-; CHECK: ldnf1sb { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %a)
   %res = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %res
@@ -107,8 +115,9 @@
 
 define <vscale x 8 x i16> @ldnf1sb_h_inbound(<vscale x 8 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_h_inbound:
-; CHECK: ldnf1sb { z0.h }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.h }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 8 x i8>*
   %base = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 8 x i8>* %base to i8*
@@ -119,16 +128,18 @@
 
 define <vscale x 8 x i16> @ldnf1h(<vscale x 8 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16(<vscale x 8 x i1> %pg, i16* %a)
   ret <vscale x 8 x i16> %load
 }
 
 define <vscale x 8 x i16> @ldnf1h_inbound(<vscale x 8 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_inbound:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 8 x i16>*
   %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 8 x i16>* %base to i16*
@@ -138,24 +149,27 @@
 
 define <vscale x 8 x half> @ldnf1h_f16(<vscale x 8 x i1> %pg, half* %a) {
 ; CHECK-LABEL: ldnf1h_f16:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16(<vscale x 8 x i1> %pg, half* %a)
   ret <vscale x 8 x half> %load
 }
 
 define <vscale x 8 x bfloat> @ldnf1h_bf16(<vscale x 8 x i1> %pg, bfloat* %a) #0 {
 ; CHECK-LABEL: ldnf1h_bf16:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnf1.nxv8bf16(<vscale x 8 x i1> %pg, bfloat* %a)
   ret <vscale x 8 x bfloat> %load
 }
 
 define <vscale x 8 x half> @ldnf1h_f16_inbound(<vscale x 8 x i1> %pg, half* %a) {
 ; CHECK-LABEL: ldnf1h_f16_inbound:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast half* %a to <vscale x 8 x half>*
   %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 8 x half>* %base to half*
@@ -165,8 +179,9 @@
 
 define <vscale x 8 x bfloat> @ldnf1h_bf16_inbound(<vscale x 8 x i1> %pg, bfloat* %a) #0 {
 ; CHECK-LABEL: ldnf1h_bf16_inbound:
-; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.h }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast bfloat* %a to <vscale x 8 x bfloat>*
   %base = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 8 x bfloat>* %base to bfloat*
@@ -176,8 +191,9 @@
 
 define <vscale x 4 x i32> @ldnf1b_s(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_s:
-; CHECK: ldnf1b { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %a)
   %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
@@ -185,8 +201,9 @@
 
 define <vscale x 4 x i32> @ldnf1b_s_inbound(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_s_inbound:
-; CHECK: ldnf1b { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 4 x i8>*
   %base = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i8>* %base to i8*
@@ -197,8 +214,9 @@
 
 define <vscale x 4 x i32> @ldnf1sb_s(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_s:
-; CHECK: ldnf1sb { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %a)
   %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
@@ -206,8 +224,9 @@
 
 define <vscale x 4 x i32> @ldnf1sb_s_inbound(<vscale x 4 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_s_inbound:
-; CHECK: ldnf1sb { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 4 x i8>*
   %base = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i8>* %base to i8*
@@ -218,8 +237,9 @@
 
 define <vscale x 4 x i32> @ldnf1h_s(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_s:
-; CHECK: ldnf1h { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %a)
   %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
@@ -227,8 +247,9 @@
 
 define <vscale x 4 x i32> @ldnf1h_s_inbound(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_s_inbound:
-; CHECK: ldnf1h { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 4 x i16>*
   %base = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i16>* %base to i16*
@@ -239,8 +260,9 @@
 
 define <vscale x 4 x i32> @ldnf1sh_s(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_s:
-; CHECK: ldnf1sh { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sh { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %a)
   %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
   ret <vscale x 4 x i32> %res
@@ -248,8 +270,9 @@
 
 define <vscale x 4 x i32> @ldnf1sh_s_inbound(<vscale x 4 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_s_inbound:
-; CHECK: ldnf1sh { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sh { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 4 x i16>*
   %base = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i16>* %base to i16*
@@ -260,16 +283,18 @@
 
 define <vscale x 4 x i32> @ldnf1w(<vscale x 4 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w:
-; CHECK: ldnf1w { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32(<vscale x 4 x i1> %pg, i32* %a)
   ret <vscale x 4 x i32> %load
 }
 
 define <vscale x 4 x i32> @ldnf1w_inbound(<vscale x 4 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w_inbound:
-; CHECK: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i32* %a to <vscale x 4 x i32>*
   %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x i32>* %base to i32*
@@ -279,16 +304,18 @@
 
 define <vscale x 4 x float> @ldnf1w_f32(<vscale x 4 x i1> %pg, float* %a) {
 ; CHECK-LABEL: ldnf1w_f32:
-; CHECK: ldnf1w { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32(<vscale x 4 x i1> %pg, float* %a)
   ret <vscale x 4 x float> %load
 }
 
 define <vscale x 4 x float> @ldnf1w_f32_inbound(<vscale x 4 x i1> %pg, float* %a) {
 ; CHECK-LABEL: ldnf1w_f32_inbound:
-; CHECK: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.s }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast float* %a to <vscale x 4 x float>*
   %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 4 x float>* %base to float*
@@ -298,8 +325,9 @@
 
 define <vscale x 2 x i64> @ldnf1b_d(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_d:
-; CHECK: ldnf1b { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %a)
   %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
@@ -307,8 +335,9 @@
 
 define <vscale x 2 x i64> @ldnf1b_d_inbound(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1b_d_inbound:
-; CHECK: ldnf1b { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1b { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 2 x i8>*
   %base = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i8>* %base to i8*
@@ -319,8 +348,9 @@
 
 define <vscale x 2 x i64> @ldnf1sb_d(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_d:
-; CHECK: ldnf1sb { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %a)
   %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
@@ -328,8 +358,9 @@
 
 define <vscale x 2 x i64> @ldnf1sb_d_inbound(<vscale x 2 x i1> %pg, i8* %a) {
 ; CHECK-LABEL: ldnf1sb_d_inbound:
-; CHECK: ldnf1sb { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sb { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i8* %a to <vscale x 2 x i8>*
   %base = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i8>* %base to i8*
@@ -340,8 +371,9 @@
 
 define <vscale x 2 x i64> @ldnf1h_d(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_d:
-; CHECK: ldnf1h { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %a)
   %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
@@ -349,8 +381,9 @@
 
 define <vscale x 2 x i64> @ldnf1h_d_inbound(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1h_d_inbound:
-; CHECK: ldnf1h { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1h { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 2 x i16>*
   %base = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i16>* %base to i16*
@@ -361,8 +394,9 @@
 
 define <vscale x 2 x i64> @ldnf1sh_d(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_d:
-; CHECK: ldnf1sh { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sh { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %a)
   %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
@@ -370,8 +404,9 @@
 
 define <vscale x 2 x i64> @ldnf1sh_d_inbound(<vscale x 2 x i1> %pg, i16* %a) {
 ; CHECK-LABEL: ldnf1sh_d_inbound:
-; CHECK: ldnf1sh { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sh { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i16* %a to <vscale x 2 x i16>*
   %base = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i16>* %base to i16*
@@ -382,8 +417,9 @@
 
 define <vscale x 2 x i64> @ldnf1w_d(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w_d:
-; CHECK: ldnf1w { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %a)
   %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
@@ -391,8 +427,9 @@
 
 define <vscale x 2 x i64> @ldnf1w_d_inbound(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1w_d_inbound:
-; CHECK: ldnf1w { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1w { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i32* %a to <vscale x 2 x i32>*
   %base = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i32>* %base to i32*
@@ -403,8 +440,9 @@
 
 define <vscale x 2 x i64> @ldnf1sw_d(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1sw_d:
-; CHECK: ldnf1sw { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sw { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %a)
   %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %res
@@ -412,8 +450,9 @@
 
 define <vscale x 2 x i64> @ldnf1sw_d_inbound(<vscale x 2 x i1> %pg, i32* %a) {
 ; CHECK-LABEL: ldnf1sw_d_inbound:
-; CHECK: ldnf1sw { z0.d }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1sw { z0.d }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i32* %a to <vscale x 2 x i32>*
   %base = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base_scalable, i64 7
   %base_scalar = bitcast <vscale x 2 x i32>* %base to i32*
@@ -424,16 +463,18 @@
 
 define <vscale x 2 x i64> @ldnf1d(<vscale x 2 x i1> %pg, i64* %a) {
 ; CHECK-LABEL: ldnf1d:
-; CHECK: ldnf1d { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64(<vscale x 2 x i1> %pg, i64* %a)
   ret <vscale x 2 x i64> %load
 }
 
 define <vscale x 2 x i64> @ldnf1d_inbound(<vscale x 2 x i1> %pg, i64* %a) {
 ; CHECK-LABEL: ldnf1d_inbound:
-; CHECK: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast i64* %a to <vscale x 2 x i64>*
   %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 2 x i64>* %base to i64*
@@ -443,16 +484,18 @@
 
 define <vscale x 2 x double> @ldnf1d_f64(<vscale x 2 x i1> %pg, double* %a) {
 ; CHECK-LABEL: ldnf1d_f64:
-; CHECK: ldnf1d { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT:    ret
   %load = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64(<vscale x 2 x i1> %pg, double* %a)
   ret <vscale x 2 x double> %load
 }
 
 define <vscale x 2 x double> @ldnf1d_f64_inbound(<vscale x 2 x i1> %pg, double* %a) {
 ; CHECK-LABEL: ldnf1d_f64_inbound:
-; CHECK: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnf1d { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_scalable = bitcast double* %a to <vscale x 2 x double>*
   %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base_scalable, i64 1
   %base_scalar = bitcast <vscale x 2 x double>* %base to double*
Index: llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
+++ llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
@@ -43,8 +43,7 @@
 define <vscale x 16 x i8> @ld1b_out_of_upper_bound(<vscale x 16 x i8>* %a) {
 ; CHECK-LABEL: ld1b_out_of_upper_bound:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #8
-; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    addvl x8, x0, #8
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x8]
 ; CHECK-NEXT:    ret
@@ -56,8 +55,7 @@
 define <vscale x 16 x i8> @ld1b_out_of_lower_bound(<vscale x 16 x i8>* %a) {
 ; CHECK-LABEL: ld1b_out_of_lower_bound:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #-9
-; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    addvl x8, x0, #-9
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x8]
 ; CHECK-NEXT:    ret
Index: llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
+++ llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s 2>%t | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
@@ -11,13 +12,12 @@
 
 define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: imm_out_of_range:
-; CHECK-NEXT: rdvl x8, #8
-; CHECK-NEXT: add x8, x0, x8
-; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x{{[0-9]+}}]
-; CHECK-NEXT: rdvl x8, #-9
-; CHECK-NEXT: add x8, x0, x8
-; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x{{[0-9]+}}]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    addvl x8, x0, #8
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT:    addvl x8, x0, #-9
+; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8
   %data = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base_load,
                                                             i32 1,
@@ -35,9 +35,10 @@
 
 define void @test_masked_ldst_sv2i8(<vscale x 2 x i8> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i8:
-; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1b { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1b { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -8
   %data = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load,
                                                           i32 1,
@@ -53,9 +54,10 @@
 
 define void @test_masked_ldst_sv2i16(<vscale x 2 x i16> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i16:
-; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sh { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1h { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 -8
   %data = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load,
                                                             i32 1,
@@ -72,9 +74,10 @@
 
 define void @test_masked_ldst_sv2i32(<vscale x 2 x i32> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i32:
-; CHECK-NEXT: ld1sw { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1w { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sw { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1w { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -8
   %data = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load,
                                                             i32 1,
@@ -90,9 +93,10 @@
 
 define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i64:
-; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1d { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 -8
   %data = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base_load,
                                                             i32 1,
@@ -108,9 +112,10 @@
 
 define void @test_masked_ldst_sv2f16(<vscale x 2 x half> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2f16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1h { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x half>, <vscale x 2 x half>* %base, i64 -8
   %data = call <vscale x 2 x half> @llvm.masked.load.nxv2f16(<vscale x 2 x half>* %base_load,
                                                              i32 1,
@@ -127,9 +132,10 @@
 
 define void @test_masked_ldst_sv2f32(<vscale x 2 x float> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2f32:
-; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: st1w { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    st1w { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x float>, <vscale x 2 x float>* %base, i64 -8
   %data = call <vscale x 2 x float> @llvm.masked.load.nxv2f32(<vscale x 2 x float>* %base_load,
                                                               i32 1,
@@ -145,9 +151,10 @@
 
 define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2f64:
-; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-6, mul vl]
-; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x0, #-5, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0, #-6, mul vl]
+; CHECK-NEXT:    st1d { z0.d }, p0, [x0, #-5, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base, i64 -6
   %data = call <vscale x 2 x double> @llvm.masked.load.nxv2f64(<vscale x 2 x double>* %base_load,
                                                                i32 1,
@@ -165,8 +172,9 @@
 
 define <vscale x 2 x i64> @masked_zload_sv2i8_to_sv2i64(<vscale x 2 x i8>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv2i8_to_sv2i64:
-; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, #-4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1b { z0.d }, p0/z, [x0, #-4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -4
   %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load,
                                                           i32 1,
@@ -178,8 +186,9 @@
 
 define <vscale x 2 x i64> @masked_sload_sv2i8_to_sv2i64(<vscale x 2 x i8>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv2i8_to_sv2i64:
-; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, #-3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.d }, p0/z, [x0, #-3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -3
   %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load,
                                                           i32 1,
@@ -191,8 +200,9 @@
 
 define <vscale x 2 x i64> @masked_zload_sv2i16_to_sv2i64(<vscale x 2 x i16>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv2i16_to_sv2i64:
-; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 1
   %load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load,
                                                             i32 1,
@@ -204,8 +214,9 @@
 
 define <vscale x 2 x i64> @masked_sload_sv2i16_to_sv2i64(<vscale x 2 x i16>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv2i16_to_sv2i64:
-; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sh { z0.d }, p0/z, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 2
   %load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load,
                                                             i32 1,
@@ -217,8 +228,9 @@
 
 define <vscale x 2 x i64> @masked_zload_sv2i32_to_sv2i64(<vscale x 2 x i32>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv2i32_to_sv2i64:
-; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, #-2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0, #-2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -2
   %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load,
                                                             i32 1,
@@ -230,8 +242,9 @@
 
 define <vscale x 2 x i64> @masked_sload_sv2i32_to_sv2i64(<vscale x 2 x i32>* %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv2i32_to_sv2i64:
-; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sw { z0.d }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -1
   %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load,
                                                             i32 1,
@@ -245,8 +258,9 @@
 
 define void @masked_trunc_store_sv2i64_to_sv2i8(<vscale x 2 x i64> %val, <vscale x 2 x i8> *%base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i8:
-; CHECK-NEXT: st1b { z0.d }, p0, [x0, #3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1b { z0.d }, p0, [x0, #3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 3
   %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8>
   call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %trunc,
@@ -259,8 +273,9 @@
 
 define void @masked_trunc_store_sv2i64_to_sv2i16(<vscale x 2 x i64> %val, <vscale x 2 x i16> *%base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i16:
-; CHECK-NEXT: st1h { z0.d }, p0, [x0, #4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1h { z0.d }, p0, [x0, #4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 4
   %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16>
   call void @llvm.masked.store.nxv2i16(<vscale x 2 x i16> %trunc,
@@ -272,8 +287,9 @@
 
 define void @masked_trunc_store_sv2i64_to_sv2i32(<vscale x 2 x i64> %val, <vscale x 2 x i32> *%base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i32:
-; CHECK-NEXT: st1w { z0.d }, p0, [x0, #5, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1w { z0.d }, p0, [x0, #5, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 5
   %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32>
   call void @llvm.masked.store.nxv2i32(<vscale x 2 x i32> %trunc,
@@ -287,9 +303,10 @@
 
 define void @test_masked_ldst_sv4i8(<vscale x 4 x i8> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4i8:
-; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1b { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1b { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -1
   %data = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load,
                                                           i32 1,
@@ -305,9 +322,10 @@
 
 define void @test_masked_ldst_sv4i16(<vscale x 4 x i16> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4i16:
-; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sh { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1h { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 -1
   %data = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load,
                                                             i32 1,
@@ -323,9 +341,10 @@
 
 define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4i32:
-; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: st1w { z[[DATA]].s }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    st1w { z0.s }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base, i64 6
   %data = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(<vscale x 4 x i32>* %base_load,
                                                             i32 1,
@@ -341,9 +360,10 @@
 
 define void @test_masked_ldst_sv4f16(<vscale x 4 x half> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4f16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1h { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x half>, <vscale x 4 x half>* %base, i64 -1
   %data = call <vscale x 4 x half> @llvm.masked.load.nxv4f16(<vscale x 4 x half>* %base_load,
                                                              i32 1,
@@ -359,9 +379,10 @@
 
 define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4f32:
-; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1w { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1w { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base, i64 -1
   %data = call <vscale x 4 x float> @llvm.masked.load.nxv4f32(<vscale x 4 x float>* %base_load,
                                                               i32 1,
@@ -379,8 +400,9 @@
 
 define <vscale x 4 x i32> @masked_zload_sv4i8_to_sv4i32(<vscale x 4 x i8>* %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv4i8_to_sv4i32:
-; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, #-4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1b { z0.s }, p0/z, [x0, #-4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -4
   %load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load,
                                                           i32 1,
@@ -392,8 +414,9 @@
 
 define <vscale x 4 x i32> @masked_sload_sv4i8_to_sv4i32(<vscale x 4 x i8>* %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv4i8_to_sv4i32:
-; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0, #-3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.s }, p0/z, [x0, #-3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -3
   %load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load,
                                                           i32 1,
@@ -405,8 +428,9 @@
 
 define <vscale x 4 x i32> @masked_zload_sv4i16_to_sv4i32(<vscale x 4 x i16>* %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv4i16_to_sv4i32:
-; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 1
   %load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load,
                                                             i32 1,
@@ -418,8 +442,9 @@
 
 define <vscale x 4 x i32> @masked_sload_sv4i16_to_sv4i32(<vscale x 4 x i16>* %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv4i16_to_sv4i32:
-; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sh { z0.s }, p0/z, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 2
   %load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load,
                                                             i32 1,
@@ -433,8 +458,9 @@
 
 define void @masked_trunc_store_sv4i32_to_sv4i8(<vscale x 4 x i32> %val, <vscale x 4 x i8> *%base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv4i32_to_sv4i8:
-; CHECK-NEXT: st1b { z0.s }, p0, [x0, #3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1b { z0.s }, p0, [x0, #3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 3
   %trunc = trunc <vscale x 4 x i32> %val to <vscale x 4 x i8>
   call void @llvm.masked.store.nxv4i8(<vscale x 4 x i8> %trunc,
@@ -447,8 +473,9 @@
 
 define void @masked_trunc_store_sv4i32_to_sv4i16(<vscale x 4 x i32> %val, <vscale x 4 x i16> *%base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv4i32_to_sv4i16:
-; CHECK-NEXT: st1h { z0.s }, p0, [x0, #4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1h { z0.s }, p0, [x0, #4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 4
   %trunc = trunc <vscale x 4 x i32> %val to <vscale x 4 x i16>
   call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %trunc,
@@ -462,9 +489,10 @@
 
 define void @test_masked_ldst_sv8i8(<vscale x 8 x i8> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8i8:
-; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: st1b { z[[DATA]].h }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.h }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    st1b { z0.h }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 6
   %data = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load,
                                                           i32 1,
@@ -480,9 +508,10 @@
 
 define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8i16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base, i64 6
   %data = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(<vscale x 8 x i16>* %base_load,
                                                             i32 1,
@@ -498,9 +527,10 @@
 
 define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8f16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base, i64 -1
   %data = call <vscale x 8 x half> @llvm.masked.load.nxv8f16(<vscale x 8 x half>* %base_load,
                                                              i32 1,
@@ -516,9 +546,10 @@
 
 define void @test_masked_ldst_sv8bf16(<vscale x 8 x bfloat> * %base, <vscale x 8 x i1> %mask) nounwind #0 {
 ; CHECK-LABEL: test_masked_ldst_sv8bf16:
-; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    st1h { z0.h }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base, i64 -1
   %data = call <vscale x 8 x bfloat> @llvm.masked.load.nxv8bf16(<vscale x 8 x bfloat>* %base_load,
                                                                 i32 1,
@@ -536,8 +567,9 @@
 
 define <vscale x 8 x i16> @masked_zload_sv8i8_to_sv8i16(<vscale x 8 x i8>* %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_zload_sv8i8_to_sv8i16:
-; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0, #-4, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1b { z0.h }, p0/z, [x0, #-4, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 -4
   %load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load,
                                                           i32 1,
@@ -549,8 +581,9 @@
 
 define <vscale x 8 x i16> @masked_sload_sv8i8_to_sv8i16(<vscale x 8 x i8>* %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_sload_sv8i8_to_sv8i16:
-; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0, #-3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1sb { z0.h }, p0/z, [x0, #-3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 -3
   %load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load,
                                                           i32 1,
@@ -564,8 +597,9 @@
 
 define void @masked_trunc_store_sv8i16_to_sv8i8(<vscale x 8 x i16> %val, <vscale x 8 x i8> *%base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: masked_trunc_store_sv8i16_to_sv8i8:
-; CHECK-NEXT: st1b { z0.h }, p0, [x0, #3, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    st1b { z0.h }, p0, [x0, #3, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 3
   %trunc = trunc <vscale x 8 x i16> %val to <vscale x 8 x i8>
   call void @llvm.masked.store.nxv8i8(<vscale x 8 x i8> %trunc,
@@ -579,9 +613,10 @@
 
 define void @test_masked_ldst_sv16i8(<vscale x 16 x i8> * %base, <vscale x 16 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv16i8:
-; CHECK-NEXT: ld1b { z[[DATA:[0-9]+]].b }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: st1b { z[[DATA]].b }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    st1b { z0.b }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base, i64 6
   %data = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8(<vscale x 16 x i8>* %base_load,
                                                             i32 1,
Index: llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
+++ llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s 2>%t | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
@@ -11,13 +12,12 @@
 
 define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: imm_out_of_range:
-; CHECK-NEXT: rdvl x8, #8
-; CHECK-NEXT: add x8, x0, x8
-; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x{{[0-9]+}}]
-; CHECK-NEXT: rdvl x8, #-9
-; CHECK-NEXT: add x8, x0, x8
-; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x{{[0-9]+}}]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    addvl x8, x0, #8
+; CHECK-NEXT:    ldnt1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT:    addvl x8, x0, #-9
+; CHECK-NEXT:    stnt1d { z0.d }, p0, [x8]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8
   %base_load_bc = bitcast <vscale x 2 x i64>* %base_load to i64*
   %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
@@ -35,9 +35,10 @@
 
 define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2i64:
-; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, #-7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1d { z0.d }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:    stnt1d { z0.d }, p0, [x0, #-7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 -8
   %base_load_bc = bitcast <vscale x 2 x i64>* %base_load to i64*
   %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
@@ -52,9 +53,10 @@
 
 define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv2f64:
-; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-6, mul vl]
-; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, #-5, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1d { z0.d }, p0/z, [x0, #-6, mul vl]
+; CHECK-NEXT:    stnt1d { z0.d }, p0, [x0, #-5, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base, i64 -6
   %base_load_bc = bitcast <vscale x 2 x double>* %base_load to double*
   %data = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %mask,
@@ -71,9 +73,10 @@
 
 define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4i32:
-; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1w { z0.s }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    stnt1w { z0.s }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base, i64 6
   %base_load_bc = bitcast <vscale x 4 x i32>* %base_load to i32*
   %data = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %mask,
@@ -88,9 +91,10 @@
 
 define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv4f32:
-; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1w { z0.s }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    stnt1w { z0.s }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base, i64 -1
   %base_load_bc = bitcast <vscale x 4 x float>* %base_load to float*
   %data = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %mask,
@@ -108,9 +112,10 @@
 
 define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8i16:
-; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1h { z0.h }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    stnt1h { z0.h }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base, i64 6
   %base_load_bc = bitcast <vscale x 8 x i16>* %base_load to i16*
   %data = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %mask,
@@ -125,9 +130,10 @@
 
 define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv8f16:
-; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1h { z0.h }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    stnt1h { z0.h }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base, i64 -1
   %base_load_bc = bitcast <vscale x 8 x half>* %base_load to half*
   %data = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %mask,
@@ -142,9 +148,10 @@
 
 define void @test_masked_ldst_sv8bf16(<vscale x 8 x bfloat> * %base, <vscale x 8 x i1> %mask) nounwind #0 {
 ; CHECK-LABEL: test_masked_ldst_sv8bf16:
-; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl]
-; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1h { z0.h }, p0/z, [x0, #-1, mul vl]
+; CHECK-NEXT:    stnt1h { z0.h }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base, i64 -1
   %base_load_bc = bitcast <vscale x 8 x bfloat>* %base_load to bfloat*
   %data = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnt1.nxv8bf16(<vscale x 8 x i1> %mask,
@@ -161,9 +168,10 @@
 
 define void @test_masked_ldst_sv16i8(<vscale x 16 x i8> * %base, <vscale x 16 x i1> %mask) nounwind {
 ; CHECK-LABEL: test_masked_ldst_sv16i8:
-; CHECK-NEXT: ldnt1b { z[[DATA:[0-9]+]].b }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: stnt1b { z[[DATA]].b }, p0, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldnt1b { z0.b }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT:    stnt1b { z0.b }, p0, [x0, #7, mul vl]
+; CHECK-NEXT:    ret
   %base_load = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base, i64 6
   %base_load_bc = bitcast <vscale x 16 x i8>* %base_load to i8*
   %data = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %mask,
Index: llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
+++ llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
@@ -43,8 +43,7 @@
 define void @st1b_out_of_upper_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
 ; CHECK-LABEL: st1b_out_of_upper_bound:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #8
-; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    addvl x8, x0, #8
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    st1b { z0.b }, p0, [x8]
 ; CHECK-NEXT:    ret
@@ -56,8 +55,7 @@
 define void @st1b_out_of_lower_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
 ; CHECK-LABEL: st1b_out_of_lower_bound:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    rdvl x8, #-9
-; CHECK-NEXT:    add x8, x0, x8
+; CHECK-NEXT:    addvl x8, x0, #-9
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    st1b { z0.b }, p0, [x8]
 ; CHECK-NEXT:    ret