diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -959,13 +959,13 @@
   return false;
 }
 
-// Determines if it is a constant integer or a build vector of constant
+// Determines if it is a constant integer or a splat/build vector of constant
 // integers (and undefs).
 // Do not permit build vector implicit truncation.
 static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
   if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
     return !(Const->isOpaque() && NoOpaques);
-  if (N.getOpcode() != ISD::BUILD_VECTOR)
+  if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR)
     return false;
   unsigned BitWidth = N.getScalarValueSizeInBits();
   for (const SDValue &Op : N->op_values()) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -306,7 +306,8 @@
     return Match(Cst);
 
   // FIXME: Add support for vector UNDEF cases?
-  if (ISD::BUILD_VECTOR != Op.getOpcode())
+  if (ISD::BUILD_VECTOR != Op.getOpcode() &&
+      ISD::SPLAT_VECTOR != Op.getOpcode())
     return false;
 
   EVT SVT = Op.getValueType().getScalarType();
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5031,9 +5031,15 @@
     return SDValue();
 
   SDValue Shift, Factor;
-  if (VT.isVector()) {
+  if (VT.isFixedLengthVector()) {
     Shift = DAG.getBuildVector(ShVT, dl, Shifts);
     Factor = DAG.getBuildVector(VT, dl, Factors);
+  } else if (VT.isScalableVector()) {
+    assert(Shifts.size() == 1 && Factors.size() == 1 &&
+           "Expected matchUnaryPredicate to return one element for scalable "
+           "vectors");
+    Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]);
+    Factor = DAG.getSplatVector(VT, dl, Factors[0]);
   } else {
     Shift = Shifts[0];
     Factor = Factors[0];
@@ -5126,11 +5132,20 @@
     return SDValue();
 
   SDValue MagicFactor, Factor, Shift, ShiftMask;
-  if (VT.isVector()) {
+  if (VT.isFixedLengthVector()) {
     MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
     Factor = DAG.getBuildVector(VT, dl, Factors);
     Shift = DAG.getBuildVector(ShVT, dl, Shifts);
     ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks);
+  } else if (VT.isScalableVector()) {
+    assert(MagicFactors.size() == 1 && Factors.size() == 1 &&
+           Shifts.size() == 1 && ShiftMasks.size() == 1 &&
+           "Expected matchUnaryPredicate to return one element for scalable "
+           "vectors");
+    MagicFactor = DAG.getSplatVector(VT, dl, MagicFactors[0]);
+    Factor = DAG.getSplatVector(VT, dl, Factors[0]);
+    Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]);
+    ShiftMask = DAG.getSplatVector(VT, dl, ShiftMasks[0]);
   } else {
     MagicFactor = MagicFactors[0];
     Factor = Factors[0];
@@ -5244,11 +5259,19 @@
     return SDValue();
 
   SDValue PreShift, PostShift, MagicFactor, NPQFactor;
-  if (VT.isVector()) {
+  if (VT.isFixedLengthVector()) {
     PreShift = DAG.getBuildVector(ShVT, dl, PreShifts);
     MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
     NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors);
     PostShift = DAG.getBuildVector(ShVT, dl, PostShifts);
+  } else if (VT.isScalableVector()) {
+    assert(PreShifts.size() == 1 && MagicFactors.size() == 1 &&
+           NPQFactors.size() == 1 && PostShifts.size() == 1 &&
+           "Expected matchUnaryPredicate to return one for scalable vectors");
+    PreShift = DAG.getSplatVector(ShVT, dl, PreShifts[0]);
+    MagicFactor = DAG.getSplatVector(VT, dl, MagicFactors[0]);
+    NPQFactor = DAG.getSplatVector(VT, dl, NPQFactors[0]);
+    PostShift = DAG.getSplatVector(ShVT, dl, PostShifts[0]);
   } else {
     PreShift = PreShifts[0];
     MagicFactor = MagicFactors[0];
@@ -5300,8 +5323,10 @@
   Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift);
   Created.push_back(Q.getNode());
 
+  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+
   SDValue One = DAG.getConstant(1, dl, VT);
-  SDValue IsOne = DAG.getSetCC(dl, VT, N1, One, ISD::SETEQ);
+  SDValue IsOne = DAG.getSetCC(dl, SetCCVT, N1, One, ISD::SETEQ);
   return DAG.getSelect(dl, VT, IsOne, N0, Q);
 }
 
@@ -5728,7 +5753,7 @@
     return SDValue();
 
   SDValue PVal, AVal, KVal, QVal;
-  if (VT.isVector()) {
+  if (VT.isFixedLengthVector()) {
     if (HadOneDivisor) {
       // Try to turn PAmts into a splat, since we don't care about the values
       // that are currently '0'. If we can't, just keep '0'`s.
@@ -5747,6 +5772,15 @@
     AVal = DAG.getBuildVector(VT, DL, AAmts);
     KVal = DAG.getBuildVector(ShVT, DL, KAmts);
     QVal = DAG.getBuildVector(VT, DL, QAmts);
+  } else if (VT.isScalableVector()) {
+    assert(PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 &&
+           QAmts.size() == 1 &&
+           "Expected matchUnaryPredicate to return one element for scalable "
+           "vectors");
+    PVal = DAG.getSplatVector(VT, DL, PAmts[0]);
+    AVal = DAG.getSplatVector(VT, DL, AAmts[0]);
+    KVal = DAG.getSplatVector(ShVT, DL, KAmts[0]);
+    QVal = DAG.getSplatVector(VT, DL, QAmts[0]);
   } else {
     PVal = PAmts[0];
     AVal = AAmts[0];
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -382,6 +382,9 @@
       setOperationAction(ISD::UMIN, VT, Legal);
       setOperationAction(ISD::UMAX, VT, Legal);
 
+      setOperationAction(ISD::ROTL, VT, Expand);
+      setOperationAction(ISD::ROTR, VT, Expand);
+
       if (isTypeLegal(VT)) {
         // Custom-lower extensions and truncations from/to mask types.
         setOperationAction(ISD::ANY_EXTEND, VT, Custom);
@@ -2010,6 +2013,8 @@
     // Comparing with 0 may allow us to fold into bnez/beqz.
     SDValue LHS = N->getOperand(0);
     SDValue RHS = N->getOperand(1);
+    if (LHS.getValueType().isScalableVector())
+      break;
     auto CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
     APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1);
     if (isOneConstant(RHS) && ISD::isIntEqualitySetCC(CC) &&
diff --git a/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll b/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
--- a/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
@@ -593,7 +593,7 @@
 
 define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a){
 ; CHECK-LABEL: @asr_i8
-; CHECK-DAG: asr z0.b, z0.b, #8
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -603,7 +603,7 @@
 
 define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a){
 ; CHECK-LABEL: @asr_i16
-; CHECK-DAG: asr z0.h, z0.h, #16
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -613,7 +613,7 @@
 
 define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a){
 ; CHECK-LABEL: @asr_i32
-; CHECK-DAG: asr z0.s, z0.s, #32
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -623,7 +623,7 @@
 
 define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a){
 ; CHECK-LABEL: @asr_i64
-; CHECK-DAG: asr z0.d, z0.d, #64
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 64, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -677,7 +677,7 @@
 
 define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a){
 ; CHECK-LABEL: @lsr_i8
-; CHECK-DAG: lsr z0.b, z0.b, #8
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -687,7 +687,7 @@
 
 define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a){
 ; CHECK-LABEL: @lsr_i16
-; CHECK-DAG: lsr z0.h, z0.h, #16
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -697,7 +697,7 @@
 
 define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a){
 ; CHECK-LABEL: @lsr_i32
-; CHECK-DAG: lsr z0.s, z0.s, #32
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -707,7 +707,7 @@
 
 define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a){
 ; CHECK-LABEL: @lsr_i64
-; CHECK-DAG: lsr z0.d, z0.d, #64
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 64, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
@@ -26,9 +26,15 @@
 define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -85,9 +91,15 @@
 define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -120,9 +132,15 @@
 define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -155,9 +173,15 @@
 define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -190,9 +214,15 @@
 define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 7
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -225,9 +255,15 @@
 define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v8, v28, 7
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -260,9 +296,15 @@
 define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v16, v8, 7
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -295,9 +337,15 @@
 define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -330,9 +378,15 @@
 define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -365,9 +419,15 @@
 define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -400,9 +460,15 @@
 define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vsrl.vi v28, v26, 15
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -435,9 +501,15 @@
 define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vsrl.vi v8, v28, 15
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -470,9 +542,15 @@
 define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vadd.vi v8, v8, 0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v16, v8, 15
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -505,9 +583,15 @@
 define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vsub.vv v25, v25, v8
+; CHECK-NEXT:    vsra.vi v26, v25, 2
+; CHECK-NEXT:    vsrl.vi v25, v25, 31
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -540,9 +624,15 @@
 define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vsub.vv v25, v25, v8
+; CHECK-NEXT:    vsra.vi v26, v25, 2
+; CHECK-NEXT:    vsrl.vi v25, v25, 31
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -575,9 +665,15 @@
 define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vsub.vv v26, v26, v8
+; CHECK-NEXT:    vsra.vi v28, v26, 2
+; CHECK-NEXT:    vsrl.vi v26, v26, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -610,9 +706,15 @@
 define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vsub.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v8, v28, 2
+; CHECK-NEXT:    vsrl.vi v28, v28, 31
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -645,9 +747,15 @@
 define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v16, v8, 2
+; CHECK-NEXT:    vsrl.vi v8, v8, 31
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -687,9 +795,25 @@
 define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vmulh.vv v25, v8, v25
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v26, v25, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -729,9 +853,25 @@
 define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vmulh.vv v26, v8, v26
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v28, v26, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -771,9 +911,25 @@
 define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v12, a1
+; CHECK-NEXT:    vsll.vx v12, v12, a0
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vor.vv v28, v12, v28
+; CHECK-NEXT:    vmulh.vv v28, v8, v28
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v8, v28, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -813,9 +969,25 @@
 define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v24, a1
+; CHECK-NEXT:    vsll.vx v24, v24, a0
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vor.vv v16, v24, v16
+; CHECK-NEXT:    vmulh.vv v8, v8, v16
+; CHECK-NEXT:    vadd.vi v8, v8, 0
+; CHECK-NEXT:    vsra.vi v16, v8, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
@@ -26,9 +26,15 @@
 define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -61,9 +67,15 @@
 define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -96,9 +108,15 @@
 define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -131,9 +149,15 @@
 define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -166,9 +190,15 @@
 define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 7
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -201,9 +231,15 @@
 define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v8, v28, 7
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -236,9 +272,15 @@
 define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v16, v8, 7
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -271,9 +313,15 @@
 define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -306,9 +354,15 @@
 define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -341,9 +395,15 @@
 define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -376,9 +436,15 @@
 define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vsrl.vi v28, v26, 15
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -411,9 +477,15 @@
 define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vsrl.vi v8, v28, 15
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -446,9 +518,15 @@
 define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vadd.vi v8, v8, 0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v16, v8, 15
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -481,9 +559,16 @@
 define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -516,9 +601,16 @@
 define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -551,9 +643,16 @@
 define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 31
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -586,9 +685,16 @@
 define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v8, v28, 31
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -621,9 +727,16 @@
 define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v16, v8, 31
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -656,9 +769,22 @@
 define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v26, v25, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -691,9 +817,22 @@
 define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v28, v26, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -726,9 +865,22 @@
 define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v8, v28, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -761,9 +913,22 @@
 define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vadd.vi v8, v8, 0
+; CHECK-NEXT:    vsra.vi v16, v8, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
@@ -26,9 +26,13 @@
 define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -85,9 +89,13 @@
 define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -120,9 +128,13 @@
 define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -155,9 +167,13 @@
 define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -190,9 +206,13 @@
 define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 5
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -225,9 +245,13 @@
 define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 5
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -260,9 +284,13 @@
 define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 5
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -295,9 +323,14 @@
 define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -330,9 +363,14 @@
 define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -365,9 +403,14 @@
 define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -400,9 +443,14 @@
 define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 13
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -435,9 +483,14 @@
 define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 13
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -470,9 +523,14 @@
 define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -505,9 +563,14 @@
 define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -540,9 +603,14 @@
 define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -575,9 +643,14 @@
 define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -610,9 +683,14 @@
 define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v12, v12, 29
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -645,9 +723,14 @@
 define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    vsrl.vi v24, v24, 29
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -687,9 +770,21 @@
 define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    vmv.v.i v27, 1
+; CHECK-NEXT:    vsll.vx v27, v27, a0
+; CHECK-NEXT:    vsrl.vx v27, v27, a0
+; CHECK-NEXT:    vor.vv v26, v27, v26
+; CHECK-NEXT:    vmulhu.vv v26, v8, v26
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -729,9 +824,21 @@
 define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    vmv.v.i v30, 1
+; CHECK-NEXT:    vsll.vx v30, v30, a0
+; CHECK-NEXT:    vsrl.vx v30, v30, a0
+; CHECK-NEXT:    vor.vv v28, v30, v28
+; CHECK-NEXT:    vmulhu.vv v28, v8, v28
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -771,9 +878,21 @@
 define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v12, v12, a0
+; CHECK-NEXT:    vmv.v.i v16, 1
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    vor.vv v12, v16, v12
+; CHECK-NEXT:    vmulhu.vv v12, v8, v12
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -813,9 +932,21 @@
 define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v24, v24, a0
+; CHECK-NEXT:    vmv.v.i v0, 1
+; CHECK-NEXT:    vsll.vx v0, v0, a0
+; CHECK-NEXT:    vsrl.vx v0, v0, a0
+; CHECK-NEXT:    vor.vv v24, v0, v24
+; CHECK-NEXT:    vmulhu.vv v24, v8, v24
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
@@ -26,9 +26,13 @@
 define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -61,9 +65,13 @@
 define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -96,9 +104,13 @@
 define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -131,9 +143,13 @@
 define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -166,9 +182,13 @@
 define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 5
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -201,9 +221,13 @@
 define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 5
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -236,9 +260,13 @@
 define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 5
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -271,9 +299,14 @@
 define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -306,9 +339,14 @@
 define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -341,9 +379,14 @@
 define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -376,9 +419,14 @@
 define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 13
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -411,9 +459,14 @@
 define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 13
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -446,9 +499,14 @@
 define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -481,9 +539,14 @@
 define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -516,9 +579,14 @@
 define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -551,9 +619,14 @@
 define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -586,9 +659,14 @@
 define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -621,9 +699,14 @@
 define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 29
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -656,9 +739,16 @@
 define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -691,9 +781,16 @@
 define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -726,9 +823,16 @@
 define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -761,9 +865,16 @@
 define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+; Test that the prepareSREMEqFold optimization doesn't crash on scalable
+; vector types. RVV doesn't have ROTR or ROTL operations so the optimization
+; itself doesn't kick in.
+define <vscale x 4 x i1> @srem_eq_fold_nxv4i8(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: srem_eq_fold_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 43
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, 6
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v25, v8, v25
+; CHECK-NEXT:    vmseq.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %head_six = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
+  %splat_six = shufflevector <vscale x 4 x i8> %head_six, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %rem = srem <vscale x 4 x i8> %va, %splat_six
+
+  %cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer
+  ret <vscale x 4 x i1> %cc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
@@ -26,9 +26,18 @@
 define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -61,9 +70,18 @@
 define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -96,9 +114,18 @@
 define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -131,9 +158,18 @@
 define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -166,9 +202,18 @@
 define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 7
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -201,9 +246,18 @@
 define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v12, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v12, v28, 7
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -236,9 +290,18 @@
 define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v24, v8, 0
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vsrl.vi v24, v16, 7
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -271,9 +334,18 @@
 define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -306,9 +378,18 @@
 define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -341,9 +422,18 @@
 define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -376,9 +466,18 @@
 define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vsrl.vi v28, v26, 15
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -411,9 +510,18 @@
 define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vsrl.vi v12, v28, 15
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -446,9 +554,18 @@
 define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vadd.vi v16, v16, 0
+; CHECK-NEXT:    vsra.vi v16, v16, 1
+; CHECK-NEXT:    vsrl.vi v24, v16, 15
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -481,9 +598,18 @@
 define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vsub.vv v25, v25, v8
+; CHECK-NEXT:    vsra.vi v26, v25, 2
+; CHECK-NEXT:    vsrl.vi v25, v25, 31
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -516,9 +642,18 @@
 define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vsub.vv v25, v25, v8
+; CHECK-NEXT:    vsra.vi v26, v25, 2
+; CHECK-NEXT:    vsrl.vi v25, v25, 31
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -551,9 +686,18 @@
 define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vsub.vv v26, v26, v8
+; CHECK-NEXT:    vsra.vi v28, v26, 2
+; CHECK-NEXT:    vsrl.vi v26, v26, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -586,9 +730,18 @@
 define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vsub.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v12, v28, 2
+; CHECK-NEXT:    vsrl.vi v28, v28, 31
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -621,9 +774,18 @@
 define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsub.vv v16, v16, v8
+; CHECK-NEXT:    vsra.vi v24, v16, 2
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -663,9 +825,28 @@
 define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vmulh.vv v25, v8, v25
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v26, v25, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -705,9 +886,28 @@
 define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vmulh.vv v26, v8, v26
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v28, v26, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -747,9 +947,28 @@
 define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v12, a1
+; CHECK-NEXT:    vsll.vx v12, v12, a0
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vor.vv v28, v12, v28
+; CHECK-NEXT:    vmulh.vv v28, v8, v28
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v12, v28, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -789,9 +1008,28 @@
 define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v24, a1
+; CHECK-NEXT:    vsll.vx v24, v24, a0
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vor.vv v16, v24, v16
+; CHECK-NEXT:    vmulh.vv v16, v8, v16
+; CHECK-NEXT:    vadd.vi v16, v16, 0
+; CHECK-NEXT:    vsra.vi v24, v16, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
@@ -26,9 +26,18 @@
 define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -61,9 +70,18 @@
 define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -96,9 +114,18 @@
 define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -131,9 +158,18 @@
 define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -166,9 +202,18 @@
 define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 7
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -201,9 +246,18 @@
 define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v12, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v12, v28, 7
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -236,9 +290,18 @@
 define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v24, v8, 0
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vsrl.vi v24, v16, 7
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -271,9 +334,18 @@
 define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -306,9 +378,18 @@
 define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -341,9 +422,18 @@
 define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -376,9 +466,18 @@
 define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vsrl.vi v28, v26, 15
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -411,9 +510,18 @@
 define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vsrl.vi v12, v28, 15
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -446,9 +554,18 @@
 define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vadd.vi v16, v16, 0
+; CHECK-NEXT:    vsra.vi v16, v16, 1
+; CHECK-NEXT:    vsrl.vi v24, v16, 15
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -481,9 +598,19 @@
 define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -516,9 +643,19 @@
 define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -551,9 +688,19 @@
 define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 31
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -586,9 +733,19 @@
 define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v12, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v12, v28, 31
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -621,9 +778,19 @@
 define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v24, v8, 0
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vsrl.vi v24, v16, 31
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -656,9 +823,25 @@
 define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v26, v25, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -691,9 +874,25 @@
 define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v28, v26, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -726,9 +925,25 @@
 define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v12, v28, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -761,9 +976,25 @@
 define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vadd.vi v16, v16, 0
+; CHECK-NEXT:    vsra.vi v24, v16, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
@@ -26,9 +26,16 @@
 define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -61,9 +68,16 @@
 define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -96,9 +110,16 @@
 define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -131,9 +152,16 @@
 define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -166,9 +194,16 @@
 define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 5
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -201,9 +236,16 @@
 define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 5
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -236,9 +278,16 @@
 define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 5
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -271,9 +320,17 @@
 define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -306,9 +363,17 @@
 define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -341,9 +406,17 @@
 define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -376,9 +449,17 @@
 define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 13
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -411,9 +492,17 @@
 define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 13
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -446,9 +535,17 @@
 define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -481,9 +578,17 @@
 define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -516,9 +621,17 @@
 define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -551,9 +664,17 @@
 define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v26, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -586,9 +707,17 @@
 define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v12, v12, 29
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v28, v12, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -621,9 +750,17 @@
 define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    vsrl.vi v24, v24, 29
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v16, v24, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -663,9 +800,24 @@
 define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    vmv.v.i v27, 1
+; CHECK-NEXT:    vsll.vx v27, v27, a0
+; CHECK-NEXT:    vsrl.vx v27, v27, a0
+; CHECK-NEXT:    vor.vv v26, v27, v26
+; CHECK-NEXT:    vmulhu.vv v26, v8, v26
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -705,9 +857,24 @@
 define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    vmv.v.i v30, 1
+; CHECK-NEXT:    vsll.vx v30, v30, a0
+; CHECK-NEXT:    vsrl.vx v30, v30, a0
+; CHECK-NEXT:    vor.vv v28, v30, v28
+; CHECK-NEXT:    vmulhu.vv v28, v8, v28
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v26, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -747,9 +914,24 @@
 define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v12, v12, a0
+; CHECK-NEXT:    vmv.v.i v16, 1
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    vor.vv v12, v16, v12
+; CHECK-NEXT:    vmulhu.vv v12, v8, v12
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v28, v12, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -789,9 +971,24 @@
 define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v24, v24, a0
+; CHECK-NEXT:    vmv.v.i v0, 1
+; CHECK-NEXT:    vsll.vx v0, v0, a0
+; CHECK-NEXT:    vsrl.vx v0, v0, a0
+; CHECK-NEXT:    vor.vv v24, v0, v24
+; CHECK-NEXT:    vmulhu.vv v24, v8, v24
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v16, v24, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
@@ -26,9 +26,16 @@
 define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -61,9 +68,16 @@
 define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -96,9 +110,16 @@
 define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -131,9 +152,16 @@
 define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -166,9 +194,16 @@
 define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 5
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -201,9 +236,16 @@
 define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 5
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -236,9 +278,16 @@
 define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 5
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -271,9 +320,17 @@
 define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -306,9 +363,17 @@
 define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -341,9 +406,17 @@
 define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -376,9 +449,17 @@
 define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 13
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -411,9 +492,17 @@
 define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 13
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -446,9 +535,17 @@
 define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -481,9 +578,17 @@
 define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -516,9 +621,17 @@
 define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -551,9 +664,17 @@
 define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -586,9 +707,17 @@
 define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -621,9 +750,17 @@
 define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 29
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -656,9 +793,19 @@
 define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -691,9 +838,19 @@
 define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v26, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -726,9 +883,19 @@
 define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v28, v12, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -761,9 +928,19 @@
 define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v16, v24, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer