diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2735,9 +2735,7 @@
   assert(LdNode && LdNode->getOffset().isUndef()
          && "Unexpected node type");
 
-  unsigned alignment = LdNode->getAlignment();
-  if (alignment > 8)
-    alignment = 8;
+  Align alignment = commonAlignment(LdNode->getOriginalAlign(), 8);
 
   SDValue Hi64 =
       DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(),
@@ -2747,7 +2745,8 @@
                               LdNode->getBasePtr(),
                               DAG.getConstant(8, dl, addrVT));
   SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr,
-                             LdNode->getPointerInfo(), alignment);
+                             LdNode->getPointerInfo().getWithOffset(8),
+                             alignment);
 
   SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
   SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
@@ -2802,20 +2801,20 @@
                                     StNode->getValue(),
                                     SubRegOdd);
 
-  unsigned alignment = StNode->getAlignment();
-  if (alignment > 8)
-    alignment = 8;
+  Align alignment = commonAlignment(StNode->getOriginalAlign(), 8);
 
   SDValue OutChains[2];
   OutChains[0] =
       DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0),
-                   StNode->getBasePtr(), MachinePointerInfo(), alignment);
+                   StNode->getBasePtr(), StNode->getPointerInfo(),
+                   alignment);
   EVT addrVT = StNode->getBasePtr().getValueType();
   SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
                               StNode->getBasePtr(),
                               DAG.getConstant(8, dl, addrVT));
   OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), LoPtr,
-                              MachinePointerInfo(), alignment);
+                              StNode->getPointerInfo().getWithOffset(8),
+                              alignment);
   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
 }
 
@@ -2834,7 +2833,8 @@
     SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
     SDValue Chain = DAG.getStore(
         St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
-        St->getAlignment(), St->getMemOperand()->getFlags(), St->getAAInfo());
+        St->getOriginalAlign(), St->getMemOperand()->getFlags(),
+        St->getAAInfo());
     return Chain;
   }
 
@@ -3400,8 +3400,9 @@
     SDLoc dl(N);
     SDValue LoadRes = DAG.getExtLoad(
         Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(),
-        Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(),
-        Ld->getMemOperand()->getFlags(), Ld->getAAInfo());
+        Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32,
+        Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags(),
+        Ld->getAAInfo());
 
     SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
     Results.push_back(Res);
diff --git a/llvm/test/CodeGen/SPARC/fp128-split.ll b/llvm/test/CodeGen/SPARC/fp128-split.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/SPARC/fp128-split.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=sparcv9-unknown-linux < %s | FileCheck %s
+
+; Check that the fp128 load/store is correctly split.
+
+define fp128 @testcase(fp128 %0) {
+; CHECK-LABEL: testcase:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ! %bb.0: ! %Entry
+; CHECK-NEXT:    add %sp, -160, %sp
+; CHECK-NEXT:    .cfi_def_cfa_register %fp
+; CHECK-NEXT:    .cfi_window_save
+; CHECK-NEXT:    .cfi_register %o7, %i7
+; CHECK-NEXT:    add %sp, 2191, %o0
+; CHECK-NEXT:    or %o0, 8, %o0
+; CHECK-NEXT:    std %f2, [%o0]
+; CHECK-NEXT:    std %f0, [%sp+2191]
+; CHECK-NEXT:    ldx [%o0], %o0
+; CHECK-NEXT:    ldx [%sp+2191], %o1
+; CHECK-NEXT:    srlx %o0, 32, %o2
+; CHECK-NEXT:    srlx %o1, 32, %o3
+; CHECK-NEXT:    addcc %o0, -1, %o0
+; CHECK-NEXT:    addxcc %o2, -1, %o2
+; CHECK-NEXT:    addxcc %o1, -1, %o1
+; CHECK-NEXT:    addxcc %o3, -1, %o3
+; CHECK-NEXT:    srl %o0, 0, %o0
+; CHECK-NEXT:    sllx %o2, 32, %o2
+; CHECK-NEXT:    or %o2, %o0, %o0
+; CHECK-NEXT:    add %sp, 2175, %o2
+; CHECK-NEXT:    or %o2, 8, %o2
+; CHECK-NEXT:    stx %o0, [%o2]
+; CHECK-NEXT:    srl %o1, 0, %o0
+; CHECK-NEXT:    sllx %o3, 32, %o1
+; CHECK-NEXT:    or %o1, %o0, %o0
+; CHECK-NEXT:    stx %o0, [%sp+2175]
+; CHECK-NEXT:    ldd [%sp+2175], %f0
+; CHECK-NEXT:    ldd [%o2], %f2
+; CHECK-NEXT:    retl
+; CHECK-NEXT:    add %sp, 160, %sp
+Entry:
+  %1 = bitcast fp128 %0 to i128
+  %2 = add i128 %1, -1
+  %3 = bitcast i128 %2 to fp128
+  ret fp128 %3
+}