diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -45,6 +45,15 @@ FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>; } +multiclass FPUnaryD_mc funct7, RegisterClass rdty, RegisterClass rs1ty, + string OpcodeStr, bits<5> rs2val> { + def _gen : FPUnaryOp_gen; + def _def : FPUnaryOp_def; + def : InstAlias(NAME # "_gen") + rdty:$rd, rs1ty:$rs1, 0b111)>; +} + let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class FPALUD_rr funct7, bits<3> funct3, string opcodestr> : RVInstR, Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>; -def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">, - Sched<[WriteFSqrt64, ReadFSqrt64]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; +defm FSQRT_D : FPUnaryD_mc<0b0101101, FPR64, FPR64, "fsqrt.d", 0b00000>, + Sched<[WriteFSqrt64, ReadFSqrt64]>; def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">, Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>; @@ -112,11 +118,8 @@ def FMAX_D : FPALUD_rr<0b0010101, 0b001, "fmax.d">, Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>; -def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d">, - Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]> { - let rs2 = 0b00001; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_S_D : FPUnaryD_mc<0b0100000, FPR32, FPR64, "fcvt.s.d", 0b00001>, + Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>; def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s">, Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]> { @@ -132,17 +135,10 @@ let rs2 = 0b00000; } -def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">, - Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">, - Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]> { - let rs2 = 0b00001; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_W_D : FPUnaryD_mc<0b1100001, GPR, FPR64, "fcvt.w.d", 0b00000>, + Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; +defm FCVT_WU_D : FPUnaryD_mc<0b1100001, GPR, FPR64, "fcvt.wu.d", 0b00001>, + Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">, Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]> { @@ -156,34 +152,20 @@ } // Predicates = [HasStdExtD] let Predicates = [HasStdExtD, IsRV64] in { -def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d">, - Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> { - let rs2 = 0b00010; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d">, - Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]> { - let rs2 = 0b00011; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_L_D : FPUnaryD_mc<0b1100001, GPR, FPR64, "fcvt.l.d", 0b00010>, + Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; +defm FCVT_LU_D : FPUnaryD_mc<0b1100001, GPR, FPR64, "fcvt.lu.d", 0b00011>, + Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d">, Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]> { let rs2 = 0b00000; } -def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l">, - Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> { - let rs2 = 0b00010; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu">, - Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]> { - let rs2 = 0b00011; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_D_L : FPUnaryD_mc<0b1101001, FPR64, GPR, "fcvt.d.l", 0b00010>, + Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; +defm FCVT_D_LU : FPUnaryD_mc<0b1101001, FPR64, GPR, "fcvt.d.lu", 0b00011>, + Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x">, Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]> { @@ -226,7 +208,7 @@ /// Float conversion operations // f64 -> f32, f32 -> f64 -def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>; +def : Pat<(fpround FPR64:$rs1), (FCVT_S_D_def FPR64:$rs1)>; def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>; // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so @@ -239,7 +221,7 @@ def : Pat<(fmul FPR64:$rs1, FPR64:$rs2), (FMUL_D_def $rs1, $rs2)>; def : Pat<(fdiv FPR64:$rs1, FPR64:$rs2), (FDIV_D_def $rs1, $rs2)>; -def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>; +def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D_def FPR64:$rs1)>; def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>; def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; @@ -247,8 +229,7 @@ def : PatFpr64Fpr64; def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>; -def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, - 0b111))>; +def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D_def $rs2))>; // fmadd: rs1 * rs2 + rs3 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3), @@ -316,8 +297,8 @@ def : Pat<(f64 (fpimm0)), (FCVT_D_W (i32 X0))>; // double->[u]int. Round-to-zero must be used. -def : Pat<(i32 (fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, 0b001)>; -def : Pat<(i32 (fp_to_uint FPR64:$rs1)), (FCVT_WU_D FPR64:$rs1, 0b001)>; +def : Pat<(i32 (fp_to_sint FPR64:$rs1)), (FCVT_W_D_gen FPR64:$rs1, 0b001)>; +def : Pat<(i32 (fp_to_uint FPR64:$rs1)), (FCVT_WU_D_gen FPR64:$rs1, 0b001)>; // [u]int->double. def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1)>; @@ -338,16 +319,16 @@ // We match the single case below because fcvt.wu.d sign-extends its result so // is cheaper than fcvt.lu.d+sext.w. def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR64:$rs1)), i32), - (FCVT_WU_D $rs1, 0b001)>; + (FCVT_WU_D_gen $rs1, 0b001)>; // [u]int32->fp def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W $rs1)>; def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU $rs1)>; -def : Pat<(i64 (fp_to_sint FPR64:$rs1)), (FCVT_L_D FPR64:$rs1, 0b001)>; -def : Pat<(i64 (fp_to_uint FPR64:$rs1)), (FCVT_LU_D FPR64:$rs1, 0b001)>; +def : Pat<(i64 (fp_to_sint FPR64:$rs1)), (FCVT_L_D_gen FPR64:$rs1, 0b001)>; +def : Pat<(i64 (fp_to_uint FPR64:$rs1)), (FCVT_LU_D_gen FPR64:$rs1, 0b001)>; -// [u]int64->fp. Match GCC and default to using dynamic rounding mode. -def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, 0b111)>; -def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, 0b111)>; +// [u]int64->fp. +def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L_def GPR:$rs1)>; +def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU_def GPR:$rs1)>; } // Predicates = [HasStdExtD, IsRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -105,21 +105,38 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class FPUnaryOp_r funct7, bits<3> funct3, RegisterClass rdty, - RegisterClass rs1ty, string opcodestr> + RegisterClass rs1ty, string opcodestr> : RVInstR; -let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in -class FPUnaryOp_r_frm funct7, RegisterClass rdty, RegisterClass rs1ty, - string opcodestr> - : RVInstRFrm; +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { + class FPUnaryOp_gen funct7, RegisterClass rdty, RegisterClass rs1ty, + string opcodestr, bits<5> rs2val> + : RVInstRFrm { + let Defs = [FFLAGSReg]; + let Uses = [FRMReg]; + let rs2 = rs2val; + } -class FPUnaryOpDynFrmAlias - : InstAlias; + class FPUnaryOp_def funct7, RegisterClass rdty, RegisterClass rs1ty, + string opcodestr, bits<5> rs2val> + : RVInstRFrm { + let funct3 = 0b000; + let rs2 = rs2val; + } +} + +multiclass FPUnaryS_mc funct7, RegisterClass rdty, RegisterClass rs1ty, + string OpcodeStr, bits<5> rs2val> { + def _gen : FPUnaryOp_gen; + def _def : FPUnaryOp_def; + def : InstAlias(NAME # "_gen") + rdty:$rd, rs1ty:$rs1, 0b111)>; +} let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class FPCmpS_rr funct3, string opcodestr> @@ -165,11 +182,8 @@ defm FDIV_S : FPALUS_mc<0b0001100, "fdiv.s">, Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>; -def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">, - Sched<[WriteFSqrt32, ReadFSqrt32]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; +defm FSQRT_S : FPUnaryS_mc<0b0101100, FPR32, FPR32, "fsqrt.s", 0b00000>, + Sched<[WriteFSqrt32, ReadFSqrt32]>; def FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">, Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; @@ -182,17 +196,11 @@ def FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">, Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>; -def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">, - Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_W_S : FPUnaryS_mc<0b1100000, GPR, FPR32, "fcvt.w.s", 0b00000>, + Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>; -def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">, - Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { - let rs2 = 0b00001; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_WU_S : FPUnaryS_mc<0b1100000, GPR, FPR32, "fcvt.wu.s", 0b00001>, + Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>; def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">, Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> { @@ -208,17 +216,11 @@ let rs2 = 0b00000; } -def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">, - Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_S_W : FPUnaryS_mc<0b1101000, FPR32, GPR, "fcvt.s.w", 0b00000>, + Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>; -def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu">, - Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { - let rs2 = 0b00001; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_S_WU : FPUnaryS_mc<0b1101000, FPR32, GPR, "fcvt.s.wu", 0b00001>, + Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>; def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x">, Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]> { @@ -227,29 +229,14 @@ } // Predicates = [HasStdExtF] let Predicates = [HasStdExtF, IsRV64] in { -def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s">, - Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { - let rs2 = 0b00010; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s">, - Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { - let rs2 = 0b00011; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l">, - Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { - let rs2 = 0b00010; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu">, - Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { - let rs2 = 0b00011; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_L_S : FPUnaryS_mc<0b1100000, GPR, FPR32, "fcvt.l.s", 0b00010>, + Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>; +defm FCVT_LU_S : FPUnaryS_mc<0b1100000, GPR, FPR32, "fcvt.lu.s", 0b00011>, + Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>; +defm FCVT_S_L : FPUnaryS_mc<0b1101000, FPR32, GPR, "fcvt.s.l", 0b00010>, + Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>; +defm FCVT_S_LU : FPUnaryS_mc<0b1101000, FPR32, GPR, "fcvt.s.lu", 0b00011>, + Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>; } // Predicates = [HasStdExtF, IsRV64] //===----------------------------------------------------------------------===// @@ -333,7 +320,7 @@ def : Pat<(fmul FPR32:$rs1, FPR32:$rs2), (FMUL_S_def $rs1, $rs2)>; def : Pat<(fdiv FPR32:$rs1, FPR32:$rs2), (FDIV_S_def $rs1, $rs2)>; -def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; +def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S_def FPR32:$rs1)>; def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; @@ -393,12 +380,12 @@ def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>; // float->[u]int. Round-to-zero must be used. -def : Pat<(i32 (fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>; -def : Pat<(i32 (fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>; +def : Pat<(i32 (fp_to_sint FPR32:$rs1)), (FCVT_W_S_gen $rs1, 0b001)>; +def : Pat<(i32 (fp_to_uint FPR32:$rs1)), (FCVT_WU_S_gen $rs1, 0b001)>; -// [u]int->float. Match GCC and default to using dynamic rounding mode. -def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>; -def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; +// [u]int->float. +def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W_def $rs1)>; +def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU_def $rs1)>; } // Predicates = [HasStdExtF, IsRV32] let Predicates = [HasStdExtF, IsRV64] in { @@ -413,15 +400,15 @@ // We match the single case below because fcvt.wu.s sign-extends its result so // is cheaper than fcvt.lu.s+sext.w. def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32), - (FCVT_WU_S $rs1, 0b001)>; + (FCVT_WU_S_gen $rs1, 0b001)>; // FP->[u]int64 -def : Pat<(i64 (fp_to_sint FPR32:$rs1)), (FCVT_L_S $rs1, 0b001)>; -def : Pat<(i64 (fp_to_uint FPR32:$rs1)), (FCVT_LU_S $rs1, 0b001)>; - -// [u]int->fp. Match GCC and default to using dynamic rounding mode. -def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W $rs1, 0b111)>; -def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>; -def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>; -def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>; +def : Pat<(i64 (fp_to_sint FPR32:$rs1)), (FCVT_L_S_gen $rs1, 0b001)>; +def : Pat<(i64 (fp_to_uint FPR32:$rs1)), (FCVT_LU_S_gen $rs1, 0b001)>; + +// [u]int->fp. +def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W_def $rs1)>; +def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU_def $rs1)>; +def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L_def $rs1)>; +def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU_def $rs1)>; } // Predicates = [HasStdExtF, IsRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -47,6 +47,15 @@ FPR16:$rd, FPR16:$rs1, FPR16:$rs2, 0b111)>; } +multiclass FPUnaryH_mc funct7, RegisterClass rdty, RegisterClass rs1ty, + string OpcodeStr, bits<5> rs2val> { + def _gen : FPUnaryOp_gen; + def _def : FPUnaryOp_def; + def : InstAlias(NAME # "_gen") + rdty:$rd, rs1ty:$rs1, 0b111)>; +} + let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class FPALUH_rr funct7, bits<3> funct3, string opcodestr> : RVInstR, Sched<[]>; -def FSQRT_H : FPUnaryOp_r_frm<0b0101110, FPR16, FPR16, "fsqrt.h">, - Sched<[]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; +defm FSQRT_H : FPUnaryH_mc<0b0101110, FPR16, FPR16, "fsqrt.h", 0b00000>, + Sched<[]>; def FSGNJ_H : FPALUH_rr<0b0010010, 0b000, "fsgnj.h">, Sched<[]>; @@ -114,35 +120,16 @@ def FMAX_H : FPALUH_rr<0b0010110, 0b001, "fmax.h">, Sched<[]>; -def FCVT_W_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.w.h">, - Sched<[]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_WU_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.wu.h">, - Sched<[]> { - let rs2 = 0b00001; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_H_W : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.w">, - Sched<[]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_H_WU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.wu">, - Sched<[]> { - let rs2 = 0b00001; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_H_S : FPUnaryOp_r_frm<0b0100010, FPR16, FPR32, "fcvt.h.s">, - Sched<[]> { - let rs2 = 0b00000; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_W_H : FPUnaryH_mc<0b1100010, GPR, FPR16, "fcvt.w.h", 0b00000>, + Sched<[]>; +defm FCVT_WU_H : FPUnaryH_mc<0b1100010, GPR, FPR16, "fcvt.wu.h", 0b00001>, + Sched<[]>; +defm FCVT_H_W : FPUnaryH_mc<0b1101010, FPR16, GPR, "fcvt.h.w", 0b00000>, + Sched<[]>; +defm FCVT_H_WU : FPUnaryH_mc<0b1101010, FPR16, GPR, "fcvt.h.wu", 0b00001>, + Sched<[]>; +defm FCVT_H_S : FPUnaryH_mc<0b0100010, FPR16, FPR32, "fcvt.h.s", 0b00000>, + Sched<[]>; def FCVT_S_H : FPUnaryOp_r<0b0100000, 0b000, FPR32, FPR16, "fcvt.s.h">, Sched<[]> { @@ -170,37 +157,19 @@ } // Predicates = [HasStdExtZfh] let Predicates = [HasStdExtZfh, IsRV64] in { -def FCVT_L_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.l.h">, - Sched<[]> { - let rs2 = 0b00010; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_LU_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.lu.h">, - Sched<[]> { - let rs2 = 0b00011; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_H_L : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.l">, - Sched<[]> { - let rs2 = 0b00010; -} -def : FPUnaryOpDynFrmAlias; - -def FCVT_H_LU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.lu">, - Sched<[]> { - let rs2 = 0b00011; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_L_H : FPUnaryH_mc<0b1100010, GPR, FPR16, "fcvt.l.h", 0b00010>, + Sched<[]>; +defm FCVT_LU_H : FPUnaryH_mc<0b1100010, GPR, FPR16, "fcvt.lu.h", 0b00011>, + Sched<[]>; +defm FCVT_H_L : FPUnaryH_mc<0b1101010, FPR16, GPR, "fcvt.h.l", 0b00010>, + Sched<[]>; +defm FCVT_H_LU : FPUnaryH_mc<0b1101010, FPR16, GPR, "fcvt.h.lu", 0b00011>, + Sched<[]>; } // Predicates = [HasStdExtZfh, IsRV64] let Predicates = [HasStdExtZfh, HasStdExtD] in { -def FCVT_H_D : FPUnaryOp_r_frm<0b0100010, FPR16, FPR64, "fcvt.h.d">, - Sched<[]> { - let rs2 = 0b00001; -} -def : FPUnaryOpDynFrmAlias; +defm FCVT_H_D : FPUnaryH_mc<0b0100010, FPR16, FPR64, "fcvt.h.d", 0b00001>, + Sched<[]>; def FCVT_D_H : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR16, "fcvt.d.h">, Sched<[]> { @@ -256,7 +225,7 @@ def : Pat<(fmul FPR16:$rs1, FPR16:$rs2), (FMUL_H_def $rs1, $rs2)>; def : Pat<(fdiv FPR16:$rs1, FPR16:$rs2), (FDIV_H_def $rs1, $rs2)>; -def : Pat<(fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>; +def : Pat<(fsqrt FPR16:$rs1), (FSQRT_H_def FPR16:$rs1)>; def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>; def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>; @@ -264,9 +233,9 @@ def : PatFpr16Fpr16; def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>; def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2), - (FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>; + (FSGNJ_H $rs1, (FCVT_H_S_def $rs2))>; def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2), - (FSGNJ_H $rs1, (FCVT_H_D $rs2, 0b111))>; + (FSGNJ_H $rs1, (FCVT_H_D_def $rs2))>; def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>; def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>; @@ -311,7 +280,7 @@ /// Float conversion operations // f32 -> f16, f16 -> f32 -def : Pat<(fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, 0b111)>; +def : Pat<(fpround FPR32:$rs1), (FCVT_H_S_def FPR32:$rs1)>; def : Pat<(fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>; // Moves (no conversion) @@ -321,12 +290,12 @@ let Predicates = [HasStdExtZfh, IsRV32] in { // float->[u]int. Round-to-zero must be used. -def : Pat<(i32 (fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>; -def : Pat<(i32 (fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>; +def : Pat<(i32 (fp_to_sint FPR16:$rs1)), (FCVT_W_H_gen $rs1, 0b001)>; +def : Pat<(i32 (fp_to_uint FPR16:$rs1)), (FCVT_WU_H_gen $rs1, 0b001)>; // [u]int->float. Match GCC and default to using dynamic rounding mode. -def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>; -def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>; +def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W_def $rs1)>; +def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU_def $rs1)>; } // Predicates = [HasStdExtZfh, IsRV32] let Predicates = [HasStdExtZfh, IsRV64] in { @@ -335,22 +304,22 @@ // We match the single case below because fcvt.wu.s sign-extends its result so // is cheaper than fcvt.lu.h+sext.w. def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR16:$rs1)), i32), - (FCVT_WU_H $rs1, 0b001)>; + (FCVT_WU_H_gen $rs1, 0b001)>; // FP->[u]int64 -def : Pat<(i64 (fp_to_sint FPR16:$rs1)), (FCVT_L_H $rs1, 0b001)>; -def : Pat<(i64 (fp_to_uint FPR16:$rs1)), (FCVT_LU_H $rs1, 0b001)>; - -// [u]int->fp. Match GCC and default to using dynamic rounding mode. -def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W $rs1, 0b111)>; -def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, 0b111)>; -def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, 0b111)>; -def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, 0b111)>; +def : Pat<(i64 (fp_to_sint FPR16:$rs1)), (FCVT_L_H_gen $rs1, 0b001)>; +def : Pat<(i64 (fp_to_uint FPR16:$rs1)), (FCVT_LU_H_gen $rs1, 0b001)>; + +// [u]int->fp. +def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W_def $rs1)>; +def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU_def $rs1)>; +def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L_def $rs1)>; +def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU_def $rs1)>; } // Predicates = [HasStdExtZfh, IsRV64] let Predicates = [HasStdExtZfh, HasStdExtD] in { /// Float conversion operations // f64 -> f16, f16 -> f64 -def : Pat<(fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>; +def : Pat<(fpround FPR64:$rs1), (FCVT_H_D_def FPR64:$rs1)>; def : Pat<(fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>; } diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll --- a/llvm/test/CodeGen/RISCV/double-arith.ll +++ b/llvm/test/CodeGen/RISCV/double-arith.ll @@ -129,7 +129,7 @@ ; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: fld ft0, 8(sp) -; RV32IFD-NEXT: fsqrt.d ft0, ft0 +; RV32IFD-NEXT: fsqrt.d ft0, ft0, rne ; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a1, 12(sp) @@ -139,7 +139,7 @@ ; RV64IFD-LABEL: fsqrt_d: ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d.x ft0, a0 -; RV64IFD-NEXT: fsqrt.d ft0, ft0 +; RV64IFD-NEXT: fsqrt.d ft0, ft0, rne ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ret %1 = call double @llvm.sqrt.f64(double %a) diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -11,7 +11,7 @@ ; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: fld ft0, 8(sp) -; RV32IFD-NEXT: fcvt.s.d ft0, ft0 +; RV32IFD-NEXT: fcvt.s.d ft0, ft0, rne ; RV32IFD-NEXT: fmv.x.w a0, ft0 ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -19,7 +19,7 @@ ; RV64IFD-LABEL: fcvt_s_d: ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d.x ft0, a0 -; RV64IFD-NEXT: fcvt.s.d ft0, ft0 +; RV64IFD-NEXT: fcvt.s.d ft0, ft0, rne ; RV64IFD-NEXT: fmv.x.w a0, ft0 ; RV64IFD-NEXT: ret %1 = fptrunc double %a to float @@ -180,7 +180,7 @@ ; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: fld ft1, 0(sp) -; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 +; RV32IFD-NEXT: fadd.d ft0, ft1, ft0, rne ; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a1, 12(sp) @@ -191,7 +191,7 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a0 -; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 +; RV64IFD-NEXT: fadd.d ft0, ft1, ft0, rne ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ret %1 = fadd double %a, %b @@ -211,7 +211,7 @@ ; ; RV64IFD-LABEL: fcvt_d_l: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: fcvt.d.l ft0, a0 +; RV64IFD-NEXT: fcvt.d.l ft0, a0, rne ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ret %1 = sitofp i64 %a to double @@ -230,7 +230,7 @@ ; ; RV64IFD-LABEL: fcvt_d_lu: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: fcvt.d.lu ft0, a0 +; RV64IFD-NEXT: fcvt.d.lu ft0, a0, rne ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ret %1 = uitofp i64 %a to double @@ -248,7 +248,7 @@ ; RV32IFD-NEXT: sw a0, 24(sp) ; RV32IFD-NEXT: fld ft0, 16(sp) ; RV32IFD-NEXT: fld ft1, 24(sp) -; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 +; RV32IFD-NEXT: fadd.d ft0, ft1, ft0, rne ; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a1, 12(sp) @@ -259,7 +259,7 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a1 -; RV64IFD-NEXT: fadd.d ft0, ft0, ft1 +; RV64IFD-NEXT: fadd.d ft0, ft0, ft1, rne ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ret %1 = bitcast i64 %a to double diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -94,14 +94,14 @@ ; RV32IF-LABEL: fsqrt_s: ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.w.x ft0, a0 -; RV32IF-NEXT: fsqrt.s ft0, ft0 +; RV32IF-NEXT: fsqrt.s ft0, ft0, rne ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fsqrt_s: ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.w.x ft0, a0 -; RV64IF-NEXT: fsqrt.s ft0, ft0 +; RV64IF-NEXT: fsqrt.s ft0, ft0, rne ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = call float @llvm.sqrt.f32(float %a) diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -45,7 +45,7 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft1, a0 -; RV32IF-NEXT: fadd.s ft0, ft1, ft0 +; RV32IF-NEXT: fadd.s ft0, ft1, ft0, rne ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; @@ -53,7 +53,7 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft1, a0 -; RV64IF-NEXT: fadd.s ft0, ft1, ft0 +; RV64IF-NEXT: fadd.s ft0, ft1, ft0, rne ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret ; Ensure fmv.x.w is generated even for a soft float calling convention @@ -65,13 +65,13 @@ define float @fcvt_s_w(i32 %a) nounwind { ; RV32IF-LABEL: fcvt_s_w: ; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.w ft0, a0 +; RV32IF-NEXT: fcvt.s.w ft0, a0, rne ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fcvt_s_w: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.w ft0, a0 +; RV64IF-NEXT: fcvt.s.w ft0, a0, rne ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = sitofp i32 %a to float @@ -81,13 +81,13 @@ define float @fcvt_s_wu(i32 %a) nounwind { ; RV32IF-LABEL: fcvt_s_wu: ; RV32IF: # %bb.0: -; RV32IF-NEXT: fcvt.s.wu ft0, a0 +; RV32IF-NEXT: fcvt.s.wu ft0, a0, rne ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; ; RV64IF-LABEL: fcvt_s_wu: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.wu ft0, a0 +; RV64IF-NEXT: fcvt.s.wu ft0, a0, rne ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = uitofp i32 %a to float @@ -99,7 +99,7 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft1, a1 -; RV32IF-NEXT: fadd.s ft0, ft0, ft1 +; RV32IF-NEXT: fadd.s ft0, ft0, ft1, rne ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; @@ -107,7 +107,7 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft1, a1 -; RV64IF-NEXT: fadd.s ft0, ft0, ft1 +; RV64IF-NEXT: fadd.s ft0, ft0, ft1, rne ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret ; Ensure fmv.w.x is generated even for a soft float calling convention @@ -167,7 +167,7 @@ ; ; RV64IF-LABEL: fcvt_s_l: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.l ft0, a0 +; RV64IF-NEXT: fcvt.s.l ft0, a0, rne ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = sitofp i64 %a to float @@ -186,7 +186,7 @@ ; ; RV64IF-LABEL: fcvt_s_lu: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.lu ft0, a0 +; RV64IF-NEXT: fcvt.s.lu ft0, a0, rne ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = uitofp i64 %a to float diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll --- a/llvm/test/CodeGen/RISCV/half-arith.ll +++ b/llvm/test/CodeGen/RISCV/half-arith.ll @@ -71,12 +71,12 @@ define half @fsqrt_s(half %a) nounwind { ; RV32IZFH-LABEL: fsqrt_s: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fsqrt.h fa0, fa0 +; RV32IZFH-NEXT: fsqrt.h fa0, fa0, rne ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: fsqrt_s: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fsqrt.h fa0, fa0 +; RV64IZFH-NEXT: fsqrt.h fa0, fa0, rne ; RV64IZFH-NEXT: ret %1 = call half @llvm.sqrt.f16(half %a) ret half %1 diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -173,28 +173,28 @@ ; RV32IZFH: # %bb.0: ; RV32IZFH-NEXT: slli a0, a0, 16 ; RV32IZFH-NEXT: srai a0, a0, 16 -; RV32IZFH-NEXT: fcvt.h.w fa0, a0 +; RV32IZFH-NEXT: fcvt.h.w fa0, a0, rne ; RV32IZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_h_si: ; RV32IDZFH: # %bb.0: ; RV32IDZFH-NEXT: slli a0, a0, 16 ; RV32IDZFH-NEXT: srai a0, a0, 16 -; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 +; RV32IDZFH-NEXT: fcvt.h.w fa0, a0, rne ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_h_si: ; RV64IZFH: # %bb.0: ; RV64IZFH-NEXT: slli a0, a0, 48 ; RV64IZFH-NEXT: srai a0, a0, 48 -; RV64IZFH-NEXT: fcvt.h.l fa0, a0 +; RV64IZFH-NEXT: fcvt.h.l fa0, a0, rne ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_si: ; RV64IDZFH: # %bb.0: ; RV64IDZFH-NEXT: slli a0, a0, 48 ; RV64IDZFH-NEXT: srai a0, a0, 48 -; RV64IDZFH-NEXT: fcvt.h.l fa0, a0 +; RV64IDZFH-NEXT: fcvt.h.l fa0, a0, rne ; RV64IDZFH-NEXT: ret %1 = sitofp i16 %a to half ret half %1 @@ -230,7 +230,7 @@ ; RV32IZFH-NEXT: lui a1, 16 ; RV32IZFH-NEXT: addi a1, a1, -1 ; RV32IZFH-NEXT: and a0, a0, a1 -; RV32IZFH-NEXT: fcvt.h.wu fa0, a0 +; RV32IZFH-NEXT: fcvt.h.wu fa0, a0, rne ; RV32IZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_h_ui: @@ -238,7 +238,7 @@ ; RV32IDZFH-NEXT: lui a1, 16 ; RV32IDZFH-NEXT: addi a1, a1, -1 ; RV32IDZFH-NEXT: and a0, a0, a1 -; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 +; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0, rne ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_h_ui: @@ -246,7 +246,7 @@ ; RV64IZFH-NEXT: lui a1, 16 ; RV64IZFH-NEXT: addiw a1, a1, -1 ; RV64IZFH-NEXT: and a0, a0, a1 -; RV64IZFH-NEXT: fcvt.h.lu fa0, a0 +; RV64IZFH-NEXT: fcvt.h.lu fa0, a0, rne ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_ui: @@ -254,7 +254,7 @@ ; RV64IDZFH-NEXT: lui a1, 16 ; RV64IDZFH-NEXT: addiw a1, a1, -1 ; RV64IDZFH-NEXT: and a0, a0, a1 -; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0 +; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0, rne ; RV64IDZFH-NEXT: ret %1 = uitofp i16 %a to half ret half %1 @@ -287,22 +287,22 @@ define half @fcvt_h_w(i32 %a) nounwind { ; RV32IZFH-LABEL: fcvt_h_w: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fcvt.h.w fa0, a0 +; RV32IZFH-NEXT: fcvt.h.w fa0, a0, rne ; RV32IZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_h_w: ; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 +; RV32IDZFH-NEXT: fcvt.h.w fa0, a0, rne ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_h_w: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.h.w fa0, a0 +; RV64IZFH-NEXT: fcvt.h.w fa0, a0, rne ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_w: ; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.w fa0, a0 +; RV64IDZFH-NEXT: fcvt.h.w fa0, a0, rne ; RV64IDZFH-NEXT: ret %1 = sitofp i32 %a to half ret half %1 @@ -311,22 +311,22 @@ define half @fcvt_h_wu(i32 %a) nounwind { ; RV32IZFH-LABEL: fcvt_h_wu: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fcvt.h.wu fa0, a0 +; RV32IZFH-NEXT: fcvt.h.wu fa0, a0, rne ; RV32IZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_h_wu: ; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 +; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0, rne ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_h_wu: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.h.wu fa0, a0 +; RV64IZFH-NEXT: fcvt.h.wu fa0, a0, rne ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_wu: ; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0 +; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0, rne ; RV64IDZFH-NEXT: ret %1 = uitofp i32 %a to half ret half %1 @@ -353,12 +353,12 @@ ; ; RV64IZFH-LABEL: fcvt_h_l: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.h.l fa0, a0 +; RV64IZFH-NEXT: fcvt.h.l fa0, a0, rne ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_l: ; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.l fa0, a0 +; RV64IDZFH-NEXT: fcvt.h.l fa0, a0, rne ; RV64IDZFH-NEXT: ret %1 = sitofp i64 %a to half ret half %1 @@ -385,12 +385,12 @@ ; ; RV64IZFH-LABEL: fcvt_h_lu: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.h.lu fa0, a0 +; RV64IZFH-NEXT: fcvt.h.lu fa0, a0, rne ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_lu: ; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0 +; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0, rne ; RV64IDZFH-NEXT: ret %1 = uitofp i64 %a to half ret half %1 @@ -399,22 +399,22 @@ define half @fcvt_h_s(float %a) nounwind { ; RV32IZFH-LABEL: fcvt_h_s: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fcvt.h.s fa0, fa0 +; RV32IZFH-NEXT: fcvt.h.s fa0, fa0, rne ; RV32IZFH-NEXT: ret ; ; RV32IDZFH-LABEL: fcvt_h_s: ; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0 +; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0, rne ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_h_s: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.h.s fa0, fa0 +; RV64IZFH-NEXT: fcvt.h.s fa0, fa0, rne ; RV64IZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_h_s: ; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0 +; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0, rne ; RV64IDZFH-NEXT: ret %1 = fptrunc float %a to half ret half %1 @@ -456,7 +456,7 @@ ; ; RV32IDZFH-LABEL: fcvt_h_d: ; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0 +; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0, rne ; RV32IDZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_h_d: @@ -470,7 +470,7 @@ ; ; RV64IDZFH-LABEL: fcvt_h_d: ; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0 +; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0, rne ; RV64IDZFH-NEXT: ret %1 = fptrunc double %a to half ret half %1