diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -37,22 +37,20 @@
                         FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
 }
 
+multiclass FPALUD_mc<bits<7> funct7, string OpcodeStr> {
+  def _gen : FPALU_gen<funct7, OpcodeStr, FPR64>;
+  def _def : FPALU_def<funct7, OpcodeStr, FPR64>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                       (!cast<Instruction>(NAME # "_gen")
+                        FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
               (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPALUD_rr_frm<bits<7> funct7, string opcodestr>
-    : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd),
-                (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr,
-                 "$rd, $rs1, $rs2, $funct3">;
-
-class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr>
-    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
-                (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPCmpD_rr<bits<3> funct3, string opcodestr>
     : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
               (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">,
@@ -88,18 +86,14 @@
 defm FNMADD_D : FPFMAD_mc<OPC_NMADD, "fnmadd.d">,
                 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
 
-def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">,
-             Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def        : FPALUDDynFrmAlias<FADD_D, "fadd.d">;
-def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">,
-             Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def        : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
-def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">,
-             Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
-def        : FPALUDDynFrmAlias<FMUL_D, "fmul.d">;
-def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">,
-             Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
-def        : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">;
+defm FADD_D : FPALUD_mc<0b0000001, "fadd.d">,
+              Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+defm FSUB_D : FPALUD_mc<0b0000101, "fsub.d">,
+              Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+defm FMUL_D : FPALUD_mc<0b0001001, "fmul.d">,
+              Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
+defm FDIV_D : FPALUD_mc<0b0001101, "fdiv.d">,
+              Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
 
 def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">,
               Sched<[WriteFSqrt64, ReadFSqrt64]> {
@@ -227,9 +221,6 @@
 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
 
-class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
-    : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;
-
 let Predicates = [HasStdExtD] in {
 
 /// Float conversion operations
@@ -243,10 +234,10 @@
 
 /// Float arithmetic operations
 
-def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
-def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
-def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
-def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
+def : Pat<(fadd FPR64:$rs1, FPR64:$rs2), (FADD_D_def $rs1, $rs2)>;
+def : Pat<(fsub FPR64:$rs1, FPR64:$rs2), (FSUB_D_def $rs1, $rs2)>;
+def : Pat<(fmul FPR64:$rs1, FPR64:$rs2), (FMUL_D_def $rs1, $rs2)>;
+def : Pat<(fdiv FPR64:$rs1, FPR64:$rs2), (FDIV_D_def $rs1, $rs2)>;
 
 def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -78,15 +78,30 @@
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd),
               (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPALUS_rr_frm<bits<7> funct7, string opcodestr>
-    : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd),
-                 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr,
-                  "$rd, $rs1, $rs2, $funct3">;
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  class FPALU_gen<bits<7> funct7, string opcodestr, RegisterClass rty>
+      : RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
+                   (ins rty:$rs1, rty:$rs2, frmarg:$funct3), opcodestr,
+                   "$rd, $rs1, $rs2, $funct3"> {
+    let Defs = [FFLAGSReg];
+    let Uses = [FRMReg];
+  }
+
+  class FPALU_def<bits<7> funct7, string opcodestr, RegisterClass rty>
+      : RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
+                   (ins rty:$rs1, rty:$rs2), opcodestr,
+                   "$rd, $rs1, $rs2, rne"> {
+    let funct3 = 0b000;
+  }
+}
 
-class FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr>
-    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
-                (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>;
+multiclass FPALUS_mc<bits<7> funct7, string OpcodeStr> {
+  def _gen : FPALU_gen<funct7, OpcodeStr, FPR32>;
+  def _def : FPALU_def<funct7, OpcodeStr, FPR32>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                       (!cast<Instruction>(NAME # "_gen")
+                        FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>;
+}
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
@@ -141,18 +156,14 @@
 defm FNMADD_S : FPFMAS_mc<OPC_NMADD, "fnmadd.s">,
                 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
 
-def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">,
-             Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
-def        : FPALUSDynFrmAlias<FADD_S, "fadd.s">;
-def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">,
-             Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
-def        : FPALUSDynFrmAlias<FSUB_S, "fsub.s">;
-def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">,
-             Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
-def        : FPALUSDynFrmAlias<FMUL_S, "fmul.s">;
-def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">,
-             Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
-def        : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">;
+defm FADD_S : FPALUS_mc<0b0000000, "fadd.s">,
+              Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
+defm FSUB_S : FPALUS_mc<0b0000100, "fsub.s">,
+              Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
+defm FMUL_S : FPALUS_mc<0b0001000, "fmul.s">,
+              Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
+defm FDIV_S : FPALUS_mc<0b0001100, "fdiv.s">,
+              Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
 
 def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">,
               Sched<[WriteFSqrt32, ReadFSqrt32]> {
@@ -305,9 +316,6 @@
 class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>;
 
-class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
-    : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>;
-
 let Predicates = [HasStdExtF] in {
 
 /// Float constants
@@ -320,10 +328,10 @@
 
 /// Float arithmetic operations
 
-def : PatFpr32Fpr32DynFrm<fadd, FADD_S>;
-def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
-def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
-def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
+def : Pat<(fadd FPR32:$rs1, FPR32:$rs2), (FADD_S_def $rs1, $rs2)>;
+def : Pat<(fsub FPR32:$rs1, FPR32:$rs2), (FSUB_S_def $rs1, $rs2)>;
+def : Pat<(fmul FPR32:$rs1, FPR32:$rs2), (FMUL_S_def $rs1, $rs2)>;
+def : Pat<(fdiv FPR32:$rs1, FPR32:$rs2), (FDIV_S_def $rs1, $rs2)>;
 
 def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -39,22 +39,20 @@
                         FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
 }
 
+multiclass FPALUH_mc<bits<7> funct7, string OpcodeStr> {
+  def _gen : FPALU_gen<funct7, OpcodeStr, FPR16>;
+  def _def : FPALU_def<funct7, OpcodeStr, FPR16>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                       (!cast<Instruction>(NAME # "_gen")
+                        FPR16:$rd, FPR16:$rs1, FPR16:$rs2, 0b111)>;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPALUH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16:$rd),
               (ins FPR16:$rs1, FPR16:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPALUH_rr_frm<bits<7> funct7, string opcodestr>
-    : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR16:$rd),
-                 (ins FPR16:$rs1, FPR16:$rs2, frmarg:$funct3), opcodestr,
-                  "$rd, $rs1, $rs2, $funct3">;
-
-class FPALUHDynFrmAlias<FPALUH_rr_frm Inst, string OpcodeStr>
-    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
-                (Inst FPR16:$rd, FPR16:$rs1, FPR16:$rs2, 0b111)>;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPCmpH_rr<bits<3> funct3, string opcodestr>
     : RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPR:$rd),
               (ins FPR16:$rs1, FPR16:$rs2), opcodestr, "$rd, $rs1, $rs2">,
@@ -89,18 +87,14 @@
 defm FNMADD_H : FPFMAH_mc<OPC_NMADD, "fnmadd.h">,
                 Sched<[]>;
 
-def FADD_H : FPALUH_rr_frm<0b0000010, "fadd.h">,
-             Sched<[]>;
-def        : FPALUHDynFrmAlias<FADD_H, "fadd.h">;
-def FSUB_H : FPALUH_rr_frm<0b0000110, "fsub.h">,
-             Sched<[]>;
-def        : FPALUHDynFrmAlias<FSUB_H, "fsub.h">;
-def FMUL_H : FPALUH_rr_frm<0b0001010, "fmul.h">,
-             Sched<[]>;
-def        : FPALUHDynFrmAlias<FMUL_H, "fmul.h">;
-def FDIV_H : FPALUH_rr_frm<0b0001110, "fdiv.h">,
-             Sched<[]>;
-def        : FPALUHDynFrmAlias<FDIV_H, "fdiv.h">;
+defm FADD_H : FPALUH_mc<0b0000010, "fadd.h">,
+              Sched<[]>;
+defm FSUB_H : FPALUH_mc<0b0000110, "fsub.h">,
+              Sched<[]>;
+defm FMUL_H : FPALUH_mc<0b0001010, "fmul.h">,
+              Sched<[]>;
+defm FDIV_H : FPALUH_mc<0b0001110, "fdiv.h">,
+              Sched<[]>;
 
 def FSQRT_H : FPUnaryOp_r_frm<0b0101110, FPR16, FPR16, "fsqrt.h">,
               Sched<[]> {
@@ -245,9 +239,6 @@
 class PatFpr16Fpr16<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2)>;
 
-class PatFpr16Fpr16DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
-    : Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2, 0b111)>;
-
 let Predicates = [HasStdExtZfh] in {
 
 /// Float constants
@@ -260,10 +251,10 @@
 
 /// Float arithmetic operations
 
-def : PatFpr16Fpr16DynFrm<fadd, FADD_H>;
-def : PatFpr16Fpr16DynFrm<fsub, FSUB_H>;
-def : PatFpr16Fpr16DynFrm<fmul, FMUL_H>;
-def : PatFpr16Fpr16DynFrm<fdiv, FDIV_H>;
+def : Pat<(fadd FPR16:$rs1, FPR16:$rs2), (FADD_H_def $rs1, $rs2)>;
+def : Pat<(fsub FPR16:$rs1, FPR16:$rs2), (FSUB_H_def $rs1, $rs2)>;
+def : Pat<(fmul FPR16:$rs1, FPR16:$rs2), (FMUL_H_def $rs1, $rs2)>;
+def : Pat<(fdiv FPR16:$rs1, FPR16:$rs2), (FDIV_H_def $rs1, $rs2)>;
 
 def : Pat<(fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>;
 
diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll
--- a/llvm/test/CodeGen/RISCV/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith.ll
@@ -18,7 +18,7 @@
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
@@ -29,7 +29,7 @@
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fadd double %a, %b
@@ -46,7 +46,7 @@
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fsub.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fsub.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
@@ -57,7 +57,7 @@
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fsub.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fsub.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fsub double %a, %b
@@ -74,7 +74,7 @@
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fmul.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fmul.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
@@ -85,7 +85,7 @@
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fmul.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fmul.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fmul double %a, %b
@@ -102,7 +102,7 @@
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fdiv.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fdiv.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
@@ -113,7 +113,7 @@
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fdiv.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fdiv.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fdiv double %a, %b
@@ -185,7 +185,7 @@
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
-; RV32IFD-NEXT:    fadd.d ft0, ft0, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft0, ft0, rne
 ; RV32IFD-NEXT:    fneg.d ft1, ft0
 ; RV32IFD-NEXT:    feq.d a0, ft0, ft1
 ; RV32IFD-NEXT:    addi sp, sp, 16
@@ -194,7 +194,7 @@
 ; RV64IFD-LABEL: fneg_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
-; RV64IFD-NEXT:    fadd.d ft0, ft0, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft0, ft0, rne
 ; RV64IFD-NEXT:    fneg.d ft1, ft0
 ; RV64IFD-NEXT:    feq.d a0, ft0, ft1
 ; RV64IFD-NEXT:    ret
@@ -254,9 +254,9 @@
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fabs.d ft1, ft0
-; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
@@ -267,9 +267,9 @@
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fabs.d ft1, ft0
-; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fadd double %a, %b
@@ -461,7 +461,7 @@
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV32IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -475,7 +475,7 @@
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a2
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV64IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
@@ -499,8 +499,8 @@
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV32IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -514,8 +514,8 @@
 ; RV64IFD-NEXT:    fmv.d.x ft1, a2
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
@@ -541,8 +541,8 @@
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV32IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -556,8 +556,8 @@
 ; RV64IFD-NEXT:    fmv.d.x ft1, a2
 ; RV64IFD-NEXT:    fmv.d.x ft2, a1
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
@@ -583,7 +583,7 @@
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV32IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -597,7 +597,7 @@
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
@@ -621,7 +621,7 @@
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV32IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -635,7 +635,7 @@
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a1
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
@@ -692,7 +692,7 @@
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV32IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -706,7 +706,7 @@
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a2
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV64IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
@@ -730,9 +730,9 @@
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
-; RV32IFD-NEXT:    fadd.d ft0, ft0, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft0, ft0, ft3, rne
 ; RV32IFD-NEXT:    fnmadd.d ft0, ft2, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -746,9 +746,9 @@
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
-; RV64IFD-NEXT:    fadd.d ft0, ft0, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft0, ft0, ft3, rne
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
@@ -775,8 +775,8 @@
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV32IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -790,8 +790,8 @@
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll
--- a/llvm/test/CodeGen/RISCV/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith.ll
@@ -13,7 +13,7 @@
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
@@ -21,7 +21,7 @@
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, %b
@@ -33,7 +33,7 @@
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fsub.s ft0, ft1, ft0
+; RV32IF-NEXT:    fsub.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
@@ -41,7 +41,7 @@
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fsub.s ft0, ft1, ft0
+; RV64IF-NEXT:    fsub.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fsub float %a, %b
@@ -53,7 +53,7 @@
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fmul.s ft0, ft1, ft0
+; RV32IF-NEXT:    fmul.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
@@ -61,7 +61,7 @@
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fmul.s ft0, ft1, ft0
+; RV64IF-NEXT:    fmul.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fmul float %a, %b
@@ -73,7 +73,7 @@
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fdiv.s ft0, ft1, ft0
+; RV32IF-NEXT:    fdiv.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
@@ -81,7 +81,7 @@
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fdiv.s ft0, ft1, ft0
+; RV64IF-NEXT:    fdiv.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fdiv float %a, %b
@@ -136,7 +136,7 @@
 ; RV32IF-LABEL: fneg_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    fadd.s ft0, ft0, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft0, ft0, rne
 ; RV32IF-NEXT:    fneg.s ft1, ft0
 ; RV32IF-NEXT:    feq.s a0, ft0, ft1
 ; RV32IF-NEXT:    ret
@@ -144,7 +144,7 @@
 ; RV64IF-LABEL: fneg_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
-; RV64IF-NEXT:    fadd.s ft0, ft0, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft0, ft0, rne
 ; RV64IF-NEXT:    fneg.s ft1, ft0
 ; RV64IF-NEXT:    feq.s a0, ft0, ft1
 ; RV64IF-NEXT:    ret
@@ -162,7 +162,7 @@
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fsgnjn.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -171,7 +171,7 @@
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fsgnjn.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
@@ -190,9 +190,9 @@
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fabs.s ft1, ft0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
@@ -200,9 +200,9 @@
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fabs.s ft1, ft0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, %b
@@ -343,7 +343,7 @@
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fmv.w.x ft2, a2
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV32IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -354,7 +354,7 @@
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a2
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV64IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
@@ -371,8 +371,8 @@
 ; RV32IF-NEXT:    fmv.w.x ft1, a2
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV32IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -383,8 +383,8 @@
 ; RV64IF-NEXT:    fmv.w.x ft1, a2
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
@@ -403,8 +403,8 @@
 ; RV32IF-NEXT:    fmv.w.x ft1, a2
 ; RV32IF-NEXT:    fmv.w.x ft2, a1
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV32IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -415,8 +415,8 @@
 ; RV64IF-NEXT:    fmv.w.x ft1, a2
 ; RV64IF-NEXT:    fmv.w.x ft2, a1
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
@@ -435,7 +435,7 @@
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV32IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -446,7 +446,7 @@
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
@@ -463,7 +463,7 @@
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fmv.w.x ft2, a1
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV32IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -474,7 +474,7 @@
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a1
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
@@ -514,7 +514,7 @@
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fmv.w.x ft2, a2
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV32IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -525,7 +525,7 @@
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a2
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV64IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
@@ -542,9 +542,9 @@
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
-; RV32IF-NEXT:    fadd.s ft0, ft0, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3, rne
+; RV32IF-NEXT:    fadd.s ft0, ft0, ft3, rne
 ; RV32IF-NEXT:    fnmadd.s ft0, ft2, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -555,9 +555,9 @@
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
-; RV64IF-NEXT:    fadd.s ft0, ft0, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3, rne
+; RV64IF-NEXT:    fadd.s ft0, ft0, ft3, rne
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
@@ -577,8 +577,8 @@
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV32IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
@@ -589,8 +589,8 @@
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -13,12 +13,12 @@
 define half @fadd_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fadd_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h fa0, fa0, fa1
+; RV32IZFH-NEXT:    fadd.h fa0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fadd_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa1
+; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fadd half %a, %b
   ret half %1
@@ -27,12 +27,12 @@
 define half @fsub_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fsub_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsub.h fa0, fa0, fa1
+; RV32IZFH-NEXT:    fsub.h fa0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fsub_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsub.h fa0, fa0, fa1
+; RV64IZFH-NEXT:    fsub.h fa0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fsub half %a, %b
   ret half %1
@@ -41,12 +41,12 @@
 define half @fmul_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fmul_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmul.h fa0, fa0, fa1
+; RV32IZFH-NEXT:    fmul.h fa0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fmul_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmul.h fa0, fa0, fa1
+; RV64IZFH-NEXT:    fmul.h fa0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fmul half %a, %b
   ret half %1
@@ -55,12 +55,12 @@
 define half @fdiv_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fdiv_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fdiv.h fa0, fa0, fa1
+; RV32IZFH-NEXT:    fdiv.h fa0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fdiv_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fdiv.h fa0, fa0, fa1
+; RV64IZFH-NEXT:    fdiv.h fa0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fdiv half %a, %b
   ret half %1
@@ -103,14 +103,14 @@
 define i32 @fneg_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fneg_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa0
+; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa0, rne
 ; RV32IZFH-NEXT:    fneg.h ft1, ft0
 ; RV32IZFH-NEXT:    feq.h a0, ft0, ft1
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fneg_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa0
+; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa0, rne
 ; RV64IZFH-NEXT:    fneg.h ft1, ft0
 ; RV64IZFH-NEXT:    feq.h a0, ft0, ft1
 ; RV64IZFH-NEXT:    ret
@@ -126,13 +126,13 @@
 define half @fsgnjn_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fsgnjn_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1
+; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    fsgnjn.h fa0, fa0, ft0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fsgnjn_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
+; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    fsgnjn.h fa0, fa0, ft0
 ; RV64IZFH-NEXT:    ret
   %1 = fadd half %a, %b
@@ -148,16 +148,16 @@
 define half @fabs_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fabs_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1
+; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    fabs.h ft1, ft0
-; RV32IZFH-NEXT:    fadd.h fa0, ft1, ft0
+; RV32IZFH-NEXT:    fadd.h fa0, ft1, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fabs_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
+; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    fabs.h ft1, ft0
-; RV64IZFH-NEXT:    fadd.h fa0, ft1, ft0
+; RV64IZFH-NEXT:    fadd.h fa0, ft1, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = call half @llvm.fabs.f16(half %1)
@@ -262,14 +262,14 @@
 ; RV32IZFH-LABEL: fmsub_s:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fmsub_s:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
@@ -282,16 +282,16 @@
 ; RV32IZFH-LABEL: fnmadd_s:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmadd_s:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %a_ = fadd half 0.0, %a
@@ -306,16 +306,16 @@
 ; RV32IZFH-LABEL: fnmadd_s_2:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa1, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft1, fa1, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmadd_s_2:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa1, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft1, fa1, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %b_ = fadd half 0.0, %b
@@ -330,14 +330,14 @@
 ; RV32IZFH-LABEL: fnmsub_s:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, ft0
+; RV32IZFH-NEXT:    fadd.h ft0, fa0, ft0, rne
 ; RV32IZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmsub_s:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, ft0
+; RV64IZFH-NEXT:    fadd.h ft0, fa0, ft0, rne
 ; RV64IZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2, rne
 ; RV64IZFH-NEXT:    ret
   %a_ = fadd half 0.0, %a
@@ -350,14 +350,14 @@
 ; RV32IZFH-LABEL: fnmsub_s_2:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0
+; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0, rne
 ; RV32IZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmsub_s_2:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0
+; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0, rne
 ; RV64IZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2, rne
 ; RV64IZFH-NEXT:    ret
   %b_ = fadd half 0.0, %b
@@ -385,14 +385,14 @@
 ; RV32IZFH-LABEL: fmsub_s_contract:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fmsub_s_contract:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
@@ -405,18 +405,18 @@
 ; RV32IZFH-LABEL: fnmadd_s_contract:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft2, fa1, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft2, fa1, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, ft2, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmadd_s_contract:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft2, fa1, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft2, fa1, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, ft2, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %a_ = fadd half 0.0, %a ; avoid negation using xor
@@ -432,16 +432,16 @@
 ; RV32IZFH-LABEL: fnmsub_s_contract:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0
+; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0, rne
 ; RV32IZFH-NEXT:    fnmsub.h fa0, ft1, ft0, fa2, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmsub_s_contract:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0
+; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0, rne
 ; RV64IZFH-NEXT:    fnmsub.h fa0, ft1, ft0, fa2, rne
 ; RV64IZFH-NEXT:    ret
   %a_ = fadd half 0.0, %a ; avoid negation using xor