diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -358,8 +358,8 @@ /// described by \p Outs can fit into the return registers. If false /// is returned, an sret-demotion is performed. virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, - SmallVectorImpl &Outs, bool IsVarArg, - LLVMContext &Context) const { + SmallVectorImpl &Outs, + bool IsVarArg) const { return true; } diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -95,8 +95,7 @@ SmallVector SplitArgs; getReturnInfo(CallConv, RetTy, CB.getAttributes(), SplitArgs, DL); - Info.CanLowerReturn = - canLowerReturn(MF, CallConv, SplitArgs, IsVarArg, RetTy->getContext()); + Info.CanLowerReturn = canLowerReturn(MF, CallConv, SplitArgs, IsVarArg); if (!Info.CanLowerReturn) { // Callee requires sret demotion. @@ -592,8 +591,7 @@ SmallVector SplitArgs; getReturnInfo(CallConv, ReturnType, F.getAttributes(), SplitArgs, MF.getDataLayout()); - return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg(), - ReturnType->getContext()); + return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg()); } bool CallLowering::analyzeArgInfo(CCState &CCState, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h @@ -40,6 +40,10 @@ bool IsOutgoing, SplitArgTy SplitArg) const; + bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, + SmallVectorImpl &Outs, + bool IsVarArg) const override; + bool lowerReturnVal(MachineIRBuilder &B, const Value *Val, ArrayRef VRegs, MachineInstrBuilder &Ret) const; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -24,6 +24,7 @@ #include "SIRegisterInfo.h" #include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/FunctionLoweringInfo.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/LowLevelTypeImpl.h" @@ -413,6 +414,22 @@ B.buildUnmerge(UnmergeResults, UnmergeSrc); } +bool AMDGPUCallLowering::canLowerReturn(MachineFunction &MF, + CallingConv::ID CallConv, + SmallVectorImpl &Outs, + bool IsVarArg) const { + // For shaders. Vector types should be explicitly handled by CC. + if (AMDGPU::isEntryFunctionCC(CallConv)) + return true; + + SmallVector ArgLocs; + const SITargetLowering &TLI = *getTLI(); + CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, + MF.getFunction().getContext()); + + return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv, IsVarArg)); +} + /// Lower the return value for the already existing \p Ret. This assumes that /// \p B's insertion point is correct. bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B, @@ -480,7 +497,9 @@ Ret.addUse(ReturnAddrVReg); } - if (!lowerReturnVal(B, Val, VRegs, Ret)) + if (!FLI.CanLowerReturn) + insertSRetStores(B, Val->getType(), VRegs, FLI.DemoteRegister); + else if (!lowerReturnVal(B, Val, VRegs, Ret)) return false; if (ReturnOpc == AMDGPU::S_SETPC_B64_return) { @@ -814,11 +833,15 @@ CCInfo.AllocateReg(ImplicitBufferPtrReg); } - SmallVector SplitArgs; unsigned Idx = 0; unsigned PSInputNum = 0; + // Insert the hidden sret parameter if the return value won't fit in the + // return registers. + if (!FLI.CanLowerReturn) + insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL); + for (auto &Arg : F.args()) { if (DL.getTypeStoreSize(Arg.getType()) == 0) continue; @@ -1268,7 +1291,10 @@ MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN); SmallVector InArgs; - if (!Info.OrigRet.Ty->isVoidTy()) { + if (!Info.CanLowerReturn) { + insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs, + Info.DemoteRegister, Info.DemoteStackIndex); + } else if (!Info.OrigRet.Ty->isVoidTy()) { splitToValueTypes( MIRBuilder, Info.OrigRet, InArgs, DL, Info.CallConv, false, [&](ArrayRef Regs, Register DstReg, @@ -1286,7 +1312,7 @@ // Finally we can copy the returned value back into its virtual-register. In // symmetry with the arguments, the physical register must be an // implicit-define of the call instruction. - if (!Info.OrigRet.Ty->isVoidTy()) { + if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) { CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, Info.IsVarArg); CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll @@ -1172,34 +1172,63 @@ define <33 x i32> @v33i32_func_void() #0 { ; CHECK-LABEL: name: v33i32_func_void - ; CHECK: bb.0: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $sgpr30_sgpr31 - ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 - ; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 + ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 + ; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF ; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `<33 x i32> addrspace(1)* addrspace(4)* undef`, addrspace 4) ; CHECK: [[LOAD1:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[LOAD]](p1) :: (load 132 from %ir.ptr, align 256, addrspace 1) - ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<33 x s32>) + ; CHECK: G_STORE [[LOAD1]](<33 x s32>), [[COPY]](p5) :: (store 132, align 256, addrspace 5) + ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] + ; CHECK: S_SETPC_B64_return [[COPY2]] %ptr = load volatile <33 x i32> addrspace(1)*, <33 x i32> addrspace(1)* addrspace(4)* undef %val = load <33 x i32>, <33 x i32> addrspace(1)* %ptr ret <33 x i32> %val } +define <33 x i32> @v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx) #0 { + ; CHECK-LABEL: name: v33i32_func_v33i32_i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31 + ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 + ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) + ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY3]](s32) + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 256 + ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]] + ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[MUL]](s64) + ; CHECK: [[COPY5:%[0-9]+]]:_(p1) = COPY [[PTR_ADD]](p1) + ; CHECK: [[LOAD:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[COPY5]](p1) :: (load 132 from %ir.gep, align 256, addrspace 1) + ; CHECK: G_STORE [[LOAD]](<33 x s32>), [[COPY]](p5) :: (store 132, align 256, addrspace 5) + ; CHECK: [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] + ; CHECK: S_SETPC_B64_return [[COPY6]] + %gep = getelementptr inbounds <33 x i32>, <33 x i32> addrspace(1)* %p, i32 %idx + %val = load <33 x i32>, <33 x i32> addrspace(1)* %gep + ret <33 x i32> %val +} + define { <32 x i32>, i32 } @struct_v32i32_i32_func_void() #0 { ; CHECK-LABEL: name: struct_v32i32_i32_func_void - ; CHECK: bb.0: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $sgpr30_sgpr31 - ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 - ; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 + ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 + ; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF ; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `{ <32 x i32>, i32 } addrspace(1)* addrspace(4)* undef`, addrspace 4) ; CHECK: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: (load 128 from %ir.ptr, addrspace 1) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128 ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load 4 from %ir.ptr + 128, align 128, addrspace 1) - ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>) + ; CHECK: G_STORE [[LOAD1]](<32 x s32>), [[COPY]](p5) :: (store 128, addrspace 5) + ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 + ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C1]](s32) + ; CHECK: G_STORE [[LOAD2]](s32), [[PTR_ADD1]](p5) :: (store 4, align 128, addrspace 5) + ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] + ; CHECK: S_SETPC_B64_return [[COPY2]] %ptr = load volatile { <32 x i32>, i32 } addrspace(1)*, { <32 x i32>, i32 } addrspace(1)* addrspace(4)* undef %val = load { <32 x i32>, i32 }, { <32 x i32>, i32 } addrspace(1)* %ptr ret { <32 x i32>, i32 }%val @@ -1207,18 +1236,22 @@ define { i32, <32 x i32> } @struct_i32_v32i32_func_void() #0 { ; CHECK-LABEL: name: struct_i32_v32i32_func_void - ; CHECK: bb.0: - ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $sgpr30_sgpr31 - ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 - ; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF ; CHECK: bb.1 (%ir-block.0): + ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 + ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 + ; CHECK: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF ; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile load 8 from `{ i32, <32 x i32> } addrspace(1)* addrspace(4)* undef`, addrspace 4) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p1) :: (load 4 from %ir.ptr, align 128, addrspace 1) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 128 ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[LOAD]], [[C]](s64) ; CHECK: [[LOAD2:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[PTR_ADD]](p1) :: (load 128 from %ir.ptr + 128, addrspace 1) - ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD2]](<32 x s32>) + ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p5) :: (store 4, align 128, addrspace 5) + ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 + ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C1]](s32) + ; CHECK: G_STORE [[LOAD2]](<32 x s32>), [[PTR_ADD1]](p5) :: (store 128, addrspace 5) + ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] + ; CHECK: S_SETPC_B64_return [[COPY2]] %ptr = load volatile { i32, <32 x i32> } addrspace(1)*, { i32, <32 x i32> } addrspace(1)* addrspace(4)* undef %val = load { i32, <32 x i32> }, { i32, <32 x i32> } addrspace(1)* %ptr ret { i32, <32 x i32> }%val diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll @@ -46,7 +46,10 @@ declare <8 x i32> @external_v8i32_func_void() #0 declare <16 x i32> @external_v16i32_func_void() #0 declare <32 x i32> @external_v32i32_func_void() #0 +declare <33 x i32> @external_v33i32_func_void() #0 +declare <33 x i32> @external_v33i32_func_v33i32_i32(<33 x i32> addrspace(1)*, i32) #0 declare { <32 x i32>, i32 } @external_v32i32_i32_func_void() #0 +declare { i32, <32 x i32> } @external_i32_v32i32_func_void() #0 declare { i32, i64 } @external_i32_i64_func_void() #0 @@ -2751,6 +2754,259 @@ ret void } +define amdgpu_kernel void @test_call_external_v32i32_i32_func_void() #0 { + ; GCN-LABEL: name: test_call_external_v32i32_i32_func_void + ; GCN: bb.1 (%ir-block.0): + ; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1 + ; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0 + ; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16 + ; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15 + ; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14 + ; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11 + ; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7 + ; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5 + ; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9 + ; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GCN: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) + ; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0 + ; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc + ; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v32i32_i32_func_void + ; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]] + ; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]] + ; GCN: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4) + ; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64) + ; GCN: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]] + ; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]] + ; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]] + ; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]] + ; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32) + ; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]] + ; GCN: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 + ; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32) + ; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5) + ; GCN: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg + ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) + ; GCN: $sgpr4_sgpr5 = COPY [[COPY11]](p4) + ; GCN: $sgpr6_sgpr7 = COPY [[COPY12]](p4) + ; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) + ; GCN: $sgpr10_sgpr11 = COPY [[COPY14]](s64) + ; GCN: $sgpr12 = COPY [[COPY15]](s32) + ; GCN: $sgpr13 = COPY [[COPY16]](s32) + ; GCN: $sgpr14 = COPY [[COPY17]](s32) + ; GCN: $vgpr31 = COPY [[OR1]](s32) + ; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v32i32_i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31 + ; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc + ; GCN: [[LOAD:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load 128 from %stack.0, addrspace 5) + ; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 + ; GCN: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C3]](s32) + ; GCN: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load 4 from %stack.0, align 128, addrspace 5) + ; GCN: G_STORE [[LOAD]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1) + ; GCN: G_STORE [[LOAD1]](s32), [[COPY10]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) + ; GCN: S_ENDPGM 0 + %val = call { <32 x i32>, i32 } @external_v32i32_i32_func_void() + %val0 = extractvalue { <32 x i32>, i32 } %val, 0 + %val1 = extractvalue { <32 x i32>, i32 } %val, 1 + store volatile <32 x i32> %val0, <32 x i32> addrspace(1)* undef, align 8 + store volatile i32 %val1, i32 addrspace(1)* undef + ret void +} + +define amdgpu_kernel void @test_call_external_i32_v32i32_func_void() #0 { + ; GCN-LABEL: name: test_call_external_i32_v32i32_func_void + ; GCN: bb.1 (%ir-block.0): + ; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1 + ; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0 + ; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16 + ; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15 + ; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14 + ; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11 + ; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7 + ; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5 + ; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9 + ; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GCN: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) + ; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0 + ; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc + ; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i32_v32i32_func_void + ; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]] + ; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]] + ; GCN: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4) + ; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64) + ; GCN: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]] + ; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]] + ; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]] + ; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]] + ; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32) + ; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]] + ; GCN: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 + ; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32) + ; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5) + ; GCN: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg + ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) + ; GCN: $sgpr4_sgpr5 = COPY [[COPY11]](p4) + ; GCN: $sgpr6_sgpr7 = COPY [[COPY12]](p4) + ; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) + ; GCN: $sgpr10_sgpr11 = COPY [[COPY14]](s64) + ; GCN: $sgpr12 = COPY [[COPY15]](s32) + ; GCN: $sgpr13 = COPY [[COPY16]](s32) + ; GCN: $sgpr14 = COPY [[COPY17]](s32) + ; GCN: $vgpr31 = COPY [[OR1]](s32) + ; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_v32i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31 + ; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc + ; GCN: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (load 4 from %stack.0, align 128, addrspace 5) + ; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 + ; GCN: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C3]](s32) + ; GCN: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[PTR_ADD1]](p5) :: (load 128 from %stack.0, addrspace 5) + ; GCN: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) + ; GCN: G_STORE [[LOAD1]](<32 x s32>), [[COPY10]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1) + ; GCN: S_ENDPGM 0 + %val = call { i32, <32 x i32> } @external_i32_v32i32_func_void() + %val0 = extractvalue { i32, <32 x i32> } %val, 0 + %val1 = extractvalue { i32, <32 x i32> } %val, 1 + store volatile i32 %val0, i32 addrspace(1)* undef + store volatile <32 x i32> %val1, <32 x i32> addrspace(1)* undef, align 8 + ret void +} + +define amdgpu_kernel void @test_call_external_v33i32_func_void() #0 { + ; GCN-LABEL: name: test_call_external_v33i32_func_void + ; GCN: bb.1 (%ir-block.0): + ; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1 + ; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0 + ; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16 + ; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15 + ; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14 + ; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11 + ; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7 + ; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5 + ; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9 + ; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0 + ; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc + ; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v33i32_func_void + ; GCN: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]] + ; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]] + ; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4) + ; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64) + ; GCN: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]] + ; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]] + ; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]] + ; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]] + ; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32) + ; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]] + ; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 + ; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32) + ; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5) + ; GCN: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg + ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) + ; GCN: $sgpr4_sgpr5 = COPY [[COPY10]](p4) + ; GCN: $sgpr6_sgpr7 = COPY [[COPY11]](p4) + ; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) + ; GCN: $sgpr10_sgpr11 = COPY [[COPY13]](s64) + ; GCN: $sgpr12 = COPY [[COPY14]](s32) + ; GCN: $sgpr13 = COPY [[COPY15]](s32) + ; GCN: $sgpr14 = COPY [[COPY16]](s32) + ; GCN: $vgpr31 = COPY [[OR1]](s32) + ; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v33i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31 + ; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc + ; GCN: [[LOAD:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load 132 from %stack.0, align 256, addrspace 5) + ; GCN: G_STORE [[LOAD]](<33 x s32>), [[DEF]](p1) :: (volatile store 132 into `<33 x i32> addrspace(1)* undef`, align 8, addrspace 1) + ; GCN: S_ENDPGM 0 + %val = call <33 x i32> @external_v33i32_func_void() + store volatile <33 x i32> %val, <33 x i32> addrspace(1)* undef, align 8 + ret void +} + +define amdgpu_kernel void @test_call_external_v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx) #0 { + ; GCN-LABEL: name: test_call_external_v33i32_func_v33i32_i32 + ; GCN: bb.1 (%ir-block.0): + ; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1 + ; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0 + ; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16 + ; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15 + ; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14 + ; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11 + ; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7 + ; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5 + ; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9 + ; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GCN: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr) + ; GCN: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load 8 from %ir.p.kernarg.offset.cast, align 16, addrspace 4) + ; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; GCN: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[INT]], [[C]](s64) + ; GCN: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 4 from %ir.idx.kernarg.offset.cast, align 8, addrspace 4) + ; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0 + ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1) + ; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc + ; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v33i32_func_v33i32_i32 + ; GCN: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]] + ; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]] + ; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4) + ; GCN: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; GCN: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C1]](s64) + ; GCN: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]] + ; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]] + ; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]] + ; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]] + ; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32) + ; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]] + ; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 + ; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32) + ; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; GCN: $vgpr0 = COPY [[FRAME_INDEX]](p5) + ; GCN: $vgpr1 = COPY [[UV]](s32) + ; GCN: $vgpr2 = COPY [[UV1]](s32) + ; GCN: $vgpr3 = COPY [[LOAD1]](s32) + ; GCN: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg + ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) + ; GCN: $sgpr4_sgpr5 = COPY [[COPY10]](p4) + ; GCN: $sgpr6_sgpr7 = COPY [[COPY11]](p4) + ; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4) + ; GCN: $sgpr10_sgpr11 = COPY [[COPY13]](s64) + ; GCN: $sgpr12 = COPY [[COPY14]](s32) + ; GCN: $sgpr13 = COPY [[COPY15]](s32) + ; GCN: $sgpr14 = COPY [[COPY16]](s32) + ; GCN: $vgpr31 = COPY [[OR1]](s32) + ; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v33i32_func_v33i32_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31 + ; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc + ; GCN: [[LOAD2:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load 132 from %stack.0, align 256, addrspace 5) + ; GCN: G_STORE [[LOAD2]](<33 x s32>), [[DEF]](p1) :: (volatile store 132 into `<33 x i32> addrspace(1)* undef`, align 8, addrspace 1) + ; GCN: S_ENDPGM 0 + %val = call <33 x i32> @external_v33i32_func_v33i32_i32(<33 x i32> addrspace(1)* %p, i32 %idx) + store volatile <33 x i32> %val, <33 x i32> addrspace(1)* undef, align 8 + ret void +} + attributes #0 = { nounwind } attributes #1 = { nounwind readnone } attributes #2 = { nounwind noinline }