diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h --- a/clang/lib/Basic/Targets/AArch64.h +++ b/clang/lib/Basic/Targets/AArch64.h @@ -36,6 +36,7 @@ bool HasFP16FML; bool HasMTE; bool HasTME; + bool HasPAuth; bool HasLS64; bool HasMatMul; bool HasSVE2; diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -510,6 +510,8 @@ HasMTE = true; if (Feature == "+tme") HasTME = true; + if (Feature == "+pauth") + HasPAuth = true; if (Feature == "+i8mm") HasMatMul = true; if (Feature == "+bf16") diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h --- a/llvm/include/llvm/Support/AArch64TargetParser.h +++ b/llvm/include/llvm/Support/AArch64TargetParser.h @@ -64,6 +64,7 @@ AEK_F64MM = 1ULL << 32, AEK_LS64 = 1ULL << 33, AEK_BRBE = 1ULL << 34, + AEK_PAUTH = 1ULL << 35, }; enum class ArchKind { diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def --- a/llvm/include/llvm/Support/AArch64TargetParser.def +++ b/llvm/include/llvm/Support/AArch64TargetParser.def @@ -108,6 +108,7 @@ AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme", "-tme") AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64, "+ls64", "-ls64") AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE, "+brbe", "-brbe") +AARCH64_ARCH_EXT_NAME("pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth") #undef AARCH64_ARCH_EXT_NAME #ifndef AARCH64_CPU_NAME diff --git a/llvm/lib/Support/AArch64TargetParser.cpp b/llvm/lib/Support/AArch64TargetParser.cpp --- a/llvm/lib/Support/AArch64TargetParser.cpp +++ b/llvm/lib/Support/AArch64TargetParser.cpp @@ -102,6 +102,8 @@ Features.push_back("+rcpc"); if (Extensions & AEK_BRBE) Features.push_back("+brbe"); + if (Extensions & AEK_PAUTH) + Features.push_back("+pauth"); return true; } diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -261,8 +261,8 @@ "dotprod", "HasDotProd", "true", "Enable dot product support">; -def FeaturePA : SubtargetFeature< - "pa", "HasPA", "true", +def FeaturePAuth : SubtargetFeature< + "pauth", "HasPAuth", "true", "Enable v8.3-A Pointer Authentication extension">; def FeatureJS : SubtargetFeature< @@ -438,7 +438,7 @@ FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", - "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA, + "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth, FeatureJS, FeatureCCIDX, FeatureComplxNum]>; def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", @@ -471,7 +471,7 @@ FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV, //v8.3 FeatureComplxNum, FeatureCCIDX, FeatureJS, - FeaturePA, FeatureRCPC, + FeaturePAuth, FeatureRCPC, //v8.4 FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4, FeatureTLB_RMI, FeatureFMI, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, @@ -539,7 +539,7 @@ } def PAUnsupported : AArch64Unsupported { - let F = [HasPA]; + let F = [HasPAuth]; } include "AArch64SchedA53.td" @@ -703,7 +703,7 @@ FeatureFullFP16, FeatureFuseAES, FeatureNEON, - FeaturePA, + FeaturePAuth, FeaturePerfMon, FeaturePostRAScheduler, FeatureRCPC, @@ -1015,7 +1015,7 @@ FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureLSE, - FeaturePA, + FeaturePAuth, FeatureUseAA, FeatureBalanceFPOps, FeaturePerfMon, diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1511,7 +1511,7 @@ // this instruction can safely used for any v8a architecture. // From v8.3a onwards there are optimised authenticate LR and return // instructions, namely RETA{A,B}, that can be used instead. - if (Subtarget.hasV8_3aOps() && MBBI != MBB.end() && + if (Subtarget.hasPAuth() && MBBI != MBB.end() && MBBI->getOpcode() == AArch64::RET_ReallyLR) { BuildMI(MBB, MBBI, DL, TII->get(MFI.shouldSignWithBKey() ? AArch64::RETAB : AArch64::RETAA)) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -7252,7 +7252,7 @@ // Armv8.3-A architectures. On Armv8.3-A and onwards XPACI is available so use // that instead. SDNode *St; - if (Subtarget->hasV8_3aOps()) { + if (Subtarget->hasPAuth()) { St = DAG.getMachineNode(AArch64::XPACI, DL, VT, ReturnAddress); } else { // XPACLRI operates on LR therefore we must move the operand accordingly. diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -6818,7 +6818,7 @@ // If v8.3a features are available we can replace a RET instruction by // RETAA or RETAB and omit the AUT instructions - if (Subtarget.hasV8_3aOps() && MBBAUT != MBB.end() && + if (Subtarget.hasPAuth() && MBBAUT != MBB.end() && MBBAUT->getOpcode() == AArch64::RET) { BuildMI(MBB, MBBAUT, DL, TII->get(ShouldSignReturnAddrWithAKey ? AArch64::RETAA diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -33,8 +33,8 @@ def HasLOR : Predicate<"Subtarget->hasLOR()">, AssemblerPredicate<(all_of FeatureLOR), "lor">; -def HasPA : Predicate<"Subtarget->hasPA()">, - AssemblerPredicate<(all_of FeaturePA), "pa">; +def HasPAuth : Predicate<"Subtarget->hasPAuth()">, + AssemblerPredicate<(all_of FeaturePAuth), "pauth">; def HasJS : Predicate<"Subtarget->hasJS()">, AssemblerPredicate<(all_of FeatureJS), "jsconv">; @@ -1073,7 +1073,7 @@ def : InstAlias<"xpaclri", (XPACLRI), 0>; // These pointer authentication instructions require armv8.3a -let Predicates = [HasPA] in { +let Predicates = [HasPAuth] in { // When PA is enabled, a better mnemonic should be emitted. def : InstAlias<"paciaz", (PACIAZ), 1>; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -126,7 +126,7 @@ bool HasAES = false; // ARMv8.3 extensions - bool HasPA = false; + bool HasPAuth = false; bool HasJS = false; bool HasCCIDX = false; bool HasComplxNum = false; @@ -186,6 +186,7 @@ bool HasETE = false; bool HasTRBE = false; bool HasBRBE = false; + bool HasPAUTH = false; bool HasSPE_EEF = false; // HasZeroCycleRegMove - Has zero-cycle register mov instructions. @@ -450,6 +451,7 @@ bool hasRandGen() const { return HasRandGen; } bool hasMTE() const { return HasMTE; } bool hasTME() const { return HasTME; } + bool hasPAUTH() const { return HasPAUTH; } // Arm SVE2 extensions bool hasSVE2AES() const { return HasSVE2AES; } bool hasSVE2SM4() const { return HasSVE2SM4; } @@ -493,7 +495,7 @@ bool hasPAN_RWV() const { return HasPAN_RWV; } bool hasCCPP() const { return HasCCPP; } - bool hasPA() const { return HasPA; } + bool hasPAuth() const { return HasPAuth; } bool hasJS() const { return HasJS; } bool hasCCIDX() const { return HasCCIDX; } bool hasComplxNum() const { return HasComplxNum; } diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -1336,7 +1336,7 @@ // v8.3a "Pointer authentication extension" registers // Op0 Op1 CRn CRm Op2 -let Requires = [{ {AArch64::FeaturePA} }] in { +let Requires = [{ {AArch64::FeaturePAuth} }] in { def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>; def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>; def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>; diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -4958,7 +4958,7 @@ AArch64::GPR64RegClass); } - if (STI.hasV8_3aOps()) { + if (STI.hasPAuth()) { MIRBuilder.buildInstr(AArch64::XPACI, {DstReg}, {MFReturnAddr}); } else { MIRBuilder.buildCopy({Register(AArch64::LR)}, {MFReturnAddr}); @@ -4986,7 +4986,7 @@ else { MFI.setReturnAddressIsTaken(true); - if (STI.hasV8_3aOps()) { + if (STI.hasPAuth()) { Register TmpReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); MIRBuilder.buildInstr(AArch64::LDRXui, {TmpReg}, {FrameAddr}).addImm(1); MIRBuilder.buildInstr(AArch64::XPACI, {DstReg}, {TmpReg}); diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp --- a/llvm/unittests/Support/TargetParserTest.cpp +++ b/llvm/unittests/Support/TargetParserTest.cpp @@ -1431,6 +1431,7 @@ {"rng", "norng", "+rand", "-rand"}, {"memtag", "nomemtag", "+mte", "-mte"}, {"tme", "notme", "+tme", "-tme"}, + {"pauth", "nopauth", "+pauth", "-pauth"}, {"ssbs", "nossbs", "+ssbs", "-ssbs"}, {"sb", "nosb", "+sb", "-sb"}, {"predres", "nopredres", "+predres", "-predres"},