Index: lib/CodeGen/TargetInstrInfo.cpp
===================================================================
--- lib/CodeGen/TargetInstrInfo.cpp
+++ lib/CodeGen/TargetInstrInfo.cpp
@@ -142,6 +142,8 @@
   unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
   bool Reg1IsKill = MI->getOperand(Idx1).isKill();
   bool Reg2IsKill = MI->getOperand(Idx2).isKill();
+  bool Reg1IsUndef = MI->getOperand(Idx1).isUndef();
+  bool Reg2IsUndef = MI->getOperand(Idx2).isUndef();
   // If destination is tied to either of the commuted source register, then
   // it must be updated.
   if (HasDef && Reg0 == Reg1 &&
@@ -172,6 +174,8 @@
   MI->getOperand(Idx1).setSubReg(SubReg2);
   MI->getOperand(Idx2).setIsKill(Reg1IsKill);
   MI->getOperand(Idx1).setIsKill(Reg2IsKill);
+  MI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
+  MI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
   return MI;
 }
 
Index: test/CodeGen/X86/pr23103.ll
===================================================================
--- test/CodeGen/X86/pr23103.ll
+++ test/CodeGen/X86/pr23103.ll
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx < %s
+
+; When commuting a VADDSDrr instruction, verify that the 'isUndef' flag is
+; correctly propagated to the operands of the resulting instruction.
+; Test for PR23103;
+
+declare zeroext i1 @foo()
+
+define <1 x double> @pr23103(<1 x double>* align 8) {
+entry:
+  %A1114 = load <1 x double>, <1 x double>* %0, align 8
+  %call.i = call zeroext i1 @foo()
+  %A1114.op = fadd <1 x double> %A1114, undef
+  %A1114.op.op = fadd <1 x double> %A1114.op, undef
+  %add4 = select i1 %call.i, <1 x double> <double fadd (double fadd (double 1.000000e+00, double undef), double undef)>, <1 x double> %A1114.op.op
+  ret <1 x double> %add4
+}