diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1131,6 +1131,11 @@
   Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
   AssemblerPredicate<(all_of FeatureGFX10Insts)>;
 
+def isGFX10Before1030 :
+  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
+            "!Subtarget->hasGFX10_3Insts()">,
+  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
+
 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
   AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
 
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -867,6 +867,10 @@
   defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>;
 } // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
 
+let SubtargetPredicate = isGFX10Before1030 in {
+  defm V_MUL_LO_I32      : VOP3_Real_gfx10<0x16b>;
+}
+
 defm V_XOR3_B32           : VOP3_Real_gfx10<0x178>;
 defm V_LSHLREV_B64        : VOP3_Real_gfx10<0x2ff>;
 defm V_LSHRREV_B64        : VOP3_Real_gfx10<0x300>;
@@ -992,6 +996,7 @@
 defm V_LSHL_B64        : VOP3_Real_gfx6_gfx7<0x161>;
 defm V_LSHR_B64        : VOP3_Real_gfx6_gfx7<0x162>;
 defm V_ASHR_I64        : VOP3_Real_gfx6_gfx7<0x163>;
+defm V_MUL_LO_I32      : VOP3_Real_gfx6_gfx7<0x16b>;
 
 defm V_MAD_LEGACY_F32  : VOP3_Real_gfx6_gfx7_gfx10<0x140>;
 defm V_MAD_F32         : VOP3_Real_gfx6_gfx7_gfx10<0x141>;
@@ -1033,7 +1038,6 @@
 defm V_LDEXP_F64       : VOP3_Real_gfx6_gfx7_gfx10<0x168>;
 defm V_MUL_LO_U32      : VOP3_Real_gfx6_gfx7_gfx10<0x169>;
 defm V_MUL_HI_U32      : VOP3_Real_gfx6_gfx7_gfx10<0x16a>;
-defm V_MUL_LO_I32      : VOP3_Real_gfx6_gfx7_gfx10<0x16b>;
 defm V_MUL_HI_I32      : VOP3_Real_gfx6_gfx7_gfx10<0x16c>;
 defm V_DIV_FMAS_F32    : VOP3_Real_gfx6_gfx7_gfx10<0x16f>;
 defm V_DIV_FMAS_F64    : VOP3_Real_gfx6_gfx7_gfx10<0x170>;
diff --git a/llvm/test/MC/AMDGPU/gfx1030_unsupported.s b/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
--- a/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
@@ -1,6 +1,9 @@
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
 
+v_mul_lo_i32 v0, v1, v2
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 //===----------------------------------------------------------------------===//
 // Unsupported dpp variants.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
@@ -6685,6 +6685,30 @@
 v_mul_hi_u32 v5, v1, -4.0
 // GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xef,0x01,0x00]
 
+v_mul_lo_i32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x6b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x67,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x77,0x04,0x02,0x00]
+
 v_mul_hi_i32 v5, v1, v2
 // GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x05,0x02,0x00]