diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
--- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
@@ -218,14 +218,15 @@
     // If the condition is an OR of 2 compares and the false successor only has
     // the current block as predecessor, queue both negated conditions for the
     // false successor.
-    if (match(Br->getCondition(), m_Or(m_Cmp(), m_Cmp()))) {
+    Value *Op0, *Op1;
+    if (match(Br->getCondition(), m_LogicalOr(m_Value(Op0), m_Value(Op1))) &&
+        match(Op0, m_Cmp()) && match(Op1, m_Cmp())) {
       BasicBlock *FalseSuccessor = Br->getSuccessor(1);
       if (FalseSuccessor->getSinglePredecessor()) {
-        auto *OrI = cast<Instruction>(Br->getCondition());
-        WorkList.emplace_back(DT.getNode(FalseSuccessor),
-                              cast<CmpInst>(OrI->getOperand(0)), true);
-        WorkList.emplace_back(DT.getNode(FalseSuccessor),
-                              cast<CmpInst>(OrI->getOperand(1)), true);
+        WorkList.emplace_back(DT.getNode(FalseSuccessor), cast<CmpInst>(Op0),
+                              true);
+        WorkList.emplace_back(DT.getNode(FalseSuccessor), cast<CmpInst>(Op1),
+                              true);
       }
       continue;
     }
@@ -233,14 +234,14 @@
     // If the condition is an AND of 2 compares and the true successor only has
     // the current block as predecessor, queue both conditions for the true
     // successor.
-    if (match(Br->getCondition(), m_And(m_Cmp(), m_Cmp()))) {
+    if (match(Br->getCondition(), m_LogicalAnd(m_Value(Op0), m_Value(Op1))) &&
+        match(Op0, m_Cmp()) && match(Op1, m_Cmp())) {
       BasicBlock *TrueSuccessor = Br->getSuccessor(0);
       if (TrueSuccessor->getSinglePredecessor()) {
-        auto *AndI = cast<Instruction>(Br->getCondition());
-        WorkList.emplace_back(DT.getNode(TrueSuccessor),
-                              cast<CmpInst>(AndI->getOperand(0)), false);
-        WorkList.emplace_back(DT.getNode(TrueSuccessor),
-                              cast<CmpInst>(AndI->getOperand(1)), false);
+        WorkList.emplace_back(DT.getNode(TrueSuccessor), cast<CmpInst>(Op0),
+                              false);
+        WorkList.emplace_back(DT.getNode(TrueSuccessor), cast<CmpInst>(Op1),
+                              false);
       }
       continue;
     }
diff --git a/llvm/test/Transforms/ConstraintElimination/and.ll b/llvm/test/Transforms/ConstraintElimination/and.ll
--- a/llvm/test/Transforms/ConstraintElimination/and.ll
+++ b/llvm/test/Transforms/ConstraintElimination/and.ll
@@ -69,6 +69,7 @@
   ret i32 20
 }
 
+; The result of test_and_ule and test_and_select_ule should be same
 define i32 @test_and_select_ule(i32 %x, i32 %y, i32 %z, i32 %a) {
 ; CHECK-LABEL: @test_and_select_ule(
 ; CHECK-NEXT:  entry:
@@ -78,11 +79,11 @@
 ; CHECK-NEXT:    br i1 [[AND]], label [[BB1:%.*]], label [[EXIT:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[T_1:%.*]] = icmp ule i32 [[X]], [[Z]]
-; CHECK-NEXT:    call void @use(i1 [[T_1]])
+; CHECK-NEXT:    call void @use(i1 true)
 ; CHECK-NEXT:    [[T_2:%.*]] = icmp ule i32 [[X]], [[Y]]
-; CHECK-NEXT:    call void @use(i1 [[T_2]])
+; CHECK-NEXT:    call void @use(i1 true)
 ; CHECK-NEXT:    [[T_3:%.*]] = icmp ule i32 [[Y]], [[Z]]
-; CHECK-NEXT:    call void @use(i1 [[T_3]])
+; CHECK-NEXT:    call void @use(i1 true)
 ; CHECK-NEXT:    [[C_3:%.*]] = icmp ule i32 [[X]], [[A:%.*]]
 ; CHECK-NEXT:    call void @use(i1 [[C_3]])
 ; CHECK-NEXT:    ret i32 10
diff --git a/llvm/test/Transforms/ConstraintElimination/or.ll b/llvm/test/Transforms/ConstraintElimination/or.ll
--- a/llvm/test/Transforms/ConstraintElimination/or.ll
+++ b/llvm/test/Transforms/ConstraintElimination/or.ll
@@ -63,6 +63,7 @@
   ret i32 20
 }
 
+; The result of test_or_ule and test_or_select_ule should be same
 define i32 @test_or_select_ule(i32 %x, i32 %y, i32 %z, i32 %a) {
 ; CHECK-LABEL: @test_or_select_ule(
 ; CHECK-NEXT:  entry:
@@ -78,15 +79,15 @@
 ; CHECK-NEXT:    ret i32 10
 ; CHECK:       exit:
 ; CHECK-NEXT:    [[F_1:%.*]] = icmp ule i32 [[X]], [[Z]]
-; CHECK-NEXT:    call void @use(i1 [[F_1]])
+; CHECK-NEXT:    call void @use(i1 false)
 ; CHECK-NEXT:    [[C_5:%.*]] = icmp ule i32 [[X]], [[A]]
 ; CHECK-NEXT:    call void @use(i1 [[C_5]])
 ; CHECK-NEXT:    [[T_1:%.*]] = icmp ugt i32 [[Y]], [[Z]]
-; CHECK-NEXT:    call void @use(i1 [[T_1]])
+; CHECK-NEXT:    call void @use(i1 true)
 ; CHECK-NEXT:    [[T_2:%.*]] = icmp ugt i32 [[X]], [[Y]]
-; CHECK-NEXT:    call void @use(i1 [[T_2]])
+; CHECK-NEXT:    call void @use(i1 true)
 ; CHECK-NEXT:    [[T_3:%.*]] = icmp ugt i32 [[X]], [[Z]]
-; CHECK-NEXT:    call void @use(i1 [[T_3]])
+; CHECK-NEXT:    call void @use(i1 true)
 ; CHECK-NEXT:    ret i32 20
 ;
 entry: