Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -313,7 +313,28 @@
                     [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
     let ExtendOperand = 3;
   }
-
+  // For vmv.v.v, vmv.v.x, vmv.v.i
+  // Input: (vector_in/scalar_in, vl)
+  class RISCVUnary : Intrinsic<[llvm_anyvector_ty],
+                               [llvm_any_ty, llvm_anyint_ty],
+                               [IntrNoMem] >, RISCVVIntrinsic {
+    let ExtendOperand = 1;
+  }
+  // For destination vector type is the same as source vector.
+  // Input: (vector_in, vl)
+  class RISCVUnaryAANoMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+  }
+  // For destination vector type is the same as source vector (with mask).
+  // Input: (maskedoff, vector_in, mask, vl)
+  class RISCVUnaryAAMask
+       : Intrinsic<[llvm_anyvector_ty],
+                   [LLVMMatchType<0>, LLVMMatchType<0>,
+                    LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                   [IntrNoMem]>, RISCVVIntrinsic {
+  }
   class RISCVTernaryAAAXNoMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
@@ -378,7 +399,10 @@
     def "int_riscv_" # NAME : RISCVIStore;
     def "int_riscv_" # NAME # "_mask" : RISCVIStoreMask;
   }
-
+  multiclass RISCVUnaryAA {
+    def "int_riscv_" # NAME : RISCVUnaryAANoMask;
+    def "int_riscv_" # NAME # "_mask" : RISCVUnaryAAMask;
+  }
   // AAX means the destination type(A) is the same as the first source
   // type(A). X means any type for the second source operand.
   multiclass RISCVBinaryAAX {
@@ -560,6 +584,8 @@
   defm vfmsub : RISCVTernaryAAXA;
   defm vfnmsub : RISCVTernaryAAXA;
 
+  defm vfsqrt : RISCVUnaryAA;
+
   defm vfmin : RISCVBinaryAAX;
   defm vfmax : RISCVBinaryAAX;
 
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -467,6 +467,22 @@
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
+class VPseudoUnaryNoMask<VReg RetClass,
+                         DAGOperand Op2Class> :
+        Pseudo<(outs RetClass:$rd),
+               (ins Op2Class:$rs2, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Uses = [VL, VTYPE];
+  let VLIndex = 2;
+  let SEWIndex = 3;
+  let HasDummyMask = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
 class VPseudoBinaryNoMask<VReg RetClass,
                           VReg Op1Class,
                           DAGOperand Op2Class,
@@ -515,6 +531,24 @@
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
+class VPseudoUnaryMask<VReg RetClass,
+                       DAGOperand Op2Class> :
+        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+                (ins GetVRegNoV0<RetClass>.R:$merge,
+                     Op2Class:$rs2,
+                     VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Uses = [VL, VTYPE];
+  let VLIndex = 4;
+  let SEWIndex = 5;
+  let MergeOpIndex = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
 class VPseudoBinaryMask<VReg RetClass,
                         VReg Op1Class,
                         DAGOperand Op2Class,
@@ -655,6 +689,15 @@
   }
 }
 
+multiclass VPseudoUnary<VReg RetClass,
+                        DAGOperand Op2Class,
+                        LMULInfo MInfo> {
+  let VLMul = MInfo.value in {
+    def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op2Class>;
+    def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op2Class>;
+  }
+}
+
 multiclass VPseudoBinary<VReg RetClass,
                          VReg Op1Class,
                          DAGOperand Op2Class,
@@ -799,6 +842,11 @@
     defm _VI : VPseudoBinary<VR, m.vrclass, simm5, m, "@earlyclobber $rd">;
 }
 
+multiclass VPseudoUnaryV_V {
+  foreach m = MxList.m in
+    defm _V : VPseudoUnary<m.vrclass, m.vrclass, m>;
+}
+
 multiclass VPseudoBinaryV_VV_VX_VI<Operand ImmType = simm5> {
   defm "" : VPseudoBinaryV_VV;
   defm "" : VPseudoBinaryV_VX</*IsFloat=*/0>;
@@ -994,6 +1042,42 @@
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns.
 //===----------------------------------------------------------------------===//
+class VPatUnaryNoMask<string intrinsic_name,
+                      string inst,
+                      string kind,
+                      ValueType result_type,
+                      ValueType op2_type,
+                      int sew,
+                      LMULInfo vlmul,
+                      VReg op2_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
+                   (op2_type op2_reg_class:$rs2),
+                   (XLenVT GPR:$vl))),
+                   (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
+                   (op2_type op2_reg_class:$rs2),
+                   (NoX0 GPR:$vl), sew)>;
+
+class VPatUnaryMask<string intrinsic_name,
+                    string inst,
+                    string kind,
+                    ValueType result_type,
+                    ValueType op2_type,
+                    ValueType mask_type,
+                    int sew,
+                    LMULInfo vlmul,
+                    VReg result_reg_class,
+                    VReg op2_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
+                   (result_type result_reg_class:$merge),
+                   (op2_type op2_reg_class:$rs2),
+                   (mask_type V0),
+                   (XLenVT GPR:$vl))),
+                   (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
+                   (result_type result_reg_class:$merge),
+                   (op2_type op2_reg_class:$rs2),
+                   (mask_type V0),
+                   (NoX0 GPR:$vl), sew)>;
+
 class VPatBinaryNoMask<string intrinsic_name,
                        string inst,
                        string kind,
@@ -1209,6 +1293,22 @@
               (PseudoMask $rs3, $rs1, $rs2, (mask_type V0), (NoX0 GPR:$vl), sew)>;
 }
 
+multiclass VPatUnary<string intrinsic,
+                     string inst,
+                     string kind,
+                     ValueType result_type,
+                     ValueType op2_type,
+                     ValueType mask_type,
+                     int sew,
+                     LMULInfo vlmul,
+                     VReg result_reg_class,
+                     VReg op2_reg_class> {
+  def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op2_type,
+                        sew, vlmul, op2_reg_class>;
+  def : VPatUnaryMask<intrinsic, inst, kind, result_type, op2_type, mask_type,
+                      sew, vlmul, result_reg_class, op2_reg_class>;
+}
+
 multiclass VPatBinary<string intrinsic,
                       string inst,
                       string kind,
@@ -1273,6 +1373,15 @@
                          (NoX0 GPR:$vl), sew)>;
 }
 
+multiclass VPatUnaryV_V<string intrinsic, string instruction,
+                        list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in
+    defm : VPatUnary<intrinsic, instruction, "V",
+                     vti.Vector, vti.Vector, vti.Mask,
+                     vti.SEW, vti.LMul, vti.RegClass,
+                     vti.RegClass>;
+}
+
 multiclass VPatBinaryV_VV<string intrinsic, string instruction,
                           list<VTypeInfo> vtilist> {
   foreach vti = vtilist in
@@ -1954,6 +2063,11 @@
 defm PseudoVFNMSUB     : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
 
 //===----------------------------------------------------------------------===//
+// 14.8. Vector Floating-Point Square-Root Instruction
+//===----------------------------------------------------------------------===//
+defm PseudoVFSQRT      : VPseudoUnaryV_V;
+
+//===----------------------------------------------------------------------===//
 // 14.9. Vector Floating-Point Min/Max Instructions
 //===----------------------------------------------------------------------===//
 defm PseudoVFMIN       : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
@@ -2353,6 +2467,11 @@
 defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors>;
 
 //===----------------------------------------------------------------------===//
+// 14.8. Vector Floating-Point Square-Root Instruction
+//===----------------------------------------------------------------------===//
+defm "" : VPatUnaryV_V<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors>;
+
+//===----------------------------------------------------------------------===//
 // 14.9. Vector Floating-Point Min/Max Instructions
 //===----------------------------------------------------------------------===//
 defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>;
Index: llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll
@@ -0,0 +1,397 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
+    <vscale x 1 x half> undef,
+    i32 undef)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
+    <vscale x 1 x half> undef,
+    <vscale x 1 x half> undef,
+    <vscale x 1 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfsqrt_v_nxv2f16_nxv2f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
+    <vscale x 2 x half> undef,
+    i32 undef)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
+    <vscale x 2 x half> undef,
+    <vscale x 2 x half> undef,
+    <vscale x 2 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfsqrt_v_nxv4f16_nxv4f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
+    <vscale x 4 x half> undef,
+    i32 undef)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
+    <vscale x 4 x half> undef,
+    <vscale x 4 x half> undef,
+    <vscale x 4 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfsqrt_v_nxv8f16_nxv8f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
+    <vscale x 8 x half> undef,
+    i32 undef)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
+    <vscale x 8 x half> undef,
+    <vscale x 8 x half> undef,
+    <vscale x 8 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfsqrt_v_nxv16f16_nxv16f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
+    <vscale x 16 x half> undef,
+    i32 undef)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
+    <vscale x 16 x half> undef,
+    <vscale x 16 x half> undef,
+    <vscale x 16 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
+  <vscale x 32 x half>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfsqrt_v_nxv32f16_nxv32f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
+    <vscale x 32 x half> undef,
+    i32 undef)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
+    <vscale x 32 x half> undef,
+    <vscale x 32 x half> undef,
+    <vscale x 32 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfsqrt_v_nxv1f32_nxv1f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
+    <vscale x 1 x float> undef,
+    i32 undef)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
+    <vscale x 1 x float> undef,
+    <vscale x 1 x float> undef,
+    <vscale x 1 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfsqrt_v_nxv2f32_nxv2f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
+    <vscale x 2 x float> undef,
+    i32 undef)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
+    <vscale x 2 x float> undef,
+    <vscale x 2 x float> undef,
+    <vscale x 2 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfsqrt_v_nxv4f32_nxv4f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
+    <vscale x 4 x float> undef,
+    i32 undef)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
+    <vscale x 4 x float> undef,
+    <vscale x 4 x float> undef,
+    <vscale x 4 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfsqrt_v_nxv8f32_nxv8f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
+    <vscale x 8 x float> undef,
+    i32 undef)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
+    <vscale x 8 x float> undef,
+    <vscale x 8 x float> undef,
+    <vscale x 8 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
+  <vscale x 16 x float>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfsqrt_v_nxv16f32_nxv16f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
+    <vscale x 16 x float> undef,
+    i32 undef)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
+    <vscale x 16 x float> undef,
+    <vscale x 16 x float> undef,
+    <vscale x 16 x i1> undef,
+    i32 undef)
+
+  ret <vscale x 16 x float> %a
+}
Index: llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll
@@ -0,0 +1,541 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
+    <vscale x 1 x half> undef,
+    i64 undef)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
+    <vscale x 1 x half> undef,
+    <vscale x 1 x half> undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfsqrt_v_nxv2f16_nxv2f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
+    <vscale x 2 x half> undef,
+    i64 undef)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
+    <vscale x 2 x half> undef,
+    <vscale x 2 x half> undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfsqrt_v_nxv4f16_nxv4f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
+    <vscale x 4 x half> undef,
+    i64 undef)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
+    <vscale x 4 x half> undef,
+    <vscale x 4 x half> undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfsqrt_v_nxv8f16_nxv8f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
+    <vscale x 8 x half> undef,
+    i64 undef)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
+    <vscale x 8 x half> undef,
+    <vscale x 8 x half> undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfsqrt_v_nxv16f16_nxv16f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
+    <vscale x 16 x half> undef,
+    i64 undef)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
+    <vscale x 16 x half> undef,
+    <vscale x 16 x half> undef,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
+  <vscale x 32 x half>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfsqrt_v_nxv32f16_nxv32f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
+    <vscale x 32 x half> undef,
+    i64 undef)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
+    <vscale x 32 x half> undef,
+    <vscale x 32 x half> undef,
+    <vscale x 32 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfsqrt_v_nxv1f32_nxv1f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
+    <vscale x 1 x float> undef,
+    i64 undef)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
+    <vscale x 1 x float> undef,
+    <vscale x 1 x float> undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfsqrt_v_nxv2f32_nxv2f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
+    <vscale x 2 x float> undef,
+    i64 undef)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
+    <vscale x 2 x float> undef,
+    <vscale x 2 x float> undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfsqrt_v_nxv4f32_nxv4f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
+    <vscale x 4 x float> undef,
+    i64 undef)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
+    <vscale x 4 x float> undef,
+    <vscale x 4 x float> undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfsqrt_v_nxv8f32_nxv8f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
+    <vscale x 8 x float> undef,
+    i64 undef)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
+    <vscale x 8 x float> undef,
+    <vscale x 8 x float> undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
+  <vscale x 16 x float>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfsqrt_v_nxv16f32_nxv16f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
+    <vscale x 16 x float> undef,
+    i64 undef)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
+    <vscale x 16 x float> undef,
+    <vscale x 16 x float> undef,
+    <vscale x 16 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64(
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfsqrt_v_nxv1f64_nxv1f64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64(
+    <vscale x 1 x double> undef,
+    i64 undef)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64(
+    <vscale x 1 x double> undef,
+    <vscale x 1 x double> undef,
+    <vscale x 1 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64(
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfsqrt_v_nxv2f64_nxv2f64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64(
+    <vscale x 2 x double> undef,
+    i64 undef)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64(
+    <vscale x 2 x double> undef,
+    <vscale x 2 x double> undef,
+    <vscale x 2 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64(
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfsqrt_v_nxv4f64_nxv4f64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64(
+    <vscale x 4 x double> undef,
+    i64 undef)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64(
+    <vscale x 4 x double> undef,
+    <vscale x 4 x double> undef,
+    <vscale x 4 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64(
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfsqrt_v_nxv8f64_nxv8f64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64(
+    <vscale x 8 x double> undef,
+    i64 undef)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfsqrt.mask.nxv8f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64() nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vfsqrt.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x double> @llvm.riscv.vfsqrt.mask.nxv8f64(
+    <vscale x 8 x double> undef,
+    <vscale x 8 x double> undef,
+    <vscale x 8 x i1> undef,
+    i64 undef)
+
+  ret <vscale x 8 x double> %a
+}