Index: llvm/include/llvm/TableGen/Record.h =================================================================== --- llvm/include/llvm/TableGen/Record.h +++ llvm/include/llvm/TableGen/Record.h @@ -1804,7 +1804,7 @@ /// Get all the concrete records that inherit from the one specified /// class. The class must be defined. - std::vector getAllDerivedDefinitions(StringRef ClassName) const; + ArrayRef getAllDerivedDefinitions(StringRef ClassName) const; /// Get all the concrete records that inherit from all the specified /// classes. The classes must be defined. Index: llvm/lib/TableGen/Record.cpp =================================================================== --- llvm/lib/TableGen/Record.cpp +++ llvm/lib/TableGen/Record.cpp @@ -2598,7 +2598,7 @@ // We cache the record vectors for single classes. Many backends request // the same vectors multiple times. -std::vector RecordKeeper::getAllDerivedDefinitions( +ArrayRef RecordKeeper::getAllDerivedDefinitions( StringRef ClassName) const { auto Pair = ClassRecordsMap.try_emplace(ClassName); Index: llvm/utils/TableGen/AsmMatcherEmitter.cpp =================================================================== --- llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -1344,8 +1344,7 @@ } void AsmMatcherInfo::buildOperandClasses() { - std::vector AsmOperands = - Records.getAllDerivedDefinitions("AsmOperandClass"); + auto AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass"); // Pre-populate AsmOperandClasses map. for (Record *Rec : AsmOperands) { @@ -1530,8 +1529,7 @@ // Parse all of the InstAlias definitions and stick them in the list of // matchables. - std::vector AllInstAliases = - Records.getAllDerivedDefinitions("InstAlias"); + auto AllInstAliases = Records.getAllDerivedDefinitions("InstAlias"); for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { auto Alias = std::make_unique(AllInstAliases[i], Target); @@ -1639,8 +1637,7 @@ // Process token alias definitions and set up the associated superclass // information. - std::vector AllTokenAliases = - Records.getAllDerivedDefinitions("TokenAlias"); + auto AllTokenAliases = Records.getAllDerivedDefinitions("TokenAlias"); for (Record *Rec : AllTokenAliases) { ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken")); ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken")); @@ -2717,7 +2714,7 @@ } static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info, - std::vector &Aliases, + const std::vector &Aliases, unsigned Indent = 0, StringRef AsmParserVariantName = StringRef()){ // Keep track of all the aliases from a mnemonic. Use an std::map so that the @@ -2799,8 +2796,7 @@ if (!MatchPrefix.empty()) return false; - std::vector Aliases = - Info.getRecords().getAllDerivedDefinitions("MnemonicAlias"); + auto Aliases = Info.getRecords().getAllDerivedDefinitions("MnemonicAlias"); if (Aliases.empty()) return false; OS << "static void applyMnemonicAliases(StringRef &Mnemonic, " Index: llvm/utils/TableGen/AsmWriterEmitter.cpp =================================================================== --- llvm/utils/TableGen/AsmWriterEmitter.cpp +++ llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -816,8 +816,7 @@ unsigned Variant = AsmWriter->getValueAsInt("Variant"); bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); - std::vector AllInstAliases = - Records.getAllDerivedDefinitions("InstAlias"); + auto AllInstAliases = Records.getAllDerivedDefinitions("InstAlias"); // Create a map from the qualified name to a list of potential matches. typedef std::set, AliasPriorityComparator> Index: llvm/utils/TableGen/Attributes.cpp =================================================================== --- llvm/utils/TableGen/Attributes.cpp +++ llvm/utils/TableGen/Attributes.cpp @@ -69,8 +69,7 @@ << " const Function &Callee) {\n"; OS << " bool Ret = true;\n\n"; - std::vector CompatRules = - Records.getAllDerivedDefinitions("CompatRule"); + auto CompatRules = Records.getAllDerivedDefinitions("CompatRule"); for (auto *Rule : CompatRules) { StringRef FuncName = Rule->getValueAsString("CompatFunc"); @@ -81,8 +80,7 @@ OS << " return Ret;\n"; OS << "}\n\n"; - std::vector MergeRules = - Records.getAllDerivedDefinitions("MergeRule"); + auto MergeRules = Records.getAllDerivedDefinitions("MergeRule"); OS << "static inline void mergeFnAttrs(Function &Caller,\n" << " const Function &Callee) {\n"; Index: llvm/utils/TableGen/CallingConvEmitter.cpp =================================================================== --- llvm/utils/TableGen/CallingConvEmitter.cpp +++ llvm/utils/TableGen/CallingConvEmitter.cpp @@ -34,7 +34,7 @@ } // End anonymous namespace void CallingConvEmitter::run(raw_ostream &O) { - std::vector CCs = Records.getAllDerivedDefinitions("CallingConv"); + auto CCs = Records.getAllDerivedDefinitions("CallingConv"); // Emit prototypes for all of the non-custom CC's so that they can forward ref // each other. Index: llvm/utils/TableGen/CodeEmitterGen.cpp =================================================================== --- llvm/utils/TableGen/CodeEmitterGen.cpp +++ llvm/utils/TableGen/CodeEmitterGen.cpp @@ -388,7 +388,7 @@ void CodeEmitterGen::run(raw_ostream &o) { CodeGenTarget Target(Records); - std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); + auto Insts = Records.getAllDerivedDefinitions("Instruction"); // For little-endian instruction bit encodings, reverse the bit order Target.reverseBitsForLittleEndianEncoding(); @@ -461,9 +461,7 @@ std::map> CaseMap; // Construct all cases statement for each opcode - for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); - IC != EC; ++IC) { - Record *R = *IC; + for (auto R : Insts) { if (R->getValueAsString("Namespace") == "TargetOpcode" || R->getValueAsBit("isPseudo")) continue; Index: llvm/utils/TableGen/CodeGenDAGPatterns.cpp =================================================================== --- llvm/utils/TableGen/CodeGenDAGPatterns.cpp +++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp @@ -3098,7 +3098,8 @@ // Parse all of the SDNode definitions for the target, populating SDNodes. void CodeGenDAGPatterns::ParseNodeInfo() { - std::vector Nodes = Records.getAllDerivedDefinitions("SDNode"); + std::vector Nodes = // Copy the returned vector. + Records.getAllDerivedDefinitions("SDNode"); const CodeGenHwModes &CGH = getTargetInfo().getHwModes(); while (!Nodes.empty()) { @@ -3116,7 +3117,8 @@ /// ParseNodeTransforms - Parse all SDNodeXForm instances into the SDNodeXForms /// map, and emit them to the file as functions. void CodeGenDAGPatterns::ParseNodeTransforms() { - std::vector Xforms = Records.getAllDerivedDefinitions("SDNodeXForm"); + std::vector Xforms = // Copy the returned vector. + Records.getAllDerivedDefinitions("SDNodeXForm"); while (!Xforms.empty()) { Record *XFormNode = Xforms.back(); Record *SDNode = XFormNode->getValueAsDef("Opcode"); @@ -3129,7 +3131,8 @@ } void CodeGenDAGPatterns::ParseComplexPatterns() { - std::vector AMs = Records.getAllDerivedDefinitions("ComplexPattern"); + std::vector AMs = // Copy the returned vector. + Records.getAllDerivedDefinitions("ComplexPattern"); while (!AMs.empty()) { ComplexPatterns.insert(std::make_pair(AMs.back(), AMs.back())); AMs.pop_back(); @@ -3143,7 +3146,7 @@ /// inside a pattern fragment to a pattern fragment. /// void CodeGenDAGPatterns::ParsePatternFragments(bool OutFrags) { - std::vector Fragments = Records.getAllDerivedDefinitions("PatFrags"); + auto Fragments = Records.getAllDerivedDefinitions("PatFrags"); // First step, parse all of the fragments. for (Record *Frag : Fragments) { @@ -3231,8 +3234,7 @@ } void CodeGenDAGPatterns::ParseDefaultOperands() { - std::vector DefaultOps; - DefaultOps = Records.getAllDerivedDefinitions("OperandWithDefaultOps"); + auto DefaultOps = Records.getAllDerivedDefinitions("OperandWithDefaultOps"); // Find some SDNode. assert(!SDNodes.empty() && "No SDNodes parsed?"); @@ -3826,7 +3828,7 @@ /// any fragments involved. This populates the Instructions list with fully /// resolved instructions. void CodeGenDAGPatterns::ParseInstructions() { - std::vector Instrs = Records.getAllDerivedDefinitions("Instruction"); + auto Instrs = Records.getAllDerivedDefinitions("Instruction"); for (Record *Instr : Instrs) { ListInit *LI = nullptr; @@ -4235,7 +4237,7 @@ } void CodeGenDAGPatterns::ParsePatterns() { - std::vector Patterns = Records.getAllDerivedDefinitions("Pattern"); + auto Patterns = Records.getAllDerivedDefinitions("Pattern"); for (Record *CurPattern : Patterns) { DagInit *Tree = CurPattern->getValueAsDag("PatternToMatch"); Index: llvm/utils/TableGen/CodeGenHwModes.cpp =================================================================== --- llvm/utils/TableGen/CodeGenHwModes.cpp +++ llvm/utils/TableGen/CodeGenHwModes.cpp @@ -52,7 +52,12 @@ } CodeGenHwModes::CodeGenHwModes(RecordKeeper &RK) : Records(RK) { - std::vector MRs = Records.getAllDerivedDefinitions("HwMode"); + std::vector MRs = // Copy the returned vector. + Records.getAllDerivedDefinitions("HwMode"); + + // TODO: There is no reason to go through the HwMode vector and + // delete the default mode. Just skip it in the next loop below. + // The default mode needs a definition in the .td sources for TableGen // to accept references to it. We need to ignore the definition here. for (auto I = MRs.begin(), E = MRs.end(); I != E; ++I) { @@ -68,7 +73,7 @@ ModeIds.insert(std::make_pair(Modes[NewId-1].Name, NewId)); } - std::vector MSs = Records.getAllDerivedDefinitions("HwModeSelect"); + auto MSs = Records.getAllDerivedDefinitions("HwModeSelect"); for (Record *R : MSs) { auto P = ModeSelects.emplace(std::make_pair(R, HwModeSelect(R, *this))); assert(P.second); Index: mlir/tools/mlir-tblgen/OpInterfacesGen.cpp =================================================================== --- mlir/tools/mlir-tblgen/OpInterfacesGen.cpp +++ mlir/tools/mlir-tblgen/OpInterfacesGen.cpp @@ -59,7 +59,7 @@ /// "DeclareOpInterfaceMethods". static std::vector getAllOpInterfaceDefinitions(const llvm::RecordKeeper &recordKeeper) { - std::vector defs = + std::vector defs = // Copy the returned vector. recordKeeper.getAllDerivedDefinitions("OpInterface"); llvm::erase_if(defs, [](const llvm::Record *def) { @@ -77,8 +77,11 @@ bool emitInterfaceDocs(); protected: - InterfaceGenerator(std::vector &&defs, raw_ostream &os) - : defs(std::move(defs)), os(os) {} + + // TODO: Do we really need to copy the defs vector? + + InterfaceGenerator(const std::vector &defs, raw_ostream &os) + : defs(defs), os(os) {} // Copy the defs vector. void emitConceptDecl(Interface &interface); void emitModelDecl(Interface &interface); @@ -87,7 +90,7 @@ StringRef interfaceTraitsName); void emitInterfaceDecl(Interface interface); - /// The set of interface records to emit. + /// The set of interface records to emit. std::vector defs; // The stream to emit to. raw_ostream &os;