diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -592,8 +592,8 @@
   defm vse : RISCVUSStore;
   defm vlse: RISCVSLoad;
   defm vsse: RISCVSStore;
-  defm vlxe: RISCVILoad;
-  defm vsxe: RISCVIStore;
+  defm vloxe: RISCVILoad;
+  defm vsoxe: RISCVIStore;
   defm vsuxe: RISCVIStore;
 
   defm vamoswap : RISCVAMO;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -24,9 +24,10 @@
 class RISCVMOP<bits<2> val> {
   bits<2> Value = val;
 }
-def MOPLDUnitStride : RISCVMOP<0b00>;
-def MOPLDStrided    : RISCVMOP<0b10>;
-def MOPLDIndexed    : RISCVMOP<0b11>;
+def MOPLDUnitStride   : RISCVMOP<0b00>;
+def MOPLDIndexedUnord : RISCVMOP<0b01>;
+def MOPLDStrided      : RISCVMOP<0b10>;
+def MOPLDIndexedOrder : RISCVMOP<0b11>;
 
 def MOPSTUnitStride   : RISCVMOP<0b00>;
 def MOPSTIndexedUnord : RISCVMOP<0b01>;
@@ -242,7 +243,7 @@
   let RVVConstraint = VMConstraint;
 }
 
-class RVInstVLX<bits<3> nf, bit mew, bits<3> width,
+class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
@@ -252,7 +253,7 @@
 
   let Inst{31-29} = nf;
   let Inst{28} = mew;
-  let Inst{27-26} = MOPLDIndexed.Value;
+  let Inst{27-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -97,16 +97,16 @@
                 "$vd, (${rs1}), $rs2$vm">;
 
 // load vd, (rs1), vs2, vm
-class VIndexedLoad<RISCVWidth width, string opcodestr>
-    : RVInstVLX<0b000, width.Value{3}, width.Value{2-0},
+class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0},
                 (outs VR:$vd),
                 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
                 "$vd, (${rs1}), $vs2$vm">;
 
 // vl<nf>r.v vd, (rs1)
-class VWholeLoad<bits<3> nf, string opcodestr>
-    : RVInstVLU<nf, 0b0, LUMOPUnitStrideWholeReg,
-                0b000, (outs VR:$vd), (ins GPR:$rs1),
+class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr>
+    : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg,
+                width.Value{2-0}, (outs VR:$vd), (ins GPR:$rs1),
                 opcodestr, "$vd, (${rs1})"> {
   let vm = 1;
   let Uses = [];
@@ -128,8 +128,9 @@
                 "$vd, (${rs1}), $rs2$vm">;
 
 // segment load vd, (rs1), vs2, vm
-class VIndexedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
-    : RVInstVLX<nf, width.Value{3}, width.Value{2-0},
+class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                          string opcodestr>
+    : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0},
                 (outs VR:$vd),
                 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
                 "$vd, (${rs1}), $vs2$vm">;
@@ -157,7 +158,7 @@
 
 // vs<nf>r.v vd, (rs1)
 class VWholeStore<bits<3> nf, string opcodestr>
-    : RVInstVSU<nf, 0b0, SUMOPUnitStrideWholeReg,
+    : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg,
                 0b000, (outs), (ins VR:$vs3, GPR:$rs1),
                 opcodestr, "$vs3, (${rs1})"> {
   let vm = 1;
@@ -177,8 +178,9 @@
                 opcodestr, "$vs3, (${rs1}), $rs2$vm">;
 
 // segment store vd, vs3, (rs1), vs2, vm
-class VIndexedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
-    : RVInstVSX<nf, width.Value{3}, MOPSTIndexedOrder, width.Value{2-0}, (outs),
+class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                           string opcodestr>
+    : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
                 (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
                 opcodestr, "$vs3, (${rs1}), $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 1
@@ -416,6 +418,17 @@
   def _UNWD : VAMONoWd<amoop, width, opcodestr>;
 }
 
+multiclass VWholeLoad<bits<3> nf, string opcodestr> {
+  def E8_V : VWholeLoad<nf, LSWidth8, opcodestr # "e8.v">;
+  def E16_V : VWholeLoad<nf, LSWidth16, opcodestr # "e16.v">;
+  def E32_V : VWholeLoad<nf, LSWidth32, opcodestr # "e32.v">;
+  def E64_V : VWholeLoad<nf, LSWidth64, opcodestr # "e64.v">;
+  def E128_V : VWholeLoad<nf, LSWidth128, opcodestr # "e128.v">;
+  def E256_V : VWholeLoad<nf, LSWidth256, opcodestr # "e256.v">;
+  def E512_V : VWholeLoad<nf, LSWidth512, opcodestr # "e512.v">;
+  def E1024_V : VWholeLoad<nf, LSWidth1024, opcodestr # "e1024.v">;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
@@ -477,35 +490,39 @@
 def VSSE1024_V : VStridedStore<LSWidth1024, "vsse1024.v">;
 
 // Vector Indexed Instructions
-def VLXEI8_V : VIndexedLoad<LSWidth8, "vlxei8.v">;
-def VLXEI16_V : VIndexedLoad<LSWidth16, "vlxei16.v">;
-def VLXEI32_V : VIndexedLoad<LSWidth32, "vlxei32.v">;
-def VLXEI64_V : VIndexedLoad<LSWidth64, "vlxei64.v">;
-def VLXEI128_V : VIndexedLoad<LSWidth128, "vlxei128.v">;
-def VLXEI256_V : VIndexedLoad<LSWidth256, "vlxei256.v">;
-def VLXEI512_V : VIndexedLoad<LSWidth512, "vlxei512.v">;
-def VLXEI1024_V : VIndexedLoad<LSWidth1024, "vlxei1024.v">;
-
-def VSXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsxei8.v">;
-def VSXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsxei16.v">;
-def VSXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsxei32.v">;
-def VSXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsxei64.v">;
-def VSXEI128_V : VIndexedStore<MOPSTIndexedOrder, LSWidth128, "vsxei128.v">;
-def VSXEI256_V : VIndexedStore<MOPSTIndexedOrder, LSWidth256, "vsxei256.v">;
-def VSXEI512_V : VIndexedStore<MOPSTIndexedOrder, LSWidth512, "vsxei512.v">;
-def VSXEI1024_V : VIndexedStore<MOPSTIndexedOrder, LSWidth1024, "vsxei1024.v">;
+def VLUXEI8_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth8, "vluxei8.v">;
+def VLUXEI16_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth16, "vluxei16.v">;
+def VLUXEI32_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth32, "vluxei32.v">;
+def VLUXEI64_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth64, "vluxei64.v">;
+
+def VLOXEI8_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth8, "vloxei8.v">;
+def VLOXEI16_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth16, "vloxei16.v">;
+def VLOXEI32_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth32, "vloxei32.v">;
+def VLOXEI64_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth64, "vloxei64.v">;
 
 def VSUXEI8_V : VIndexedStore<MOPSTIndexedUnord, LSWidth8, "vsuxei8.v">;
 def VSUXEI16_V : VIndexedStore<MOPSTIndexedUnord, LSWidth16, "vsuxei16.v">;
 def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">;
 def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">;
-def VSUXEI128_V : VIndexedStore<MOPSTIndexedUnord, LSWidth128, "vsuxei128.v">;
-def VSUXEI256_V : VIndexedStore<MOPSTIndexedUnord, LSWidth256, "vsuxei256.v">;
-def VSUXEI512_V : VIndexedStore<MOPSTIndexedUnord, LSWidth512, "vsuxei512.v">;
-def VSUXEI1024_V : VIndexedStore<MOPSTIndexedUnord, LSWidth1024, "vsuxei1024.v">;
 
-def VL1R_V : VWholeLoad<0, "vl1r.v">;
-def VS1R_V : VWholeStore<0, "vs1r.v">;
+def VSOXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsoxei8.v">;
+def VSOXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsoxei16.v">;
+def VSOXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsoxei32.v">;
+def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">;
+
+defm VL1R : VWholeLoad<1, "vl1r">;
+defm VL2R : VWholeLoad<2, "vl2r">;
+defm VL4R : VWholeLoad<4, "vl4r">;
+defm VL8R : VWholeLoad<8, "vl8r">;
+def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
+def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VR:$vd, GPR:$rs1)>;
+def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VR:$vd, GPR:$rs1)>;
+def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VR:$vd, GPR:$rs1)>;
+
+def VS1R_V : VWholeStore<1, "vs1r.v">;
+def VS2R_V : VWholeStore<2, "vs2r.v">;
+def VS4R_V : VWholeStore<4, "vs4r.v">;
+def VS8R_V : VWholeStore<8, "vs8r.v">;
 
 // Vector Single-Width Integer Add and Subtract
 defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
@@ -1090,23 +1107,73 @@
     def VSSSEG#nf#E1024_V : VStridedSegmentStore<!add(nf, -1), LSWidth1024, "vssseg"#nf#"e1024.v">;
 
     // Vector Indexed Instructions
-    def VLXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth8, "vlxseg"#nf#"ei8.v">;
-    def VLXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth16, "vlxseg"#nf#"ei16.v">;
-    def VLXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth32, "vlxseg"#nf#"ei32.v">;
-    def VLXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth64, "vlxseg"#nf#"ei64.v">;
-    def VLXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth128, "vlxseg"#nf#"ei128.v">;
-    def VLXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth256, "vlxseg"#nf#"ei256.v">;
-    def VLXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth512, "vlxseg"#nf#"ei512.v">;
-    def VLXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth1024, "vlxseg"#nf#"ei1024.v">;
-
-    def VSXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), LSWidth8, "vsxseg"#nf#"ei8.v">;
-    def VSXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), LSWidth16, "vsxseg"#nf#"ei16.v">;
-    def VSXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), LSWidth32, "vsxseg"#nf#"ei32.v">;
-    def VSXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), LSWidth64, "vsxseg"#nf#"ei64.v">;
-    def VSXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), LSWidth128, "vsxseg"#nf#"ei128.v">;
-    def VSXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), LSWidth256, "vsxseg"#nf#"ei256.v">;
-    def VSXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), LSWidth512, "vsxseg"#nf#"ei512.v">;
-    def VSXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), LSWidth1024, "vsxseg"#nf#"ei1024.v">;
+    def VLUXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                             LSWidth8, "vluxseg"#nf#"ei8.v">;
+    def VLUXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                              LSWidth16, "vluxseg"#nf#"ei16.v">;
+    def VLUXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                              LSWidth32, "vluxseg"#nf#"ei32.v">;
+    def VLUXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                              LSWidth64, "vluxseg"#nf#"ei64.v">;
+    def VLUXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                               LSWidth128, "vluxseg"#nf#"ei128.v">;
+    def VLUXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                               LSWidth256, "vluxseg"#nf#"ei256.v">;
+    def VLUXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                               LSWidth512, "vluxseg"#nf#"ei512.v">;
+    def VLUXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                               LSWidth1024, "vluxseg"#nf#"ei1024.v">;
+
+    def VLOXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                             LSWidth8, "vloxseg"#nf#"ei8.v">;
+    def VLOXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                              LSWidth16, "vloxseg"#nf#"ei16.v">;
+    def VLOXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                              LSWidth32, "vloxseg"#nf#"ei32.v">;
+    def VLOXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                              LSWidth64, "vloxseg"#nf#"ei64.v">;
+    def VLOXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                               LSWidth128, "vloxseg"#nf#"ei128.v">;
+    def VLOXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                               LSWidth256, "vloxseg"#nf#"ei256.v">;
+    def VLOXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                               LSWidth512, "vloxseg"#nf#"ei512.v">;
+    def VLOXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                               LSWidth1024, "vloxseg"#nf#"ei1024.v">;
+
+    def VSUXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                             LSWidth8, "vsuxseg"#nf#"ei8.v">;
+    def VSUXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                              LSWidth16, "vsuxseg"#nf#"ei16.v">;
+    def VSUXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                              LSWidth32, "vsuxseg"#nf#"ei32.v">;
+    def VSUXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                              LSWidth64, "vsuxseg"#nf#"ei64.v">;
+    def VSUXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                               LSWidth128, "vsuxseg"#nf#"ei128.v">;
+    def VSUXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                               LSWidth256, "vsuxseg"#nf#"ei256.v">;
+    def VSUXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                               LSWidth512, "vsuxseg"#nf#"ei512.v">;
+    def VSUXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                                LSWidth1024, "vsuxseg"#nf#"ei1024.v">;
+
+    def VSOXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                             LSWidth8, "vsoxseg"#nf#"ei8.v">;
+    def VSOXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                              LSWidth16, "vsoxseg"#nf#"ei16.v">;
+    def VSOXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                              LSWidth32, "vsoxseg"#nf#"ei32.v">;
+    def VSOXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                              LSWidth64, "vsoxseg"#nf#"ei64.v">;
+    def VSOXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                               LSWidth128, "vsoxseg"#nf#"ei128.v">;
+    def VSOXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                               LSWidth256, "vsoxseg"#nf#"ei256.v">;
+    def VSOXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                               LSWidth512, "vsoxseg"#nf#"ei512.v">;
+    def VSOXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                                LSWidth1024, "vsoxseg"#nf#"ei1024.v">;
   }
 } // Predicates = [HasStdExtZvlsseg]
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2617,8 +2617,8 @@
 
 // Vector Indexed Loads and Stores
 foreach eew = EEWList in {
-  defm PseudoVLXEI # eew : VPseudoILoad;
-  defm PseudoVSXEI # eew : VPseudoIStore;
+  defm PseudoVLOXEI # eew : VPseudoILoad;
+  defm PseudoVSOXEI # eew : VPseudoIStore;
   defm PseudoVSUXEI # eew : VPseudoIStore;
 }
 
@@ -3182,12 +3182,12 @@
        defvar elmul =!cast<LMULInfo>("V_" # elmul_str);
        defvar idx_vti = !cast<VTypeInfo>("VI" # eew # elmul_str);
 
-       defm : VPatILoad<"int_riscv_vlxe",
-                        "PseudoVLXEI"#eew,
+       defm : VPatILoad<"int_riscv_vloxe",
+                        "PseudoVLOXEI"#eew,
                          vti.Vector, idx_vti.Vector, vti.Mask, vti.SEW,
                          vlmul, elmul, vti.RegClass, idx_vti.RegClass>;
-       defm : VPatIStore<"int_riscv_vsxe",
-                          "PseudoVSXEI"#eew,
+       defm : VPatIStore<"int_riscv_vsoxe",
+                          "PseudoVSOXEI"#eew,
                           vti.Vector, idx_vti.Vector, vti.Mask, vti.SEW,
                           vlmul, elmul, vti.RegClass, idx_vti.RegClass>;
        defm : VPatIStore<"int_riscv_vsuxe",
diff --git a/llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll
@@ -1,16 +1,16 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh,+f,+d -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vlxe.nxv1i8.nxv1i32(
+declare <vscale x 1 x i8> @llvm.riscv.vloxe.nxv1i8.nxv1i32(
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   i32);
 
-define <vscale x 1 x i8> @intrinsic_vlxe_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vloxe_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i8_nxv1i8_nxv1i32
+; CHECK-LABEL: intrinsic_vloxe_v_nxv1i8_nxv1i8_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i8> @llvm.riscv.vlxe.nxv1i8.nxv1i32(
+; CHECK:       vloxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vloxe.nxv1i8.nxv1i32(
     <vscale x 1 x i8>* %0,
     <vscale x 1 x i32> %1,
     i32 %2)
@@ -18,19 +18,19 @@
   ret <vscale x 1 x i8> %a
 }
 
-declare <vscale x 1 x i8> @llvm.riscv.vlxe.mask.nxv1i8.nxv1i32(
+declare <vscale x 1 x i8> @llvm.riscv.vloxe.mask.nxv1i8.nxv1i32(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i32);
 
-define <vscale x 1 x i8> @intrinsic_vlxe_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vloxe_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i8_nxv1i8_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i8> @llvm.riscv.vlxe.mask.nxv1i8.nxv1i32(
+; CHECK-LABEL: intrinsic_vloxe_mask_v_nxv1i8_nxv1i8_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vloxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vloxe.mask.nxv1i8.nxv1i32(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i32> %2,
@@ -39,3243 +39,3 @@
 
   ret <vscale x 1 x i8> %a
 }
-
-declare <vscale x 2 x i8> @llvm.riscv.vlxe.nxv2i8.nxv2i32(
-  <vscale x 2 x i8>*,
-  <vscale x 2 x i32>,
-  i32);
-
-define <vscale x 2 x i8> @intrinsic_vlxe_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i8_nxv2i8_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i8> @llvm.riscv.vlxe.nxv2i8.nxv2i32(
-    <vscale x 2 x i8>* %0,
-    <vscale x 2 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vlxe.mask.nxv2i8.nxv2i32(
-  <vscale x 2 x i8>,
-  <vscale x 2 x i8>*,
-  <vscale x 2 x i32>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i8> @intrinsic_vlxe_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i8_nxv2i8_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i8> @llvm.riscv.vlxe.mask.nxv2i8.nxv2i32(
-    <vscale x 2 x i8> %0,
-    <vscale x 2 x i8>* %1,
-    <vscale x 2 x i32> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vlxe.nxv4i8.nxv4i32(
-  <vscale x 4 x i8>*,
-  <vscale x 4 x i32>,
-  i32);
-
-define <vscale x 4 x i8> @intrinsic_vlxe_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i8_nxv4i8_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i8> @llvm.riscv.vlxe.nxv4i8.nxv4i32(
-    <vscale x 4 x i8>* %0,
-    <vscale x 4 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vlxe.mask.nxv4i8.nxv4i32(
-  <vscale x 4 x i8>,
-  <vscale x 4 x i8>*,
-  <vscale x 4 x i32>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i8> @intrinsic_vlxe_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i8_nxv4i8_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i8> @llvm.riscv.vlxe.mask.nxv4i8.nxv4i32(
-    <vscale x 4 x i8> %0,
-    <vscale x 4 x i8>* %1,
-    <vscale x 4 x i32> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vlxe.nxv8i8.nxv8i32(
-  <vscale x 8 x i8>*,
-  <vscale x 8 x i32>,
-  i32);
-
-define <vscale x 8 x i8> @intrinsic_vlxe_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i8_nxv8i8_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i8> @llvm.riscv.vlxe.nxv8i8.nxv8i32(
-    <vscale x 8 x i8>* %0,
-    <vscale x 8 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vlxe.mask.nxv8i8.nxv8i32(
-  <vscale x 8 x i8>,
-  <vscale x 8 x i8>*,
-  <vscale x 8 x i32>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i8> @intrinsic_vlxe_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i8_nxv8i8_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i8> @llvm.riscv.vlxe.mask.nxv8i8.nxv8i32(
-    <vscale x 8 x i8> %0,
-    <vscale x 8 x i8>* %1,
-    <vscale x 8 x i32> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vlxe.nxv16i8.nxv16i32(
-  <vscale x 16 x i8>*,
-  <vscale x 16 x i32>,
-  i32);
-
-define <vscale x 16 x i8> @intrinsic_vlxe_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i8_nxv16i8_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i8> @llvm.riscv.vlxe.nxv16i8.nxv16i32(
-    <vscale x 16 x i8>* %0,
-    <vscale x 16 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vlxe.mask.nxv16i8.nxv16i32(
-  <vscale x 16 x i8>,
-  <vscale x 16 x i8>*,
-  <vscale x 16 x i32>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i8> @intrinsic_vlxe_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i8_nxv16i8_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i8> @llvm.riscv.vlxe.mask.nxv16i8.nxv16i32(
-    <vscale x 16 x i8> %0,
-    <vscale x 16 x i8>* %1,
-    <vscale x 16 x i32> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vlxe.nxv1i16.nxv1i32(
-  <vscale x 1 x i16>*,
-  <vscale x 1 x i32>,
-  i32);
-
-define <vscale x 1 x i16> @intrinsic_vlxe_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i16_nxv1i16_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i16> @llvm.riscv.vlxe.nxv1i16.nxv1i32(
-    <vscale x 1 x i16>* %0,
-    <vscale x 1 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vlxe.mask.nxv1i16.nxv1i32(
-  <vscale x 1 x i16>,
-  <vscale x 1 x i16>*,
-  <vscale x 1 x i32>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x i16> @intrinsic_vlxe_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i16_nxv1i16_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i16> @llvm.riscv.vlxe.mask.nxv1i16.nxv1i32(
-    <vscale x 1 x i16> %0,
-    <vscale x 1 x i16>* %1,
-    <vscale x 1 x i32> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vlxe.nxv2i16.nxv2i32(
-  <vscale x 2 x i16>*,
-  <vscale x 2 x i32>,
-  i32);
-
-define <vscale x 2 x i16> @intrinsic_vlxe_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i16_nxv2i16_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i16> @llvm.riscv.vlxe.nxv2i16.nxv2i32(
-    <vscale x 2 x i16>* %0,
-    <vscale x 2 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vlxe.mask.nxv2i16.nxv2i32(
-  <vscale x 2 x i16>,
-  <vscale x 2 x i16>*,
-  <vscale x 2 x i32>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i16> @intrinsic_vlxe_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i16_nxv2i16_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i16> @llvm.riscv.vlxe.mask.nxv2i16.nxv2i32(
-    <vscale x 2 x i16> %0,
-    <vscale x 2 x i16>* %1,
-    <vscale x 2 x i32> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vlxe.nxv4i16.nxv4i32(
-  <vscale x 4 x i16>*,
-  <vscale x 4 x i32>,
-  i32);
-
-define <vscale x 4 x i16> @intrinsic_vlxe_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i16_nxv4i16_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i16> @llvm.riscv.vlxe.nxv4i16.nxv4i32(
-    <vscale x 4 x i16>* %0,
-    <vscale x 4 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vlxe.mask.nxv4i16.nxv4i32(
-  <vscale x 4 x i16>,
-  <vscale x 4 x i16>*,
-  <vscale x 4 x i32>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i16> @intrinsic_vlxe_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i16_nxv4i16_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i16> @llvm.riscv.vlxe.mask.nxv4i16.nxv4i32(
-    <vscale x 4 x i16> %0,
-    <vscale x 4 x i16>* %1,
-    <vscale x 4 x i32> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vlxe.nxv8i16.nxv8i32(
-  <vscale x 8 x i16>*,
-  <vscale x 8 x i32>,
-  i32);
-
-define <vscale x 8 x i16> @intrinsic_vlxe_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i16_nxv8i16_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i16> @llvm.riscv.vlxe.nxv8i16.nxv8i32(
-    <vscale x 8 x i16>* %0,
-    <vscale x 8 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vlxe.mask.nxv8i16.nxv8i32(
-  <vscale x 8 x i16>,
-  <vscale x 8 x i16>*,
-  <vscale x 8 x i32>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i16> @intrinsic_vlxe_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i16_nxv8i16_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i16> @llvm.riscv.vlxe.mask.nxv8i16.nxv8i32(
-    <vscale x 8 x i16> %0,
-    <vscale x 8 x i16>* %1,
-    <vscale x 8 x i32> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vlxe.nxv16i16.nxv16i32(
-  <vscale x 16 x i16>*,
-  <vscale x 16 x i32>,
-  i32);
-
-define <vscale x 16 x i16> @intrinsic_vlxe_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i16_nxv16i16_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i16> @llvm.riscv.vlxe.nxv16i16.nxv16i32(
-    <vscale x 16 x i16>* %0,
-    <vscale x 16 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vlxe.mask.nxv16i16.nxv16i32(
-  <vscale x 16 x i16>,
-  <vscale x 16 x i16>*,
-  <vscale x 16 x i32>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i16> @intrinsic_vlxe_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i16_nxv16i16_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i16> @llvm.riscv.vlxe.mask.nxv16i16.nxv16i32(
-    <vscale x 16 x i16> %0,
-    <vscale x 16 x i16>* %1,
-    <vscale x 16 x i32> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vlxe.nxv1i32.nxv1i32(
-  <vscale x 1 x i32>*,
-  <vscale x 1 x i32>,
-  i32);
-
-define <vscale x 1 x i32> @intrinsic_vlxe_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i32_nxv1i32_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i32> @llvm.riscv.vlxe.nxv1i32.nxv1i32(
-    <vscale x 1 x i32>* %0,
-    <vscale x 1 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vlxe.mask.nxv1i32.nxv1i32(
-  <vscale x 1 x i32>,
-  <vscale x 1 x i32>*,
-  <vscale x 1 x i32>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x i32> @intrinsic_vlxe_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i32_nxv1i32_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i32> @llvm.riscv.vlxe.mask.nxv1i32.nxv1i32(
-    <vscale x 1 x i32> %0,
-    <vscale x 1 x i32>* %1,
-    <vscale x 1 x i32> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vlxe.nxv2i32.nxv2i32(
-  <vscale x 2 x i32>*,
-  <vscale x 2 x i32>,
-  i32);
-
-define <vscale x 2 x i32> @intrinsic_vlxe_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i32_nxv2i32_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i32> @llvm.riscv.vlxe.nxv2i32.nxv2i32(
-    <vscale x 2 x i32>* %0,
-    <vscale x 2 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vlxe.mask.nxv2i32.nxv2i32(
-  <vscale x 2 x i32>,
-  <vscale x 2 x i32>*,
-  <vscale x 2 x i32>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i32> @intrinsic_vlxe_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i32_nxv2i32_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i32> @llvm.riscv.vlxe.mask.nxv2i32.nxv2i32(
-    <vscale x 2 x i32> %0,
-    <vscale x 2 x i32>* %1,
-    <vscale x 2 x i32> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vlxe.nxv4i32.nxv4i32(
-  <vscale x 4 x i32>*,
-  <vscale x 4 x i32>,
-  i32);
-
-define <vscale x 4 x i32> @intrinsic_vlxe_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i32_nxv4i32_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i32> @llvm.riscv.vlxe.nxv4i32.nxv4i32(
-    <vscale x 4 x i32>* %0,
-    <vscale x 4 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vlxe.mask.nxv4i32.nxv4i32(
-  <vscale x 4 x i32>,
-  <vscale x 4 x i32>*,
-  <vscale x 4 x i32>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i32> @intrinsic_vlxe_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i32_nxv4i32_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i32> @llvm.riscv.vlxe.mask.nxv4i32.nxv4i32(
-    <vscale x 4 x i32> %0,
-    <vscale x 4 x i32>* %1,
-    <vscale x 4 x i32> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vlxe.nxv8i32.nxv8i32(
-  <vscale x 8 x i32>*,
-  <vscale x 8 x i32>,
-  i32);
-
-define <vscale x 8 x i32> @intrinsic_vlxe_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i32_nxv8i32_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i32> @llvm.riscv.vlxe.nxv8i32.nxv8i32(
-    <vscale x 8 x i32>* %0,
-    <vscale x 8 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vlxe.mask.nxv8i32.nxv8i32(
-  <vscale x 8 x i32>,
-  <vscale x 8 x i32>*,
-  <vscale x 8 x i32>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i32> @intrinsic_vlxe_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i32_nxv8i32_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i32> @llvm.riscv.vlxe.mask.nxv8i32.nxv8i32(
-    <vscale x 8 x i32> %0,
-    <vscale x 8 x i32>* %1,
-    <vscale x 8 x i32> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vlxe.nxv16i32.nxv16i32(
-  <vscale x 16 x i32>*,
-  <vscale x 16 x i32>,
-  i32);
-
-define <vscale x 16 x i32> @intrinsic_vlxe_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i32_nxv16i32_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i32> @llvm.riscv.vlxe.nxv16i32.nxv16i32(
-    <vscale x 16 x i32>* %0,
-    <vscale x 16 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vlxe.mask.nxv16i32.nxv16i32(
-  <vscale x 16 x i32>,
-  <vscale x 16 x i32>*,
-  <vscale x 16 x i32>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i32> @intrinsic_vlxe_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i32_nxv16i32_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i32> @llvm.riscv.vlxe.mask.nxv16i32.nxv16i32(
-    <vscale x 16 x i32> %0,
-    <vscale x 16 x i32>* %1,
-    <vscale x 16 x i32> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x half> @llvm.riscv.vlxe.nxv1f16.nxv1i32(
-  <vscale x 1 x half>*,
-  <vscale x 1 x i32>,
-  i32);
-
-define <vscale x 1 x half> @intrinsic_vlxe_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1f16_nxv1f16_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x half> @llvm.riscv.vlxe.nxv1f16.nxv1i32(
-    <vscale x 1 x half>* %0,
-    <vscale x 1 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 1 x half> %a
-}
-
-declare <vscale x 1 x half> @llvm.riscv.vlxe.mask.nxv1f16.nxv1i32(
-  <vscale x 1 x half>,
-  <vscale x 1 x half>*,
-  <vscale x 1 x i32>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x half> @intrinsic_vlxe_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1f16_nxv1f16_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x half> @llvm.riscv.vlxe.mask.nxv1f16.nxv1i32(
-    <vscale x 1 x half> %0,
-    <vscale x 1 x half>* %1,
-    <vscale x 1 x i32> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x half> %a
-}
-
-declare <vscale x 2 x half> @llvm.riscv.vlxe.nxv2f16.nxv2i32(
-  <vscale x 2 x half>*,
-  <vscale x 2 x i32>,
-  i32);
-
-define <vscale x 2 x half> @intrinsic_vlxe_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2f16_nxv2f16_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x half> @llvm.riscv.vlxe.nxv2f16.nxv2i32(
-    <vscale x 2 x half>* %0,
-    <vscale x 2 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 2 x half> %a
-}
-
-declare <vscale x 2 x half> @llvm.riscv.vlxe.mask.nxv2f16.nxv2i32(
-  <vscale x 2 x half>,
-  <vscale x 2 x half>*,
-  <vscale x 2 x i32>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x half> @intrinsic_vlxe_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2f16_nxv2f16_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x half> @llvm.riscv.vlxe.mask.nxv2f16.nxv2i32(
-    <vscale x 2 x half> %0,
-    <vscale x 2 x half>* %1,
-    <vscale x 2 x i32> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x half> %a
-}
-
-declare <vscale x 4 x half> @llvm.riscv.vlxe.nxv4f16.nxv4i32(
-  <vscale x 4 x half>*,
-  <vscale x 4 x i32>,
-  i32);
-
-define <vscale x 4 x half> @intrinsic_vlxe_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4f16_nxv4f16_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x half> @llvm.riscv.vlxe.nxv4f16.nxv4i32(
-    <vscale x 4 x half>* %0,
-    <vscale x 4 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 4 x half> %a
-}
-
-declare <vscale x 4 x half> @llvm.riscv.vlxe.mask.nxv4f16.nxv4i32(
-  <vscale x 4 x half>,
-  <vscale x 4 x half>*,
-  <vscale x 4 x i32>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x half> @intrinsic_vlxe_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4f16_nxv4f16_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x half> @llvm.riscv.vlxe.mask.nxv4f16.nxv4i32(
-    <vscale x 4 x half> %0,
-    <vscale x 4 x half>* %1,
-    <vscale x 4 x i32> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x half> %a
-}
-
-declare <vscale x 8 x half> @llvm.riscv.vlxe.nxv8f16.nxv8i32(
-  <vscale x 8 x half>*,
-  <vscale x 8 x i32>,
-  i32);
-
-define <vscale x 8 x half> @intrinsic_vlxe_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8f16_nxv8f16_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x half> @llvm.riscv.vlxe.nxv8f16.nxv8i32(
-    <vscale x 8 x half>* %0,
-    <vscale x 8 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 8 x half> %a
-}
-
-declare <vscale x 8 x half> @llvm.riscv.vlxe.mask.nxv8f16.nxv8i32(
-  <vscale x 8 x half>,
-  <vscale x 8 x half>*,
-  <vscale x 8 x i32>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x half> @intrinsic_vlxe_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8f16_nxv8f16_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x half> @llvm.riscv.vlxe.mask.nxv8f16.nxv8i32(
-    <vscale x 8 x half> %0,
-    <vscale x 8 x half>* %1,
-    <vscale x 8 x i32> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x half> %a
-}
-
-declare <vscale x 16 x half> @llvm.riscv.vlxe.nxv16f16.nxv16i32(
-  <vscale x 16 x half>*,
-  <vscale x 16 x i32>,
-  i32);
-
-define <vscale x 16 x half> @intrinsic_vlxe_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16f16_nxv16f16_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x half> @llvm.riscv.vlxe.nxv16f16.nxv16i32(
-    <vscale x 16 x half>* %0,
-    <vscale x 16 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 16 x half> %a
-}
-
-declare <vscale x 16 x half> @llvm.riscv.vlxe.mask.nxv16f16.nxv16i32(
-  <vscale x 16 x half>,
-  <vscale x 16 x half>*,
-  <vscale x 16 x i32>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x half> @intrinsic_vlxe_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16f16_nxv16f16_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x half> @llvm.riscv.vlxe.mask.nxv16f16.nxv16i32(
-    <vscale x 16 x half> %0,
-    <vscale x 16 x half>* %1,
-    <vscale x 16 x i32> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x half> %a
-}
-
-declare <vscale x 1 x float> @llvm.riscv.vlxe.nxv1f32.nxv1i32(
-  <vscale x 1 x float>*,
-  <vscale x 1 x i32>,
-  i32);
-
-define <vscale x 1 x float> @intrinsic_vlxe_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float>* %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1f32_nxv1f32_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x float> @llvm.riscv.vlxe.nxv1f32.nxv1i32(
-    <vscale x 1 x float>* %0,
-    <vscale x 1 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 1 x float> %a
-}
-
-declare <vscale x 1 x float> @llvm.riscv.vlxe.mask.nxv1f32.nxv1i32(
-  <vscale x 1 x float>,
-  <vscale x 1 x float>*,
-  <vscale x 1 x i32>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x float> @intrinsic_vlxe_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1f32_nxv1f32_nxv1i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x float> @llvm.riscv.vlxe.mask.nxv1f32.nxv1i32(
-    <vscale x 1 x float> %0,
-    <vscale x 1 x float>* %1,
-    <vscale x 1 x i32> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x float> %a
-}
-
-declare <vscale x 2 x float> @llvm.riscv.vlxe.nxv2f32.nxv2i32(
-  <vscale x 2 x float>*,
-  <vscale x 2 x i32>,
-  i32);
-
-define <vscale x 2 x float> @intrinsic_vlxe_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float>* %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2f32_nxv2f32_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x float> @llvm.riscv.vlxe.nxv2f32.nxv2i32(
-    <vscale x 2 x float>* %0,
-    <vscale x 2 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 2 x float> %a
-}
-
-declare <vscale x 2 x float> @llvm.riscv.vlxe.mask.nxv2f32.nxv2i32(
-  <vscale x 2 x float>,
-  <vscale x 2 x float>*,
-  <vscale x 2 x i32>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x float> @intrinsic_vlxe_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2f32_nxv2f32_nxv2i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x float> @llvm.riscv.vlxe.mask.nxv2f32.nxv2i32(
-    <vscale x 2 x float> %0,
-    <vscale x 2 x float>* %1,
-    <vscale x 2 x i32> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x float> %a
-}
-
-declare <vscale x 4 x float> @llvm.riscv.vlxe.nxv4f32.nxv4i32(
-  <vscale x 4 x float>*,
-  <vscale x 4 x i32>,
-  i32);
-
-define <vscale x 4 x float> @intrinsic_vlxe_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float>* %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4f32_nxv4f32_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x float> @llvm.riscv.vlxe.nxv4f32.nxv4i32(
-    <vscale x 4 x float>* %0,
-    <vscale x 4 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 4 x float> %a
-}
-
-declare <vscale x 4 x float> @llvm.riscv.vlxe.mask.nxv4f32.nxv4i32(
-  <vscale x 4 x float>,
-  <vscale x 4 x float>*,
-  <vscale x 4 x i32>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x float> @intrinsic_vlxe_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4f32_nxv4f32_nxv4i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x float> @llvm.riscv.vlxe.mask.nxv4f32.nxv4i32(
-    <vscale x 4 x float> %0,
-    <vscale x 4 x float>* %1,
-    <vscale x 4 x i32> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x float> %a
-}
-
-declare <vscale x 8 x float> @llvm.riscv.vlxe.nxv8f32.nxv8i32(
-  <vscale x 8 x float>*,
-  <vscale x 8 x i32>,
-  i32);
-
-define <vscale x 8 x float> @intrinsic_vlxe_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float>* %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8f32_nxv8f32_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x float> @llvm.riscv.vlxe.nxv8f32.nxv8i32(
-    <vscale x 8 x float>* %0,
-    <vscale x 8 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 8 x float> %a
-}
-
-declare <vscale x 8 x float> @llvm.riscv.vlxe.mask.nxv8f32.nxv8i32(
-  <vscale x 8 x float>,
-  <vscale x 8 x float>*,
-  <vscale x 8 x i32>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x float> @intrinsic_vlxe_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8f32_nxv8f32_nxv8i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x float> @llvm.riscv.vlxe.mask.nxv8f32.nxv8i32(
-    <vscale x 8 x float> %0,
-    <vscale x 8 x float>* %1,
-    <vscale x 8 x i32> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x float> %a
-}
-
-declare <vscale x 16 x float> @llvm.riscv.vlxe.nxv16f32.nxv16i32(
-  <vscale x 16 x float>*,
-  <vscale x 16 x i32>,
-  i32);
-
-define <vscale x 16 x float> @intrinsic_vlxe_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float>* %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16f32_nxv16f32_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x float> @llvm.riscv.vlxe.nxv16f32.nxv16i32(
-    <vscale x 16 x float>* %0,
-    <vscale x 16 x i32> %1,
-    i32 %2)
-
-  ret <vscale x 16 x float> %a
-}
-
-declare <vscale x 16 x float> @llvm.riscv.vlxe.mask.nxv16f32.nxv16i32(
-  <vscale x 16 x float>,
-  <vscale x 16 x float>*,
-  <vscale x 16 x i32>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x float> @intrinsic_vlxe_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16f32_nxv16f32_nxv16i32
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vlxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x float> @llvm.riscv.vlxe.mask.nxv16f32.nxv16i32(
-    <vscale x 16 x float> %0,
-    <vscale x 16 x float>* %1,
-    <vscale x 16 x i32> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x float> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vlxe.nxv1i8.nxv1i16(
-  <vscale x 1 x i8>*,
-  <vscale x 1 x i16>,
-  i32);
-
-define <vscale x 1 x i8> @intrinsic_vlxe_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i8_nxv1i8_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i8> @llvm.riscv.vlxe.nxv1i8.nxv1i16(
-    <vscale x 1 x i8>* %0,
-    <vscale x 1 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vlxe.mask.nxv1i8.nxv1i16(
-  <vscale x 1 x i8>,
-  <vscale x 1 x i8>*,
-  <vscale x 1 x i16>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x i8> @intrinsic_vlxe_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i8_nxv1i8_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i8> @llvm.riscv.vlxe.mask.nxv1i8.nxv1i16(
-    <vscale x 1 x i8> %0,
-    <vscale x 1 x i8>* %1,
-    <vscale x 1 x i16> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vlxe.nxv2i8.nxv2i16(
-  <vscale x 2 x i8>*,
-  <vscale x 2 x i16>,
-  i32);
-
-define <vscale x 2 x i8> @intrinsic_vlxe_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i8_nxv2i8_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i8> @llvm.riscv.vlxe.nxv2i8.nxv2i16(
-    <vscale x 2 x i8>* %0,
-    <vscale x 2 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vlxe.mask.nxv2i8.nxv2i16(
-  <vscale x 2 x i8>,
-  <vscale x 2 x i8>*,
-  <vscale x 2 x i16>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i8> @intrinsic_vlxe_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i8_nxv2i8_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i8> @llvm.riscv.vlxe.mask.nxv2i8.nxv2i16(
-    <vscale x 2 x i8> %0,
-    <vscale x 2 x i8>* %1,
-    <vscale x 2 x i16> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vlxe.nxv4i8.nxv4i16(
-  <vscale x 4 x i8>*,
-  <vscale x 4 x i16>,
-  i32);
-
-define <vscale x 4 x i8> @intrinsic_vlxe_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i8_nxv4i8_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i8> @llvm.riscv.vlxe.nxv4i8.nxv4i16(
-    <vscale x 4 x i8>* %0,
-    <vscale x 4 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vlxe.mask.nxv4i8.nxv4i16(
-  <vscale x 4 x i8>,
-  <vscale x 4 x i8>*,
-  <vscale x 4 x i16>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i8> @intrinsic_vlxe_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i8_nxv4i8_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i8> @llvm.riscv.vlxe.mask.nxv4i8.nxv4i16(
-    <vscale x 4 x i8> %0,
-    <vscale x 4 x i8>* %1,
-    <vscale x 4 x i16> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vlxe.nxv8i8.nxv8i16(
-  <vscale x 8 x i8>*,
-  <vscale x 8 x i16>,
-  i32);
-
-define <vscale x 8 x i8> @intrinsic_vlxe_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i8_nxv8i8_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i8> @llvm.riscv.vlxe.nxv8i8.nxv8i16(
-    <vscale x 8 x i8>* %0,
-    <vscale x 8 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vlxe.mask.nxv8i8.nxv8i16(
-  <vscale x 8 x i8>,
-  <vscale x 8 x i8>*,
-  <vscale x 8 x i16>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i8> @intrinsic_vlxe_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i8_nxv8i8_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i8> @llvm.riscv.vlxe.mask.nxv8i8.nxv8i16(
-    <vscale x 8 x i8> %0,
-    <vscale x 8 x i8>* %1,
-    <vscale x 8 x i16> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vlxe.nxv16i8.nxv16i16(
-  <vscale x 16 x i8>*,
-  <vscale x 16 x i16>,
-  i32);
-
-define <vscale x 16 x i8> @intrinsic_vlxe_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i8_nxv16i8_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i8> @llvm.riscv.vlxe.nxv16i8.nxv16i16(
-    <vscale x 16 x i8>* %0,
-    <vscale x 16 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vlxe.mask.nxv16i8.nxv16i16(
-  <vscale x 16 x i8>,
-  <vscale x 16 x i8>*,
-  <vscale x 16 x i16>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i8> @intrinsic_vlxe_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i8_nxv16i8_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i8> @llvm.riscv.vlxe.mask.nxv16i8.nxv16i16(
-    <vscale x 16 x i8> %0,
-    <vscale x 16 x i8>* %1,
-    <vscale x 16 x i16> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vlxe.nxv32i8.nxv32i16(
-  <vscale x 32 x i8>*,
-  <vscale x 32 x i16>,
-  i32);
-
-define <vscale x 32 x i8> @intrinsic_vlxe_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv32i8_nxv32i8_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 32 x i8> @llvm.riscv.vlxe.nxv32i8.nxv32i16(
-    <vscale x 32 x i8>* %0,
-    <vscale x 32 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vlxe.mask.nxv32i8.nxv32i16(
-  <vscale x 32 x i8>,
-  <vscale x 32 x i8>*,
-  <vscale x 32 x i16>,
-  <vscale x 32 x i1>,
-  i32);
-
-define <vscale x 32 x i8> @intrinsic_vlxe_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv32i8_nxv32i8_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 32 x i8> @llvm.riscv.vlxe.mask.nxv32i8.nxv32i16(
-    <vscale x 32 x i8> %0,
-    <vscale x 32 x i8>* %1,
-    <vscale x 32 x i16> %2,
-    <vscale x 32 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vlxe.nxv1i16.nxv1i16(
-  <vscale x 1 x i16>*,
-  <vscale x 1 x i16>,
-  i32);
-
-define <vscale x 1 x i16> @intrinsic_vlxe_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i16_nxv1i16_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i16> @llvm.riscv.vlxe.nxv1i16.nxv1i16(
-    <vscale x 1 x i16>* %0,
-    <vscale x 1 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vlxe.mask.nxv1i16.nxv1i16(
-  <vscale x 1 x i16>,
-  <vscale x 1 x i16>*,
-  <vscale x 1 x i16>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x i16> @intrinsic_vlxe_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i16_nxv1i16_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i16> @llvm.riscv.vlxe.mask.nxv1i16.nxv1i16(
-    <vscale x 1 x i16> %0,
-    <vscale x 1 x i16>* %1,
-    <vscale x 1 x i16> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vlxe.nxv2i16.nxv2i16(
-  <vscale x 2 x i16>*,
-  <vscale x 2 x i16>,
-  i32);
-
-define <vscale x 2 x i16> @intrinsic_vlxe_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i16_nxv2i16_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i16> @llvm.riscv.vlxe.nxv2i16.nxv2i16(
-    <vscale x 2 x i16>* %0,
-    <vscale x 2 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vlxe.mask.nxv2i16.nxv2i16(
-  <vscale x 2 x i16>,
-  <vscale x 2 x i16>*,
-  <vscale x 2 x i16>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i16> @intrinsic_vlxe_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i16_nxv2i16_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i16> @llvm.riscv.vlxe.mask.nxv2i16.nxv2i16(
-    <vscale x 2 x i16> %0,
-    <vscale x 2 x i16>* %1,
-    <vscale x 2 x i16> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vlxe.nxv4i16.nxv4i16(
-  <vscale x 4 x i16>*,
-  <vscale x 4 x i16>,
-  i32);
-
-define <vscale x 4 x i16> @intrinsic_vlxe_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i16_nxv4i16_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i16> @llvm.riscv.vlxe.nxv4i16.nxv4i16(
-    <vscale x 4 x i16>* %0,
-    <vscale x 4 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vlxe.mask.nxv4i16.nxv4i16(
-  <vscale x 4 x i16>,
-  <vscale x 4 x i16>*,
-  <vscale x 4 x i16>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i16> @intrinsic_vlxe_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i16_nxv4i16_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i16> @llvm.riscv.vlxe.mask.nxv4i16.nxv4i16(
-    <vscale x 4 x i16> %0,
-    <vscale x 4 x i16>* %1,
-    <vscale x 4 x i16> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vlxe.nxv8i16.nxv8i16(
-  <vscale x 8 x i16>*,
-  <vscale x 8 x i16>,
-  i32);
-
-define <vscale x 8 x i16> @intrinsic_vlxe_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i16_nxv8i16_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i16> @llvm.riscv.vlxe.nxv8i16.nxv8i16(
-    <vscale x 8 x i16>* %0,
-    <vscale x 8 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vlxe.mask.nxv8i16.nxv8i16(
-  <vscale x 8 x i16>,
-  <vscale x 8 x i16>*,
-  <vscale x 8 x i16>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i16> @intrinsic_vlxe_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i16_nxv8i16_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i16> @llvm.riscv.vlxe.mask.nxv8i16.nxv8i16(
-    <vscale x 8 x i16> %0,
-    <vscale x 8 x i16>* %1,
-    <vscale x 8 x i16> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vlxe.nxv16i16.nxv16i16(
-  <vscale x 16 x i16>*,
-  <vscale x 16 x i16>,
-  i32);
-
-define <vscale x 16 x i16> @intrinsic_vlxe_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i16_nxv16i16_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i16> @llvm.riscv.vlxe.nxv16i16.nxv16i16(
-    <vscale x 16 x i16>* %0,
-    <vscale x 16 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vlxe.mask.nxv16i16.nxv16i16(
-  <vscale x 16 x i16>,
-  <vscale x 16 x i16>*,
-  <vscale x 16 x i16>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i16> @intrinsic_vlxe_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i16_nxv16i16_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i16> @llvm.riscv.vlxe.mask.nxv16i16.nxv16i16(
-    <vscale x 16 x i16> %0,
-    <vscale x 16 x i16>* %1,
-    <vscale x 16 x i16> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vlxe.nxv32i16.nxv32i16(
-  <vscale x 32 x i16>*,
-  <vscale x 32 x i16>,
-  i32);
-
-define <vscale x 32 x i16> @intrinsic_vlxe_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv32i16_nxv32i16_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 32 x i16> @llvm.riscv.vlxe.nxv32i16.nxv32i16(
-    <vscale x 32 x i16>* %0,
-    <vscale x 32 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vlxe.mask.nxv32i16.nxv32i16(
-  <vscale x 32 x i16>,
-  <vscale x 32 x i16>*,
-  <vscale x 32 x i16>,
-  <vscale x 32 x i1>,
-  i32);
-
-define <vscale x 32 x i16> @intrinsic_vlxe_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv32i16_nxv32i16_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 32 x i16> @llvm.riscv.vlxe.mask.nxv32i16.nxv32i16(
-    <vscale x 32 x i16> %0,
-    <vscale x 32 x i16>* %1,
-    <vscale x 32 x i16> %2,
-    <vscale x 32 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vlxe.nxv1i32.nxv1i16(
-  <vscale x 1 x i32>*,
-  <vscale x 1 x i16>,
-  i32);
-
-define <vscale x 1 x i32> @intrinsic_vlxe_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i32_nxv1i32_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i32> @llvm.riscv.vlxe.nxv1i32.nxv1i16(
-    <vscale x 1 x i32>* %0,
-    <vscale x 1 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vlxe.mask.nxv1i32.nxv1i16(
-  <vscale x 1 x i32>,
-  <vscale x 1 x i32>*,
-  <vscale x 1 x i16>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x i32> @intrinsic_vlxe_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i32_nxv1i32_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i32> @llvm.riscv.vlxe.mask.nxv1i32.nxv1i16(
-    <vscale x 1 x i32> %0,
-    <vscale x 1 x i32>* %1,
-    <vscale x 1 x i16> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vlxe.nxv2i32.nxv2i16(
-  <vscale x 2 x i32>*,
-  <vscale x 2 x i16>,
-  i32);
-
-define <vscale x 2 x i32> @intrinsic_vlxe_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i32_nxv2i32_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i32> @llvm.riscv.vlxe.nxv2i32.nxv2i16(
-    <vscale x 2 x i32>* %0,
-    <vscale x 2 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vlxe.mask.nxv2i32.nxv2i16(
-  <vscale x 2 x i32>,
-  <vscale x 2 x i32>*,
-  <vscale x 2 x i16>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i32> @intrinsic_vlxe_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i32_nxv2i32_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i32> @llvm.riscv.vlxe.mask.nxv2i32.nxv2i16(
-    <vscale x 2 x i32> %0,
-    <vscale x 2 x i32>* %1,
-    <vscale x 2 x i16> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vlxe.nxv4i32.nxv4i16(
-  <vscale x 4 x i32>*,
-  <vscale x 4 x i16>,
-  i32);
-
-define <vscale x 4 x i32> @intrinsic_vlxe_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i32_nxv4i32_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i32> @llvm.riscv.vlxe.nxv4i32.nxv4i16(
-    <vscale x 4 x i32>* %0,
-    <vscale x 4 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vlxe.mask.nxv4i32.nxv4i16(
-  <vscale x 4 x i32>,
-  <vscale x 4 x i32>*,
-  <vscale x 4 x i16>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i32> @intrinsic_vlxe_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i32_nxv4i32_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i32> @llvm.riscv.vlxe.mask.nxv4i32.nxv4i16(
-    <vscale x 4 x i32> %0,
-    <vscale x 4 x i32>* %1,
-    <vscale x 4 x i16> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vlxe.nxv8i32.nxv8i16(
-  <vscale x 8 x i32>*,
-  <vscale x 8 x i16>,
-  i32);
-
-define <vscale x 8 x i32> @intrinsic_vlxe_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i32_nxv8i32_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i32> @llvm.riscv.vlxe.nxv8i32.nxv8i16(
-    <vscale x 8 x i32>* %0,
-    <vscale x 8 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vlxe.mask.nxv8i32.nxv8i16(
-  <vscale x 8 x i32>,
-  <vscale x 8 x i32>*,
-  <vscale x 8 x i16>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i32> @intrinsic_vlxe_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i32_nxv8i32_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i32> @llvm.riscv.vlxe.mask.nxv8i32.nxv8i16(
-    <vscale x 8 x i32> %0,
-    <vscale x 8 x i32>* %1,
-    <vscale x 8 x i16> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vlxe.nxv16i32.nxv16i16(
-  <vscale x 16 x i32>*,
-  <vscale x 16 x i16>,
-  i32);
-
-define <vscale x 16 x i32> @intrinsic_vlxe_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i32_nxv16i32_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i32> @llvm.riscv.vlxe.nxv16i32.nxv16i16(
-    <vscale x 16 x i32>* %0,
-    <vscale x 16 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vlxe.mask.nxv16i32.nxv16i16(
-  <vscale x 16 x i32>,
-  <vscale x 16 x i32>*,
-  <vscale x 16 x i16>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i32> @intrinsic_vlxe_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i32_nxv16i32_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i32> @llvm.riscv.vlxe.mask.nxv16i32.nxv16i16(
-    <vscale x 16 x i32> %0,
-    <vscale x 16 x i32>* %1,
-    <vscale x 16 x i16> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x half> @llvm.riscv.vlxe.nxv1f16.nxv1i16(
-  <vscale x 1 x half>*,
-  <vscale x 1 x i16>,
-  i32);
-
-define <vscale x 1 x half> @intrinsic_vlxe_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1f16_nxv1f16_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x half> @llvm.riscv.vlxe.nxv1f16.nxv1i16(
-    <vscale x 1 x half>* %0,
-    <vscale x 1 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 1 x half> %a
-}
-
-declare <vscale x 1 x half> @llvm.riscv.vlxe.mask.nxv1f16.nxv1i16(
-  <vscale x 1 x half>,
-  <vscale x 1 x half>*,
-  <vscale x 1 x i16>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x half> @intrinsic_vlxe_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1f16_nxv1f16_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x half> @llvm.riscv.vlxe.mask.nxv1f16.nxv1i16(
-    <vscale x 1 x half> %0,
-    <vscale x 1 x half>* %1,
-    <vscale x 1 x i16> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x half> %a
-}
-
-declare <vscale x 2 x half> @llvm.riscv.vlxe.nxv2f16.nxv2i16(
-  <vscale x 2 x half>*,
-  <vscale x 2 x i16>,
-  i32);
-
-define <vscale x 2 x half> @intrinsic_vlxe_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2f16_nxv2f16_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x half> @llvm.riscv.vlxe.nxv2f16.nxv2i16(
-    <vscale x 2 x half>* %0,
-    <vscale x 2 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 2 x half> %a
-}
-
-declare <vscale x 2 x half> @llvm.riscv.vlxe.mask.nxv2f16.nxv2i16(
-  <vscale x 2 x half>,
-  <vscale x 2 x half>*,
-  <vscale x 2 x i16>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x half> @intrinsic_vlxe_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2f16_nxv2f16_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x half> @llvm.riscv.vlxe.mask.nxv2f16.nxv2i16(
-    <vscale x 2 x half> %0,
-    <vscale x 2 x half>* %1,
-    <vscale x 2 x i16> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x half> %a
-}
-
-declare <vscale x 4 x half> @llvm.riscv.vlxe.nxv4f16.nxv4i16(
-  <vscale x 4 x half>*,
-  <vscale x 4 x i16>,
-  i32);
-
-define <vscale x 4 x half> @intrinsic_vlxe_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4f16_nxv4f16_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x half> @llvm.riscv.vlxe.nxv4f16.nxv4i16(
-    <vscale x 4 x half>* %0,
-    <vscale x 4 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 4 x half> %a
-}
-
-declare <vscale x 4 x half> @llvm.riscv.vlxe.mask.nxv4f16.nxv4i16(
-  <vscale x 4 x half>,
-  <vscale x 4 x half>*,
-  <vscale x 4 x i16>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x half> @intrinsic_vlxe_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4f16_nxv4f16_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x half> @llvm.riscv.vlxe.mask.nxv4f16.nxv4i16(
-    <vscale x 4 x half> %0,
-    <vscale x 4 x half>* %1,
-    <vscale x 4 x i16> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x half> %a
-}
-
-declare <vscale x 8 x half> @llvm.riscv.vlxe.nxv8f16.nxv8i16(
-  <vscale x 8 x half>*,
-  <vscale x 8 x i16>,
-  i32);
-
-define <vscale x 8 x half> @intrinsic_vlxe_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8f16_nxv8f16_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x half> @llvm.riscv.vlxe.nxv8f16.nxv8i16(
-    <vscale x 8 x half>* %0,
-    <vscale x 8 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 8 x half> %a
-}
-
-declare <vscale x 8 x half> @llvm.riscv.vlxe.mask.nxv8f16.nxv8i16(
-  <vscale x 8 x half>,
-  <vscale x 8 x half>*,
-  <vscale x 8 x i16>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x half> @intrinsic_vlxe_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8f16_nxv8f16_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x half> @llvm.riscv.vlxe.mask.nxv8f16.nxv8i16(
-    <vscale x 8 x half> %0,
-    <vscale x 8 x half>* %1,
-    <vscale x 8 x i16> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x half> %a
-}
-
-declare <vscale x 16 x half> @llvm.riscv.vlxe.nxv16f16.nxv16i16(
-  <vscale x 16 x half>*,
-  <vscale x 16 x i16>,
-  i32);
-
-define <vscale x 16 x half> @intrinsic_vlxe_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16f16_nxv16f16_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x half> @llvm.riscv.vlxe.nxv16f16.nxv16i16(
-    <vscale x 16 x half>* %0,
-    <vscale x 16 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 16 x half> %a
-}
-
-declare <vscale x 16 x half> @llvm.riscv.vlxe.mask.nxv16f16.nxv16i16(
-  <vscale x 16 x half>,
-  <vscale x 16 x half>*,
-  <vscale x 16 x i16>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x half> @intrinsic_vlxe_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16f16_nxv16f16_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x half> @llvm.riscv.vlxe.mask.nxv16f16.nxv16i16(
-    <vscale x 16 x half> %0,
-    <vscale x 16 x half>* %1,
-    <vscale x 16 x i16> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x half> %a
-}
-
-declare <vscale x 32 x half> @llvm.riscv.vlxe.nxv32f16.nxv32i16(
-  <vscale x 32 x half>*,
-  <vscale x 32 x i16>,
-  i32);
-
-define <vscale x 32 x half> @intrinsic_vlxe_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half>* %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv32f16_nxv32f16_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 32 x half> @llvm.riscv.vlxe.nxv32f16.nxv32i16(
-    <vscale x 32 x half>* %0,
-    <vscale x 32 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 32 x half> %a
-}
-
-declare <vscale x 32 x half> @llvm.riscv.vlxe.mask.nxv32f16.nxv32i16(
-  <vscale x 32 x half>,
-  <vscale x 32 x half>*,
-  <vscale x 32 x i16>,
-  <vscale x 32 x i1>,
-  i32);
-
-define <vscale x 32 x half> @intrinsic_vlxe_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv32f16_nxv32f16_nxv32i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 32 x half> @llvm.riscv.vlxe.mask.nxv32f16.nxv32i16(
-    <vscale x 32 x half> %0,
-    <vscale x 32 x half>* %1,
-    <vscale x 32 x i16> %2,
-    <vscale x 32 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 32 x half> %a
-}
-
-declare <vscale x 1 x float> @llvm.riscv.vlxe.nxv1f32.nxv1i16(
-  <vscale x 1 x float>*,
-  <vscale x 1 x i16>,
-  i32);
-
-define <vscale x 1 x float> @intrinsic_vlxe_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1f32_nxv1f32_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x float> @llvm.riscv.vlxe.nxv1f32.nxv1i16(
-    <vscale x 1 x float>* %0,
-    <vscale x 1 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 1 x float> %a
-}
-
-declare <vscale x 1 x float> @llvm.riscv.vlxe.mask.nxv1f32.nxv1i16(
-  <vscale x 1 x float>,
-  <vscale x 1 x float>*,
-  <vscale x 1 x i16>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x float> @intrinsic_vlxe_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1f32_nxv1f32_nxv1i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x float> @llvm.riscv.vlxe.mask.nxv1f32.nxv1i16(
-    <vscale x 1 x float> %0,
-    <vscale x 1 x float>* %1,
-    <vscale x 1 x i16> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x float> %a
-}
-
-declare <vscale x 2 x float> @llvm.riscv.vlxe.nxv2f32.nxv2i16(
-  <vscale x 2 x float>*,
-  <vscale x 2 x i16>,
-  i32);
-
-define <vscale x 2 x float> @intrinsic_vlxe_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float>* %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2f32_nxv2f32_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x float> @llvm.riscv.vlxe.nxv2f32.nxv2i16(
-    <vscale x 2 x float>* %0,
-    <vscale x 2 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 2 x float> %a
-}
-
-declare <vscale x 2 x float> @llvm.riscv.vlxe.mask.nxv2f32.nxv2i16(
-  <vscale x 2 x float>,
-  <vscale x 2 x float>*,
-  <vscale x 2 x i16>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x float> @intrinsic_vlxe_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2f32_nxv2f32_nxv2i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x float> @llvm.riscv.vlxe.mask.nxv2f32.nxv2i16(
-    <vscale x 2 x float> %0,
-    <vscale x 2 x float>* %1,
-    <vscale x 2 x i16> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x float> %a
-}
-
-declare <vscale x 4 x float> @llvm.riscv.vlxe.nxv4f32.nxv4i16(
-  <vscale x 4 x float>*,
-  <vscale x 4 x i16>,
-  i32);
-
-define <vscale x 4 x float> @intrinsic_vlxe_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float>* %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4f32_nxv4f32_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x float> @llvm.riscv.vlxe.nxv4f32.nxv4i16(
-    <vscale x 4 x float>* %0,
-    <vscale x 4 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 4 x float> %a
-}
-
-declare <vscale x 4 x float> @llvm.riscv.vlxe.mask.nxv4f32.nxv4i16(
-  <vscale x 4 x float>,
-  <vscale x 4 x float>*,
-  <vscale x 4 x i16>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x float> @intrinsic_vlxe_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4f32_nxv4f32_nxv4i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x float> @llvm.riscv.vlxe.mask.nxv4f32.nxv4i16(
-    <vscale x 4 x float> %0,
-    <vscale x 4 x float>* %1,
-    <vscale x 4 x i16> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x float> %a
-}
-
-declare <vscale x 8 x float> @llvm.riscv.vlxe.nxv8f32.nxv8i16(
-  <vscale x 8 x float>*,
-  <vscale x 8 x i16>,
-  i32);
-
-define <vscale x 8 x float> @intrinsic_vlxe_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float>* %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8f32_nxv8f32_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x float> @llvm.riscv.vlxe.nxv8f32.nxv8i16(
-    <vscale x 8 x float>* %0,
-    <vscale x 8 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 8 x float> %a
-}
-
-declare <vscale x 8 x float> @llvm.riscv.vlxe.mask.nxv8f32.nxv8i16(
-  <vscale x 8 x float>,
-  <vscale x 8 x float>*,
-  <vscale x 8 x i16>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x float> @intrinsic_vlxe_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8f32_nxv8f32_nxv8i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x float> @llvm.riscv.vlxe.mask.nxv8f32.nxv8i16(
-    <vscale x 8 x float> %0,
-    <vscale x 8 x float>* %1,
-    <vscale x 8 x i16> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x float> %a
-}
-
-declare <vscale x 16 x float> @llvm.riscv.vlxe.nxv16f32.nxv16i16(
-  <vscale x 16 x float>*,
-  <vscale x 16 x i16>,
-  i32);
-
-define <vscale x 16 x float> @intrinsic_vlxe_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float>* %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16f32_nxv16f32_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x float> @llvm.riscv.vlxe.nxv16f32.nxv16i16(
-    <vscale x 16 x float>* %0,
-    <vscale x 16 x i16> %1,
-    i32 %2)
-
-  ret <vscale x 16 x float> %a
-}
-
-declare <vscale x 16 x float> @llvm.riscv.vlxe.mask.nxv16f32.nxv16i16(
-  <vscale x 16 x float>,
-  <vscale x 16 x float>*,
-  <vscale x 16 x i16>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x float> @intrinsic_vlxe_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16f32_nxv16f32_nxv16i16
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vlxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x float> @llvm.riscv.vlxe.mask.nxv16f32.nxv16i16(
-    <vscale x 16 x float> %0,
-    <vscale x 16 x float>* %1,
-    <vscale x 16 x i16> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x float> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vlxe.nxv1i8.nxv1i8(
-  <vscale x 1 x i8>*,
-  <vscale x 1 x i8>,
-  i32);
-
-define <vscale x 1 x i8> @intrinsic_vlxe_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i8_nxv1i8_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i8> @llvm.riscv.vlxe.nxv1i8.nxv1i8(
-    <vscale x 1 x i8>* %0,
-    <vscale x 1 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vlxe.mask.nxv1i8.nxv1i8(
-  <vscale x 1 x i8>,
-  <vscale x 1 x i8>*,
-  <vscale x 1 x i8>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x i8> @intrinsic_vlxe_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i8_nxv1i8_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i8> @llvm.riscv.vlxe.mask.nxv1i8.nxv1i8(
-    <vscale x 1 x i8> %0,
-    <vscale x 1 x i8>* %1,
-    <vscale x 1 x i8> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vlxe.nxv2i8.nxv2i8(
-  <vscale x 2 x i8>*,
-  <vscale x 2 x i8>,
-  i32);
-
-define <vscale x 2 x i8> @intrinsic_vlxe_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i8_nxv2i8_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i8> @llvm.riscv.vlxe.nxv2i8.nxv2i8(
-    <vscale x 2 x i8>* %0,
-    <vscale x 2 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vlxe.mask.nxv2i8.nxv2i8(
-  <vscale x 2 x i8>,
-  <vscale x 2 x i8>*,
-  <vscale x 2 x i8>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i8> @intrinsic_vlxe_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i8_nxv2i8_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i8> @llvm.riscv.vlxe.mask.nxv2i8.nxv2i8(
-    <vscale x 2 x i8> %0,
-    <vscale x 2 x i8>* %1,
-    <vscale x 2 x i8> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vlxe.nxv4i8.nxv4i8(
-  <vscale x 4 x i8>*,
-  <vscale x 4 x i8>,
-  i32);
-
-define <vscale x 4 x i8> @intrinsic_vlxe_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i8_nxv4i8_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i8> @llvm.riscv.vlxe.nxv4i8.nxv4i8(
-    <vscale x 4 x i8>* %0,
-    <vscale x 4 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vlxe.mask.nxv4i8.nxv4i8(
-  <vscale x 4 x i8>,
-  <vscale x 4 x i8>*,
-  <vscale x 4 x i8>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i8> @intrinsic_vlxe_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i8_nxv4i8_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i8> @llvm.riscv.vlxe.mask.nxv4i8.nxv4i8(
-    <vscale x 4 x i8> %0,
-    <vscale x 4 x i8>* %1,
-    <vscale x 4 x i8> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vlxe.nxv8i8.nxv8i8(
-  <vscale x 8 x i8>*,
-  <vscale x 8 x i8>,
-  i32);
-
-define <vscale x 8 x i8> @intrinsic_vlxe_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i8_nxv8i8_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i8> @llvm.riscv.vlxe.nxv8i8.nxv8i8(
-    <vscale x 8 x i8>* %0,
-    <vscale x 8 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vlxe.mask.nxv8i8.nxv8i8(
-  <vscale x 8 x i8>,
-  <vscale x 8 x i8>*,
-  <vscale x 8 x i8>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i8> @intrinsic_vlxe_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i8_nxv8i8_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i8> @llvm.riscv.vlxe.mask.nxv8i8.nxv8i8(
-    <vscale x 8 x i8> %0,
-    <vscale x 8 x i8>* %1,
-    <vscale x 8 x i8> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vlxe.nxv16i8.nxv16i8(
-  <vscale x 16 x i8>*,
-  <vscale x 16 x i8>,
-  i32);
-
-define <vscale x 16 x i8> @intrinsic_vlxe_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i8_nxv16i8_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i8> @llvm.riscv.vlxe.nxv16i8.nxv16i8(
-    <vscale x 16 x i8>* %0,
-    <vscale x 16 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vlxe.mask.nxv16i8.nxv16i8(
-  <vscale x 16 x i8>,
-  <vscale x 16 x i8>*,
-  <vscale x 16 x i8>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i8> @intrinsic_vlxe_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i8_nxv16i8_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i8> @llvm.riscv.vlxe.mask.nxv16i8.nxv16i8(
-    <vscale x 16 x i8> %0,
-    <vscale x 16 x i8>* %1,
-    <vscale x 16 x i8> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vlxe.nxv32i8.nxv32i8(
-  <vscale x 32 x i8>*,
-  <vscale x 32 x i8>,
-  i32);
-
-define <vscale x 32 x i8> @intrinsic_vlxe_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv32i8_nxv32i8_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 32 x i8> @llvm.riscv.vlxe.nxv32i8.nxv32i8(
-    <vscale x 32 x i8>* %0,
-    <vscale x 32 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vlxe.mask.nxv32i8.nxv32i8(
-  <vscale x 32 x i8>,
-  <vscale x 32 x i8>*,
-  <vscale x 32 x i8>,
-  <vscale x 32 x i1>,
-  i32);
-
-define <vscale x 32 x i8> @intrinsic_vlxe_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv32i8_nxv32i8_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 32 x i8> @llvm.riscv.vlxe.mask.nxv32i8.nxv32i8(
-    <vscale x 32 x i8> %0,
-    <vscale x 32 x i8>* %1,
-    <vscale x 32 x i8> %2,
-    <vscale x 32 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vlxe.nxv64i8.nxv64i8(
-  <vscale x 64 x i8>*,
-  <vscale x 64 x i8>,
-  i32);
-
-define <vscale x 64 x i8> @intrinsic_vlxe_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv64i8_nxv64i8_nxv64i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 64 x i8> @llvm.riscv.vlxe.nxv64i8.nxv64i8(
-    <vscale x 64 x i8>* %0,
-    <vscale x 64 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vlxe.mask.nxv64i8.nxv64i8(
-  <vscale x 64 x i8>,
-  <vscale x 64 x i8>*,
-  <vscale x 64 x i8>,
-  <vscale x 64 x i1>,
-  i32);
-
-define <vscale x 64 x i8> @intrinsic_vlxe_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv64i8_nxv64i8_nxv64i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 64 x i8> @llvm.riscv.vlxe.mask.nxv64i8.nxv64i8(
-    <vscale x 64 x i8> %0,
-    <vscale x 64 x i8>* %1,
-    <vscale x 64 x i8> %2,
-    <vscale x 64 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vlxe.nxv1i16.nxv1i8(
-  <vscale x 1 x i16>*,
-  <vscale x 1 x i8>,
-  i32);
-
-define <vscale x 1 x i16> @intrinsic_vlxe_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i16_nxv1i16_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i16> @llvm.riscv.vlxe.nxv1i16.nxv1i8(
-    <vscale x 1 x i16>* %0,
-    <vscale x 1 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vlxe.mask.nxv1i16.nxv1i8(
-  <vscale x 1 x i16>,
-  <vscale x 1 x i16>*,
-  <vscale x 1 x i8>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x i16> @intrinsic_vlxe_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i16_nxv1i16_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i16> @llvm.riscv.vlxe.mask.nxv1i16.nxv1i8(
-    <vscale x 1 x i16> %0,
-    <vscale x 1 x i16>* %1,
-    <vscale x 1 x i8> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vlxe.nxv2i16.nxv2i8(
-  <vscale x 2 x i16>*,
-  <vscale x 2 x i8>,
-  i32);
-
-define <vscale x 2 x i16> @intrinsic_vlxe_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i16_nxv2i16_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i16> @llvm.riscv.vlxe.nxv2i16.nxv2i8(
-    <vscale x 2 x i16>* %0,
-    <vscale x 2 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vlxe.mask.nxv2i16.nxv2i8(
-  <vscale x 2 x i16>,
-  <vscale x 2 x i16>*,
-  <vscale x 2 x i8>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i16> @intrinsic_vlxe_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i16_nxv2i16_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i16> @llvm.riscv.vlxe.mask.nxv2i16.nxv2i8(
-    <vscale x 2 x i16> %0,
-    <vscale x 2 x i16>* %1,
-    <vscale x 2 x i8> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vlxe.nxv4i16.nxv4i8(
-  <vscale x 4 x i16>*,
-  <vscale x 4 x i8>,
-  i32);
-
-define <vscale x 4 x i16> @intrinsic_vlxe_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i16_nxv4i16_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i16> @llvm.riscv.vlxe.nxv4i16.nxv4i8(
-    <vscale x 4 x i16>* %0,
-    <vscale x 4 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vlxe.mask.nxv4i16.nxv4i8(
-  <vscale x 4 x i16>,
-  <vscale x 4 x i16>*,
-  <vscale x 4 x i8>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i16> @intrinsic_vlxe_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i16_nxv4i16_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i16> @llvm.riscv.vlxe.mask.nxv4i16.nxv4i8(
-    <vscale x 4 x i16> %0,
-    <vscale x 4 x i16>* %1,
-    <vscale x 4 x i8> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vlxe.nxv8i16.nxv8i8(
-  <vscale x 8 x i16>*,
-  <vscale x 8 x i8>,
-  i32);
-
-define <vscale x 8 x i16> @intrinsic_vlxe_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i16_nxv8i16_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i16> @llvm.riscv.vlxe.nxv8i16.nxv8i8(
-    <vscale x 8 x i16>* %0,
-    <vscale x 8 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vlxe.mask.nxv8i16.nxv8i8(
-  <vscale x 8 x i16>,
-  <vscale x 8 x i16>*,
-  <vscale x 8 x i8>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i16> @intrinsic_vlxe_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i16_nxv8i16_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i16> @llvm.riscv.vlxe.mask.nxv8i16.nxv8i8(
-    <vscale x 8 x i16> %0,
-    <vscale x 8 x i16>* %1,
-    <vscale x 8 x i8> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vlxe.nxv16i16.nxv16i8(
-  <vscale x 16 x i16>*,
-  <vscale x 16 x i8>,
-  i32);
-
-define <vscale x 16 x i16> @intrinsic_vlxe_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i16_nxv16i16_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i16> @llvm.riscv.vlxe.nxv16i16.nxv16i8(
-    <vscale x 16 x i16>* %0,
-    <vscale x 16 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vlxe.mask.nxv16i16.nxv16i8(
-  <vscale x 16 x i16>,
-  <vscale x 16 x i16>*,
-  <vscale x 16 x i8>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i16> @intrinsic_vlxe_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i16_nxv16i16_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i16> @llvm.riscv.vlxe.mask.nxv16i16.nxv16i8(
-    <vscale x 16 x i16> %0,
-    <vscale x 16 x i16>* %1,
-    <vscale x 16 x i8> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vlxe.nxv32i16.nxv32i8(
-  <vscale x 32 x i16>*,
-  <vscale x 32 x i8>,
-  i32);
-
-define <vscale x 32 x i16> @intrinsic_vlxe_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv32i16_nxv32i16_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 32 x i16> @llvm.riscv.vlxe.nxv32i16.nxv32i8(
-    <vscale x 32 x i16>* %0,
-    <vscale x 32 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vlxe.mask.nxv32i16.nxv32i8(
-  <vscale x 32 x i16>,
-  <vscale x 32 x i16>*,
-  <vscale x 32 x i8>,
-  <vscale x 32 x i1>,
-  i32);
-
-define <vscale x 32 x i16> @intrinsic_vlxe_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv32i16_nxv32i16_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 32 x i16> @llvm.riscv.vlxe.mask.nxv32i16.nxv32i8(
-    <vscale x 32 x i16> %0,
-    <vscale x 32 x i16>* %1,
-    <vscale x 32 x i8> %2,
-    <vscale x 32 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vlxe.nxv1i32.nxv1i8(
-  <vscale x 1 x i32>*,
-  <vscale x 1 x i8>,
-  i32);
-
-define <vscale x 1 x i32> @intrinsic_vlxe_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1i32_nxv1i32_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x i32> @llvm.riscv.vlxe.nxv1i32.nxv1i8(
-    <vscale x 1 x i32>* %0,
-    <vscale x 1 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vlxe.mask.nxv1i32.nxv1i8(
-  <vscale x 1 x i32>,
-  <vscale x 1 x i32>*,
-  <vscale x 1 x i8>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x i32> @intrinsic_vlxe_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1i32_nxv1i32_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x i32> @llvm.riscv.vlxe.mask.nxv1i32.nxv1i8(
-    <vscale x 1 x i32> %0,
-    <vscale x 1 x i32>* %1,
-    <vscale x 1 x i8> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vlxe.nxv2i32.nxv2i8(
-  <vscale x 2 x i32>*,
-  <vscale x 2 x i8>,
-  i32);
-
-define <vscale x 2 x i32> @intrinsic_vlxe_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2i32_nxv2i32_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x i32> @llvm.riscv.vlxe.nxv2i32.nxv2i8(
-    <vscale x 2 x i32>* %0,
-    <vscale x 2 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vlxe.mask.nxv2i32.nxv2i8(
-  <vscale x 2 x i32>,
-  <vscale x 2 x i32>*,
-  <vscale x 2 x i8>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x i32> @intrinsic_vlxe_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2i32_nxv2i32_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x i32> @llvm.riscv.vlxe.mask.nxv2i32.nxv2i8(
-    <vscale x 2 x i32> %0,
-    <vscale x 2 x i32>* %1,
-    <vscale x 2 x i8> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vlxe.nxv4i32.nxv4i8(
-  <vscale x 4 x i32>*,
-  <vscale x 4 x i8>,
-  i32);
-
-define <vscale x 4 x i32> @intrinsic_vlxe_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4i32_nxv4i32_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x i32> @llvm.riscv.vlxe.nxv4i32.nxv4i8(
-    <vscale x 4 x i32>* %0,
-    <vscale x 4 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vlxe.mask.nxv4i32.nxv4i8(
-  <vscale x 4 x i32>,
-  <vscale x 4 x i32>*,
-  <vscale x 4 x i8>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x i32> @intrinsic_vlxe_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4i32_nxv4i32_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x i32> @llvm.riscv.vlxe.mask.nxv4i32.nxv4i8(
-    <vscale x 4 x i32> %0,
-    <vscale x 4 x i32>* %1,
-    <vscale x 4 x i8> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vlxe.nxv8i32.nxv8i8(
-  <vscale x 8 x i32>*,
-  <vscale x 8 x i8>,
-  i32);
-
-define <vscale x 8 x i32> @intrinsic_vlxe_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8i32_nxv8i32_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x i32> @llvm.riscv.vlxe.nxv8i32.nxv8i8(
-    <vscale x 8 x i32>* %0,
-    <vscale x 8 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vlxe.mask.nxv8i32.nxv8i8(
-  <vscale x 8 x i32>,
-  <vscale x 8 x i32>*,
-  <vscale x 8 x i8>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x i32> @intrinsic_vlxe_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8i32_nxv8i32_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x i32> @llvm.riscv.vlxe.mask.nxv8i32.nxv8i8(
-    <vscale x 8 x i32> %0,
-    <vscale x 8 x i32>* %1,
-    <vscale x 8 x i8> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vlxe.nxv16i32.nxv16i8(
-  <vscale x 16 x i32>*,
-  <vscale x 16 x i8>,
-  i32);
-
-define <vscale x 16 x i32> @intrinsic_vlxe_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16i32_nxv16i32_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x i32> @llvm.riscv.vlxe.nxv16i32.nxv16i8(
-    <vscale x 16 x i32>* %0,
-    <vscale x 16 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vlxe.mask.nxv16i32.nxv16i8(
-  <vscale x 16 x i32>,
-  <vscale x 16 x i32>*,
-  <vscale x 16 x i8>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x i32> @intrinsic_vlxe_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16i32_nxv16i32_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x i32> @llvm.riscv.vlxe.mask.nxv16i32.nxv16i8(
-    <vscale x 16 x i32> %0,
-    <vscale x 16 x i32>* %1,
-    <vscale x 16 x i8> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x half> @llvm.riscv.vlxe.nxv1f16.nxv1i8(
-  <vscale x 1 x half>*,
-  <vscale x 1 x i8>,
-  i32);
-
-define <vscale x 1 x half> @intrinsic_vlxe_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1f16_nxv1f16_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x half> @llvm.riscv.vlxe.nxv1f16.nxv1i8(
-    <vscale x 1 x half>* %0,
-    <vscale x 1 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 1 x half> %a
-}
-
-declare <vscale x 1 x half> @llvm.riscv.vlxe.mask.nxv1f16.nxv1i8(
-  <vscale x 1 x half>,
-  <vscale x 1 x half>*,
-  <vscale x 1 x i8>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x half> @intrinsic_vlxe_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1f16_nxv1f16_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x half> @llvm.riscv.vlxe.mask.nxv1f16.nxv1i8(
-    <vscale x 1 x half> %0,
-    <vscale x 1 x half>* %1,
-    <vscale x 1 x i8> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x half> %a
-}
-
-declare <vscale x 2 x half> @llvm.riscv.vlxe.nxv2f16.nxv2i8(
-  <vscale x 2 x half>*,
-  <vscale x 2 x i8>,
-  i32);
-
-define <vscale x 2 x half> @intrinsic_vlxe_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2f16_nxv2f16_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x half> @llvm.riscv.vlxe.nxv2f16.nxv2i8(
-    <vscale x 2 x half>* %0,
-    <vscale x 2 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 2 x half> %a
-}
-
-declare <vscale x 2 x half> @llvm.riscv.vlxe.mask.nxv2f16.nxv2i8(
-  <vscale x 2 x half>,
-  <vscale x 2 x half>*,
-  <vscale x 2 x i8>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x half> @intrinsic_vlxe_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2f16_nxv2f16_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x half> @llvm.riscv.vlxe.mask.nxv2f16.nxv2i8(
-    <vscale x 2 x half> %0,
-    <vscale x 2 x half>* %1,
-    <vscale x 2 x i8> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x half> %a
-}
-
-declare <vscale x 4 x half> @llvm.riscv.vlxe.nxv4f16.nxv4i8(
-  <vscale x 4 x half>*,
-  <vscale x 4 x i8>,
-  i32);
-
-define <vscale x 4 x half> @intrinsic_vlxe_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4f16_nxv4f16_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x half> @llvm.riscv.vlxe.nxv4f16.nxv4i8(
-    <vscale x 4 x half>* %0,
-    <vscale x 4 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 4 x half> %a
-}
-
-declare <vscale x 4 x half> @llvm.riscv.vlxe.mask.nxv4f16.nxv4i8(
-  <vscale x 4 x half>,
-  <vscale x 4 x half>*,
-  <vscale x 4 x i8>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x half> @intrinsic_vlxe_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4f16_nxv4f16_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x half> @llvm.riscv.vlxe.mask.nxv4f16.nxv4i8(
-    <vscale x 4 x half> %0,
-    <vscale x 4 x half>* %1,
-    <vscale x 4 x i8> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x half> %a
-}
-
-declare <vscale x 8 x half> @llvm.riscv.vlxe.nxv8f16.nxv8i8(
-  <vscale x 8 x half>*,
-  <vscale x 8 x i8>,
-  i32);
-
-define <vscale x 8 x half> @intrinsic_vlxe_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8f16_nxv8f16_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x half> @llvm.riscv.vlxe.nxv8f16.nxv8i8(
-    <vscale x 8 x half>* %0,
-    <vscale x 8 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 8 x half> %a
-}
-
-declare <vscale x 8 x half> @llvm.riscv.vlxe.mask.nxv8f16.nxv8i8(
-  <vscale x 8 x half>,
-  <vscale x 8 x half>*,
-  <vscale x 8 x i8>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x half> @intrinsic_vlxe_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8f16_nxv8f16_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x half> @llvm.riscv.vlxe.mask.nxv8f16.nxv8i8(
-    <vscale x 8 x half> %0,
-    <vscale x 8 x half>* %1,
-    <vscale x 8 x i8> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x half> %a
-}
-
-declare <vscale x 16 x half> @llvm.riscv.vlxe.nxv16f16.nxv16i8(
-  <vscale x 16 x half>*,
-  <vscale x 16 x i8>,
-  i32);
-
-define <vscale x 16 x half> @intrinsic_vlxe_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16f16_nxv16f16_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x half> @llvm.riscv.vlxe.nxv16f16.nxv16i8(
-    <vscale x 16 x half>* %0,
-    <vscale x 16 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 16 x half> %a
-}
-
-declare <vscale x 16 x half> @llvm.riscv.vlxe.mask.nxv16f16.nxv16i8(
-  <vscale x 16 x half>,
-  <vscale x 16 x half>*,
-  <vscale x 16 x i8>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x half> @intrinsic_vlxe_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16f16_nxv16f16_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x half> @llvm.riscv.vlxe.mask.nxv16f16.nxv16i8(
-    <vscale x 16 x half> %0,
-    <vscale x 16 x half>* %1,
-    <vscale x 16 x i8> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x half> %a
-}
-
-declare <vscale x 32 x half> @llvm.riscv.vlxe.nxv32f16.nxv32i8(
-  <vscale x 32 x half>*,
-  <vscale x 32 x i8>,
-  i32);
-
-define <vscale x 32 x half> @intrinsic_vlxe_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half>* %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv32f16_nxv32f16_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 32 x half> @llvm.riscv.vlxe.nxv32f16.nxv32i8(
-    <vscale x 32 x half>* %0,
-    <vscale x 32 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 32 x half> %a
-}
-
-declare <vscale x 32 x half> @llvm.riscv.vlxe.mask.nxv32f16.nxv32i8(
-  <vscale x 32 x half>,
-  <vscale x 32 x half>*,
-  <vscale x 32 x i8>,
-  <vscale x 32 x i1>,
-  i32);
-
-define <vscale x 32 x half> @intrinsic_vlxe_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv32f16_nxv32f16_nxv32i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 32 x half> @llvm.riscv.vlxe.mask.nxv32f16.nxv32i8(
-    <vscale x 32 x half> %0,
-    <vscale x 32 x half>* %1,
-    <vscale x 32 x i8> %2,
-    <vscale x 32 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 32 x half> %a
-}
-
-declare <vscale x 1 x float> @llvm.riscv.vlxe.nxv1f32.nxv1i8(
-  <vscale x 1 x float>*,
-  <vscale x 1 x i8>,
-  i32);
-
-define <vscale x 1 x float> @intrinsic_vlxe_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float>* %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv1f32_nxv1f32_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 1 x float> @llvm.riscv.vlxe.nxv1f32.nxv1i8(
-    <vscale x 1 x float>* %0,
-    <vscale x 1 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 1 x float> %a
-}
-
-declare <vscale x 1 x float> @llvm.riscv.vlxe.mask.nxv1f32.nxv1i8(
-  <vscale x 1 x float>,
-  <vscale x 1 x float>*,
-  <vscale x 1 x i8>,
-  <vscale x 1 x i1>,
-  i32);
-
-define <vscale x 1 x float> @intrinsic_vlxe_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv1f32_nxv1f32_nxv1i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 1 x float> @llvm.riscv.vlxe.mask.nxv1f32.nxv1i8(
-    <vscale x 1 x float> %0,
-    <vscale x 1 x float>* %1,
-    <vscale x 1 x i8> %2,
-    <vscale x 1 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 1 x float> %a
-}
-
-declare <vscale x 2 x float> @llvm.riscv.vlxe.nxv2f32.nxv2i8(
-  <vscale x 2 x float>*,
-  <vscale x 2 x i8>,
-  i32);
-
-define <vscale x 2 x float> @intrinsic_vlxe_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float>* %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv2f32_nxv2f32_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 2 x float> @llvm.riscv.vlxe.nxv2f32.nxv2i8(
-    <vscale x 2 x float>* %0,
-    <vscale x 2 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 2 x float> %a
-}
-
-declare <vscale x 2 x float> @llvm.riscv.vlxe.mask.nxv2f32.nxv2i8(
-  <vscale x 2 x float>,
-  <vscale x 2 x float>*,
-  <vscale x 2 x i8>,
-  <vscale x 2 x i1>,
-  i32);
-
-define <vscale x 2 x float> @intrinsic_vlxe_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv2f32_nxv2f32_nxv2i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 2 x float> @llvm.riscv.vlxe.mask.nxv2f32.nxv2i8(
-    <vscale x 2 x float> %0,
-    <vscale x 2 x float>* %1,
-    <vscale x 2 x i8> %2,
-    <vscale x 2 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 2 x float> %a
-}
-
-declare <vscale x 4 x float> @llvm.riscv.vlxe.nxv4f32.nxv4i8(
-  <vscale x 4 x float>*,
-  <vscale x 4 x i8>,
-  i32);
-
-define <vscale x 4 x float> @intrinsic_vlxe_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float>* %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv4f32_nxv4f32_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 4 x float> @llvm.riscv.vlxe.nxv4f32.nxv4i8(
-    <vscale x 4 x float>* %0,
-    <vscale x 4 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 4 x float> %a
-}
-
-declare <vscale x 4 x float> @llvm.riscv.vlxe.mask.nxv4f32.nxv4i8(
-  <vscale x 4 x float>,
-  <vscale x 4 x float>*,
-  <vscale x 4 x i8>,
-  <vscale x 4 x i1>,
-  i32);
-
-define <vscale x 4 x float> @intrinsic_vlxe_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv4f32_nxv4f32_nxv4i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 4 x float> @llvm.riscv.vlxe.mask.nxv4f32.nxv4i8(
-    <vscale x 4 x float> %0,
-    <vscale x 4 x float>* %1,
-    <vscale x 4 x i8> %2,
-    <vscale x 4 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 4 x float> %a
-}
-
-declare <vscale x 8 x float> @llvm.riscv.vlxe.nxv8f32.nxv8i8(
-  <vscale x 8 x float>*,
-  <vscale x 8 x i8>,
-  i32);
-
-define <vscale x 8 x float> @intrinsic_vlxe_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float>* %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv8f32_nxv8f32_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 8 x float> @llvm.riscv.vlxe.nxv8f32.nxv8i8(
-    <vscale x 8 x float>* %0,
-    <vscale x 8 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 8 x float> %a
-}
-
-declare <vscale x 8 x float> @llvm.riscv.vlxe.mask.nxv8f32.nxv8i8(
-  <vscale x 8 x float>,
-  <vscale x 8 x float>*,
-  <vscale x 8 x i8>,
-  <vscale x 8 x i1>,
-  i32);
-
-define <vscale x 8 x float> @intrinsic_vlxe_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv8f32_nxv8f32_nxv8i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 8 x float> @llvm.riscv.vlxe.mask.nxv8f32.nxv8i8(
-    <vscale x 8 x float> %0,
-    <vscale x 8 x float>* %1,
-    <vscale x 8 x i8> %2,
-    <vscale x 8 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 8 x float> %a
-}
-
-declare <vscale x 16 x float> @llvm.riscv.vlxe.nxv16f32.nxv16i8(
-  <vscale x 16 x float>*,
-  <vscale x 16 x i8>,
-  i32);
-
-define <vscale x 16 x float> @intrinsic_vlxe_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float>* %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_v_nxv16f32_nxv16f32_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  %a = call <vscale x 16 x float> @llvm.riscv.vlxe.nxv16f32.nxv16i8(
-    <vscale x 16 x float>* %0,
-    <vscale x 16 x i8> %1,
-    i32 %2)
-
-  ret <vscale x 16 x float> %a
-}
-
-declare <vscale x 16 x float> @llvm.riscv.vlxe.mask.nxv16f32.nxv16i8(
-  <vscale x 16 x float>,
-  <vscale x 16 x float>*,
-  <vscale x 16 x i8>,
-  <vscale x 16 x i1>,
-  i32);
-
-define <vscale x 16 x float> @intrinsic_vlxe_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vlxe_mask_v_nxv16f32_nxv16f32_nxv16i8
-; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu
-; CHECK:       vlxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  %a = call <vscale x 16 x float> @llvm.riscv.vlxe.mask.nxv16f32.nxv16i8(
-    <vscale x 16 x float> %0,
-    <vscale x 16 x float>* %1,
-    <vscale x 16 x i8> %2,
-    <vscale x 16 x i1> %3,
-    i32 %4)
-
-  ret <vscale x 16 x float> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll
@@ -1,17 +1,17 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh,+f -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
-declare void @llvm.riscv.vsxe.nxv1i8.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1i8.nxv1i32(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i8.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i8.nxv1i32(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i32> %2,
@@ -20,19 +20,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i32(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i32(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i32> %2,
@@ -42,18 +42,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i8.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2i8.nxv2i32(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i8.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i8.nxv2i32(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i32> %2,
@@ -62,19 +62,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i32(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i32(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i32> %2,
@@ -84,18 +84,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i8.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4i8.nxv4i32(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i8.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i8.nxv4i32(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i32> %2,
@@ -104,19 +104,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i32(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i32(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i32> %2,
@@ -126,18 +126,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i8.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8i8.nxv8i32(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i8.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i8.nxv8i32(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i32> %2,
@@ -146,19 +146,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i32(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i32(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i32> %2,
@@ -168,18 +168,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i8.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16i8.nxv16i32(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i8.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i8.nxv16i32(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i32> %2,
@@ -188,19 +188,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i32(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i32(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i32> %2,
@@ -210,18 +210,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i16.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1i16.nxv1i32(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i16.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i16.nxv1i32(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i32> %2,
@@ -230,19 +230,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i32(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i32(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i32> %2,
@@ -252,18 +252,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i16.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2i16.nxv2i32(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i16.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i16.nxv2i32(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i32> %2,
@@ -272,19 +272,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i32(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i32(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i32> %2,
@@ -294,18 +294,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i16.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4i16.nxv4i32(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i16.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i16.nxv4i32(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i32> %2,
@@ -314,19 +314,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i32(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i32(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i32> %2,
@@ -336,18 +336,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i16.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8i16.nxv8i32(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i16.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i16.nxv8i32(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i32> %2,
@@ -356,19 +356,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i32(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i32(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i32> %2,
@@ -378,18 +378,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i16.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16i16.nxv16i32(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i16.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i16.nxv16i32(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i32> %2,
@@ -398,19 +398,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i32(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i32(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i32> %2,
@@ -420,18 +420,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i32.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1i32.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i32.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i32.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i32> %2,
@@ -440,19 +440,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i32> %2,
@@ -462,18 +462,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i32.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2i32.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i32.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i32.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i32> %2,
@@ -482,19 +482,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i32> %2,
@@ -504,18 +504,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i32.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4i32.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i32.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i32.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i32> %2,
@@ -524,19 +524,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i32> %2,
@@ -546,18 +546,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i32.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8i32.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i32.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i32.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i32> %2,
@@ -566,19 +566,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i32> %2,
@@ -588,18 +588,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i32.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16i32.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i32.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i32.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i32> %2,
@@ -608,19 +608,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i32> %2,
@@ -630,18 +630,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f16.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1f16.nxv1i32(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f16.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f16.nxv1i32(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i32> %2,
@@ -650,19 +650,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i32(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i32(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i32> %2,
@@ -672,18 +672,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f16.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2f16.nxv2i32(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f16.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f16.nxv2i32(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i32> %2,
@@ -692,19 +692,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i32(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i32(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i32> %2,
@@ -714,18 +714,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f16.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4f16.nxv4i32(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f16.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f16.nxv4i32(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i32> %2,
@@ -734,19 +734,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i32(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i32(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i32> %2,
@@ -756,18 +756,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f16.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8f16.nxv8i32(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f16.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f16.nxv8i32(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i32> %2,
@@ -776,19 +776,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i32(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i32(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i32> %2,
@@ -798,18 +798,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f16.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16f16.nxv16i32(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f16.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f16.nxv16i32(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i32> %2,
@@ -818,19 +818,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i32(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i32(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i32> %2,
@@ -840,18 +840,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f32.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1f32.nxv1i32(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f32.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f32.nxv1i32(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i32> %2,
@@ -860,19 +860,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i32(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i32(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i32> %2,
@@ -882,18 +882,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f32.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2f32.nxv2i32(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f32.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f32.nxv2i32(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i32> %2,
@@ -902,19 +902,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i32(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i32(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i32> %2,
@@ -924,18 +924,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f32.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4f32.nxv4i32(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f32.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f32.nxv4i32(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i32> %2,
@@ -944,19 +944,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i32(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i32(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i32> %2,
@@ -966,18 +966,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f32.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8f32.nxv8i32(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f32.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f32.nxv8i32(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i32> %2,
@@ -986,19 +986,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i32(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i32(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i32> %2,
@@ -1008,18 +1008,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f32.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16f32.nxv16i32(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i32>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f32.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f32.nxv16i32(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i32> %2,
@@ -1028,19 +1028,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i32(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i32(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i32> %2,
@@ -1050,18 +1050,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i8.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1i8.nxv1i16(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i8.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i8.nxv1i16(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i16> %2,
@@ -1070,19 +1070,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i16(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i16(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i16> %2,
@@ -1092,18 +1092,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i8.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2i8.nxv2i16(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i8.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i8.nxv2i16(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i16> %2,
@@ -1112,19 +1112,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i16(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i16(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i16> %2,
@@ -1134,18 +1134,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i8.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4i8.nxv4i16(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i8.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i8.nxv4i16(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i16> %2,
@@ -1154,19 +1154,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i16(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i16(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i16> %2,
@@ -1176,18 +1176,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i8.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8i8.nxv8i16(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i8.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i8.nxv8i16(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i16> %2,
@@ -1196,19 +1196,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i16(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i16(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i16> %2,
@@ -1218,18 +1218,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i8.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16i8.nxv16i16(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i8.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i8.nxv16i16(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i16> %2,
@@ -1238,19 +1238,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i16(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i16(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i16> %2,
@@ -1260,18 +1260,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32i8.nxv32i16(
+declare void @llvm.riscv.vsoxe.nxv32i8.nxv32i16(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>*,
   <vscale x 32 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32i8_nxv32i8_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32i8_nxv32i8_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32i8.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32i8.nxv32i16(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8>* %1,
     <vscale x 32 x i16> %2,
@@ -1280,19 +1280,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32i8.nxv32i16(
+declare void @llvm.riscv.vsoxe.mask.nxv32i8.nxv32i16(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>*,
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32i8_nxv32i8_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32i8_nxv32i8_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32i8.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32i8.nxv32i16(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8>* %1,
     <vscale x 32 x i16> %2,
@@ -1302,18 +1302,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i16.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1i16.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i16.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i16.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i16> %2,
@@ -1322,19 +1322,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i16> %2,
@@ -1344,18 +1344,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i16.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2i16.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i16.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i16.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i16> %2,
@@ -1364,19 +1364,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i16> %2,
@@ -1386,18 +1386,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i16.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4i16.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i16.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i16.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i16> %2,
@@ -1406,19 +1406,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i16> %2,
@@ -1428,18 +1428,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i16.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8i16.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i16.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i16.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i16> %2,
@@ -1448,19 +1448,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i16> %2,
@@ -1470,18 +1470,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i16.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16i16.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i16.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i16.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i16> %2,
@@ -1490,19 +1490,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i16> %2,
@@ -1512,18 +1512,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32i16.nxv32i16(
+declare void @llvm.riscv.vsoxe.nxv32i16.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>*,
   <vscale x 32 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32i16_nxv32i16_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32i16_nxv32i16_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32i16.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32i16.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16>* %1,
     <vscale x 32 x i16> %2,
@@ -1532,19 +1532,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32i16.nxv32i16(
+declare void @llvm.riscv.vsoxe.mask.nxv32i16.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>*,
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32i16_nxv32i16_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32i16_nxv32i16_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32i16.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32i16.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16>* %1,
     <vscale x 32 x i16> %2,
@@ -1554,18 +1554,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i32.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1i32.nxv1i16(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i32.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i32.nxv1i16(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i16> %2,
@@ -1574,19 +1574,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i16(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i16(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i16> %2,
@@ -1596,18 +1596,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i32.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2i32.nxv2i16(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i32.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i32.nxv2i16(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i16> %2,
@@ -1616,19 +1616,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i16(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i16(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i16> %2,
@@ -1638,18 +1638,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i32.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4i32.nxv4i16(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i32.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i32.nxv4i16(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i16> %2,
@@ -1658,19 +1658,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i16(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i16(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i16> %2,
@@ -1680,18 +1680,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i32.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8i32.nxv8i16(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i32.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i32.nxv8i16(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i16> %2,
@@ -1700,19 +1700,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i16(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i16(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i16> %2,
@@ -1722,18 +1722,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i32.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16i32.nxv16i16(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i32.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i32.nxv16i16(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i16> %2,
@@ -1742,19 +1742,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i16(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i16(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i16> %2,
@@ -1764,18 +1764,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f16.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1f16.nxv1i16(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f16.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f16.nxv1i16(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i16> %2,
@@ -1784,19 +1784,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i16(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i16(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i16> %2,
@@ -1806,18 +1806,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f16.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2f16.nxv2i16(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f16.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f16.nxv2i16(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i16> %2,
@@ -1826,19 +1826,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i16(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i16(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i16> %2,
@@ -1848,18 +1848,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f16.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4f16.nxv4i16(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f16.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f16.nxv4i16(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i16> %2,
@@ -1868,19 +1868,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i16(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i16(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i16> %2,
@@ -1890,18 +1890,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f16.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8f16.nxv8i16(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f16.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f16.nxv8i16(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i16> %2,
@@ -1910,19 +1910,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i16(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i16(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i16> %2,
@@ -1932,18 +1932,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f16.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16f16.nxv16i16(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f16.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f16.nxv16i16(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i16> %2,
@@ -1952,19 +1952,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i16(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i16(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i16> %2,
@@ -1974,18 +1974,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32f16.nxv32i16(
+declare void @llvm.riscv.vsoxe.nxv32f16.nxv32i16(
   <vscale x 32 x half>,
   <vscale x 32 x half>*,
   <vscale x 32 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32f16_nxv32f16_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32f16_nxv32f16_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32f16.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32f16.nxv32i16(
     <vscale x 32 x half> %0,
     <vscale x 32 x half>* %1,
     <vscale x 32 x i16> %2,
@@ -1994,19 +1994,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32f16.nxv32i16(
+declare void @llvm.riscv.vsoxe.mask.nxv32f16.nxv32i16(
   <vscale x 32 x half>,
   <vscale x 32 x half>*,
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32f16_nxv32f16_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32f16_nxv32f16_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32f16.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32f16.nxv32i16(
     <vscale x 32 x half> %0,
     <vscale x 32 x half>* %1,
     <vscale x 32 x i16> %2,
@@ -2016,18 +2016,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f32.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1f32.nxv1i16(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f32.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f32.nxv1i16(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i16> %2,
@@ -2036,19 +2036,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i16(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i16(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i16> %2,
@@ -2058,18 +2058,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f32.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2f32.nxv2i16(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f32.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f32.nxv2i16(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i16> %2,
@@ -2078,19 +2078,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i16(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i16(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i16> %2,
@@ -2100,18 +2100,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f32.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4f32.nxv4i16(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f32.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f32.nxv4i16(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i16> %2,
@@ -2120,19 +2120,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i16(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i16(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i16> %2,
@@ -2142,18 +2142,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f32.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8f32.nxv8i16(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f32.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f32.nxv8i16(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i16> %2,
@@ -2162,19 +2162,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i16(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i16(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i16> %2,
@@ -2184,18 +2184,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f32.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16f32.nxv16i16(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i16>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f32.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f32.nxv16i16(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i16> %2,
@@ -2204,19 +2204,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i16(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i16(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i16> %2,
@@ -2226,18 +2226,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i8.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1i8.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i8.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i8.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i8> %2,
@@ -2246,19 +2246,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i8> %2,
@@ -2268,18 +2268,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i8.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2i8.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i8.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i8.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i8> %2,
@@ -2288,19 +2288,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i8> %2,
@@ -2310,18 +2310,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i8.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4i8.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i8.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i8.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i8> %2,
@@ -2330,19 +2330,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i8> %2,
@@ -2352,18 +2352,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i8.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8i8.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i8.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i8.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i8> %2,
@@ -2372,19 +2372,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i8> %2,
@@ -2394,18 +2394,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i8.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16i8.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i8.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i8.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i8> %2,
@@ -2414,19 +2414,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i8> %2,
@@ -2436,18 +2436,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32i8.nxv32i8(
+declare void @llvm.riscv.vsoxe.nxv32i8.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>*,
   <vscale x 32 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32i8_nxv32i8_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32i8_nxv32i8_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32i8.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32i8.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8>* %1,
     <vscale x 32 x i8> %2,
@@ -2456,19 +2456,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32i8.nxv32i8(
+declare void @llvm.riscv.vsoxe.mask.nxv32i8.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>*,
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32i8_nxv32i8_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32i8_nxv32i8_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32i8.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32i8.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8>* %1,
     <vscale x 32 x i8> %2,
@@ -2478,18 +2478,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv64i8.nxv64i8(
+declare void @llvm.riscv.vsoxe.nxv64i8.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>*,
   <vscale x 64 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv64i8_nxv64i8_nxv64i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv64i8_nxv64i8_nxv64i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv64i8.nxv64i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv64i8.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8>* %1,
     <vscale x 64 x i8> %2,
@@ -2498,19 +2498,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv64i8.nxv64i8(
+declare void @llvm.riscv.vsoxe.mask.nxv64i8.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>*,
   <vscale x 64 x i8>,
   <vscale x 64 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv64i8_nxv64i8_nxv64i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv64i8_nxv64i8_nxv64i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv64i8.nxv64i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv64i8.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8>* %1,
     <vscale x 64 x i8> %2,
@@ -2520,18 +2520,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i16.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1i16.nxv1i8(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i16.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i16.nxv1i8(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i8> %2,
@@ -2540,19 +2540,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i8(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i8(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i8> %2,
@@ -2562,18 +2562,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i16.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2i16.nxv2i8(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i16.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i16.nxv2i8(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i8> %2,
@@ -2582,19 +2582,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i8(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i8(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i8> %2,
@@ -2604,18 +2604,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i16.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4i16.nxv4i8(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i16.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i16.nxv4i8(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i8> %2,
@@ -2624,19 +2624,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i8(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i8(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i8> %2,
@@ -2646,18 +2646,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i16.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8i16.nxv8i8(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i16.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i16.nxv8i8(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i8> %2,
@@ -2666,19 +2666,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i8(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i8(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i8> %2,
@@ -2688,18 +2688,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i16.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16i16.nxv16i8(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i16.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i16.nxv16i8(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i8> %2,
@@ -2708,19 +2708,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i8(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i8(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i8> %2,
@@ -2730,18 +2730,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32i16.nxv32i8(
+declare void @llvm.riscv.vsoxe.nxv32i16.nxv32i8(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>*,
   <vscale x 32 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32i16_nxv32i16_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32i16_nxv32i16_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32i16.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32i16.nxv32i8(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16>* %1,
     <vscale x 32 x i8> %2,
@@ -2750,19 +2750,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32i16.nxv32i8(
+declare void @llvm.riscv.vsoxe.mask.nxv32i16.nxv32i8(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>*,
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32i16_nxv32i16_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32i16_nxv32i16_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32i16.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32i16.nxv32i8(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16>* %1,
     <vscale x 32 x i8> %2,
@@ -2772,18 +2772,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i32.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1i32.nxv1i8(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i32.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i32.nxv1i8(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i8> %2,
@@ -2792,19 +2792,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i8(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i8(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i8> %2,
@@ -2814,18 +2814,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i32.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2i32.nxv2i8(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i32.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i32.nxv2i8(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i8> %2,
@@ -2834,19 +2834,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i8(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i8(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i8> %2,
@@ -2856,18 +2856,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i32.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4i32.nxv4i8(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i32.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i32.nxv4i8(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i8> %2,
@@ -2876,19 +2876,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i8(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i8(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i8> %2,
@@ -2898,18 +2898,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i32.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8i32.nxv8i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i32.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i32.nxv8i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i8> %2,
@@ -2918,19 +2918,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i8> %2,
@@ -2940,18 +2940,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i32.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16i32.nxv16i8(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i32.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i32.nxv16i8(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i8> %2,
@@ -2960,19 +2960,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i8(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i8(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i8> %2,
@@ -2982,18 +2982,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f16.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1f16.nxv1i8(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f16.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f16.nxv1i8(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i8> %2,
@@ -3002,19 +3002,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i8(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i8(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i8> %2,
@@ -3024,18 +3024,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f16.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2f16.nxv2i8(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f16.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f16.nxv2i8(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i8> %2,
@@ -3044,19 +3044,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i8(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i8(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i8> %2,
@@ -3066,18 +3066,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f16.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4f16.nxv4i8(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f16.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f16.nxv4i8(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i8> %2,
@@ -3086,19 +3086,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i8(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i8(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i8> %2,
@@ -3108,18 +3108,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f16.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8f16.nxv8i8(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f16.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f16.nxv8i8(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i8> %2,
@@ -3128,19 +3128,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i8(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i8(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i8> %2,
@@ -3150,18 +3150,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f16.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16f16.nxv16i8(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f16.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f16.nxv16i8(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i8> %2,
@@ -3170,19 +3170,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i8(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i8(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i8> %2,
@@ -3192,18 +3192,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32f16.nxv32i8(
+declare void @llvm.riscv.vsoxe.nxv32f16.nxv32i8(
   <vscale x 32 x half>,
   <vscale x 32 x half>*,
   <vscale x 32 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32f16_nxv32f16_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32f16_nxv32f16_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32f16.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32f16.nxv32i8(
     <vscale x 32 x half> %0,
     <vscale x 32 x half>* %1,
     <vscale x 32 x i8> %2,
@@ -3212,19 +3212,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32f16.nxv32i8(
+declare void @llvm.riscv.vsoxe.mask.nxv32f16.nxv32i8(
   <vscale x 32 x half>,
   <vscale x 32 x half>*,
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32f16_nxv32f16_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32f16_nxv32f16_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32f16.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32f16.nxv32i8(
     <vscale x 32 x half> %0,
     <vscale x 32 x half>* %1,
     <vscale x 32 x i8> %2,
@@ -3234,18 +3234,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f32.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1f32.nxv1i8(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f32.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f32.nxv1i8(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i8> %2,
@@ -3254,19 +3254,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i8(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i8(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i8> %2,
@@ -3276,18 +3276,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f32.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2f32.nxv2i8(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f32.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f32.nxv2i8(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i8> %2,
@@ -3296,19 +3296,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i8(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i8(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i8> %2,
@@ -3318,18 +3318,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f32.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4f32.nxv4i8(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f32.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f32.nxv4i8(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i8> %2,
@@ -3338,19 +3338,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i8(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i8(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i8> %2,
@@ -3360,18 +3360,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f32.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8f32.nxv8i8(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f32.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f32.nxv8i8(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i8> %2,
@@ -3380,19 +3380,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i8(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i8(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i8> %2,
@@ -3402,18 +3402,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f32.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16f32.nxv16i8(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i8>,
   i32);
 
-define void @intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f32.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f32.nxv16i8(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i8> %2,
@@ -3422,19 +3422,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i8(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i32);
 
-define void @intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i8(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i8> %2,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll
@@ -1,17 +1,17 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
-declare void @llvm.riscv.vsxe.nxv1i8.nxv1i64(
+declare void @llvm.riscv.vsoxe.nxv1i8.nxv1i64(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i8.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i8.nxv1i64(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i64> %2,
@@ -20,19 +20,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i64(
+declare void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i64(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i64(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i64> %2,
@@ -42,18 +42,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i8.nxv2i64(
+declare void @llvm.riscv.vsoxe.nxv2i8.nxv2i64(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i8.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i8.nxv2i64(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i64> %2,
@@ -62,19 +62,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i64(
+declare void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i64(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i64(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i64> %2,
@@ -84,18 +84,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i8.nxv4i64(
+declare void @llvm.riscv.vsoxe.nxv4i8.nxv4i64(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i8.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i8.nxv4i64(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i64> %2,
@@ -104,19 +104,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i64(
+declare void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i64(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i64(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i64> %2,
@@ -126,18 +126,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i8.nxv8i64(
+declare void @llvm.riscv.vsoxe.nxv8i8.nxv8i64(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i8.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i8.nxv8i64(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i64> %2,
@@ -146,19 +146,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i64(
+declare void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i64(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i64(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i64> %2,
@@ -168,18 +168,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i16.nxv1i64(
+declare void @llvm.riscv.vsoxe.nxv1i16.nxv1i64(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i16.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i16.nxv1i64(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i64> %2,
@@ -188,19 +188,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i64(
+declare void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i64(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i64(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i64> %2,
@@ -210,18 +210,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i16.nxv2i64(
+declare void @llvm.riscv.vsoxe.nxv2i16.nxv2i64(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i16.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i16.nxv2i64(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i64> %2,
@@ -230,19 +230,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i64(
+declare void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i64(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i64(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i64> %2,
@@ -252,18 +252,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i16.nxv4i64(
+declare void @llvm.riscv.vsoxe.nxv4i16.nxv4i64(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i16.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i16.nxv4i64(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i64> %2,
@@ -272,19 +272,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i64(
+declare void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i64(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i64(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i64> %2,
@@ -294,18 +294,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i16.nxv8i64(
+declare void @llvm.riscv.vsoxe.nxv8i16.nxv8i64(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i16.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i16.nxv8i64(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i64> %2,
@@ -314,19 +314,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i64(
+declare void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i64(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i64(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i64> %2,
@@ -336,18 +336,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i32.nxv1i64(
+declare void @llvm.riscv.vsoxe.nxv1i32.nxv1i64(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i32.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i32.nxv1i64(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i64> %2,
@@ -356,19 +356,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i64(
+declare void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i64(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i64(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i64> %2,
@@ -378,18 +378,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i32.nxv2i64(
+declare void @llvm.riscv.vsoxe.nxv2i32.nxv2i64(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i32.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i32.nxv2i64(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i64> %2,
@@ -398,19 +398,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i64(
+declare void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i64(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i64(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i64> %2,
@@ -420,18 +420,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i32.nxv4i64(
+declare void @llvm.riscv.vsoxe.nxv4i32.nxv4i64(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i32.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i32.nxv4i64(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i64> %2,
@@ -440,19 +440,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i64(
+declare void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i64(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i64(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i64> %2,
@@ -462,18 +462,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i32.nxv8i64(
+declare void @llvm.riscv.vsoxe.nxv8i32.nxv8i64(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i32.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i32.nxv8i64(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i64> %2,
@@ -482,19 +482,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i64(
+declare void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i64(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i64(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i64> %2,
@@ -504,18 +504,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i64.nxv1i64(
+declare void @llvm.riscv.vsoxe.nxv1i64.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>*,
   <vscale x 1 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i64_nxv1i64_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i64_nxv1i64_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i64.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i64> %2,
@@ -524,19 +524,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i64.nxv1i64(
+declare void @llvm.riscv.vsoxe.mask.nxv1i64.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>*,
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i64_nxv1i64_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i64_nxv1i64_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i64.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i64> %2,
@@ -546,18 +546,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i64.nxv2i64(
+declare void @llvm.riscv.vsoxe.nxv2i64.nxv2i64(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>*,
   <vscale x 2 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i64_nxv2i64_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i64_nxv2i64_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i64.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i64.nxv2i64(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64>* %1,
     <vscale x 2 x i64> %2,
@@ -566,19 +566,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i64.nxv2i64(
+declare void @llvm.riscv.vsoxe.mask.nxv2i64.nxv2i64(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>*,
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i64_nxv2i64_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i64_nxv2i64_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i64.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i64.nxv2i64(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64>* %1,
     <vscale x 2 x i64> %2,
@@ -588,18 +588,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i64.nxv4i64(
+declare void @llvm.riscv.vsoxe.nxv4i64.nxv4i64(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>*,
   <vscale x 4 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i64_nxv4i64_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i64_nxv4i64_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i64.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i64.nxv4i64(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64>* %1,
     <vscale x 4 x i64> %2,
@@ -608,19 +608,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i64.nxv4i64(
+declare void @llvm.riscv.vsoxe.mask.nxv4i64.nxv4i64(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>*,
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i64_nxv4i64_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i64_nxv4i64_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i64.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i64.nxv4i64(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64>* %1,
     <vscale x 4 x i64> %2,
@@ -630,18 +630,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i64.nxv8i64(
+declare void @llvm.riscv.vsoxe.nxv8i64.nxv8i64(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>*,
   <vscale x 8 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i64_nxv8i64_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i64_nxv8i64_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i64.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i64.nxv8i64(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64>* %1,
     <vscale x 8 x i64> %2,
@@ -650,19 +650,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i64.nxv8i64(
+declare void @llvm.riscv.vsoxe.mask.nxv8i64.nxv8i64(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>*,
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i64_nxv8i64_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i64_nxv8i64_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i64.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i64.nxv8i64(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64>* %1,
     <vscale x 8 x i64> %2,
@@ -672,18 +672,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f16.nxv1i64(
+declare void @llvm.riscv.vsoxe.nxv1f16.nxv1i64(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f16.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f16.nxv1i64(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i64> %2,
@@ -692,19 +692,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i64(
+declare void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i64(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i64(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i64> %2,
@@ -714,18 +714,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f16.nxv2i64(
+declare void @llvm.riscv.vsoxe.nxv2f16.nxv2i64(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f16.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f16.nxv2i64(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i64> %2,
@@ -734,19 +734,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i64(
+declare void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i64(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i64(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i64> %2,
@@ -756,18 +756,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f16.nxv4i64(
+declare void @llvm.riscv.vsoxe.nxv4f16.nxv4i64(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f16.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f16.nxv4i64(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i64> %2,
@@ -776,19 +776,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i64(
+declare void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i64(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i64(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i64> %2,
@@ -798,18 +798,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f16.nxv8i64(
+declare void @llvm.riscv.vsoxe.nxv8f16.nxv8i64(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f16.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f16.nxv8i64(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i64> %2,
@@ -818,19 +818,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i64(
+declare void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i64(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i64(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i64> %2,
@@ -840,18 +840,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f32.nxv1i64(
+declare void @llvm.riscv.vsoxe.nxv1f32.nxv1i64(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f32.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f32.nxv1i64(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i64> %2,
@@ -860,19 +860,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i64(
+declare void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i64(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i64(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i64> %2,
@@ -882,18 +882,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f32.nxv2i64(
+declare void @llvm.riscv.vsoxe.nxv2f32.nxv2i64(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f32.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f32.nxv2i64(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i64> %2,
@@ -902,19 +902,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i64(
+declare void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i64(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i64(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i64> %2,
@@ -924,18 +924,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f32.nxv4i64(
+declare void @llvm.riscv.vsoxe.nxv4f32.nxv4i64(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f32.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f32.nxv4i64(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i64> %2,
@@ -944,19 +944,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i64(
+declare void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i64(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i64(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i64> %2,
@@ -966,18 +966,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f32.nxv8i64(
+declare void @llvm.riscv.vsoxe.nxv8f32.nxv8i64(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f32.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f32.nxv8i64(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i64> %2,
@@ -986,19 +986,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i64(
+declare void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i64(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i64(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i64> %2,
@@ -1008,18 +1008,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f64.nxv1i64(
+declare void @llvm.riscv.vsoxe.nxv1f64.nxv1i64(
   <vscale x 1 x double>,
   <vscale x 1 x double>*,
   <vscale x 1 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f64_nxv1f64_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f64_nxv1f64_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f64.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f64.nxv1i64(
     <vscale x 1 x double> %0,
     <vscale x 1 x double>* %1,
     <vscale x 1 x i64> %2,
@@ -1028,19 +1028,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f64.nxv1i64(
+declare void @llvm.riscv.vsoxe.mask.nxv1f64.nxv1i64(
   <vscale x 1 x double>,
   <vscale x 1 x double>*,
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f64_nxv1f64_nxv1i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f64_nxv1f64_nxv1i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f64.nxv1i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f64.nxv1i64(
     <vscale x 1 x double> %0,
     <vscale x 1 x double>* %1,
     <vscale x 1 x i64> %2,
@@ -1050,18 +1050,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f64.nxv2i64(
+declare void @llvm.riscv.vsoxe.nxv2f64.nxv2i64(
   <vscale x 2 x double>,
   <vscale x 2 x double>*,
   <vscale x 2 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f64_nxv2f64_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f64_nxv2f64_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f64.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f64.nxv2i64(
     <vscale x 2 x double> %0,
     <vscale x 2 x double>* %1,
     <vscale x 2 x i64> %2,
@@ -1070,19 +1070,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f64.nxv2i64(
+declare void @llvm.riscv.vsoxe.mask.nxv2f64.nxv2i64(
   <vscale x 2 x double>,
   <vscale x 2 x double>*,
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f64_nxv2f64_nxv2i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f64_nxv2f64_nxv2i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f64.nxv2i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f64.nxv2i64(
     <vscale x 2 x double> %0,
     <vscale x 2 x double>* %1,
     <vscale x 2 x i64> %2,
@@ -1092,18 +1092,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f64.nxv4i64(
+declare void @llvm.riscv.vsoxe.nxv4f64.nxv4i64(
   <vscale x 4 x double>,
   <vscale x 4 x double>*,
   <vscale x 4 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f64_nxv4f64_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f64_nxv4f64_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f64.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f64.nxv4i64(
     <vscale x 4 x double> %0,
     <vscale x 4 x double>* %1,
     <vscale x 4 x i64> %2,
@@ -1112,19 +1112,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f64.nxv4i64(
+declare void @llvm.riscv.vsoxe.mask.nxv4f64.nxv4i64(
   <vscale x 4 x double>,
   <vscale x 4 x double>*,
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f64_nxv4f64_nxv4i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f64_nxv4f64_nxv4i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f64.nxv4i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f64.nxv4i64(
     <vscale x 4 x double> %0,
     <vscale x 4 x double>* %1,
     <vscale x 4 x i64> %2,
@@ -1134,18 +1134,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f64.nxv8i64(
+declare void @llvm.riscv.vsoxe.nxv8f64.nxv8i64(
   <vscale x 8 x double>,
   <vscale x 8 x double>*,
   <vscale x 8 x i64>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f64_nxv8f64_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f64_nxv8f64_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f64.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f64.nxv8i64(
     <vscale x 8 x double> %0,
     <vscale x 8 x double>* %1,
     <vscale x 8 x i64> %2,
@@ -1154,19 +1154,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f64.nxv8i64(
+declare void @llvm.riscv.vsoxe.mask.nxv8f64.nxv8i64(
   <vscale x 8 x double>,
   <vscale x 8 x double>*,
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f64_nxv8f64_nxv8i64
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f64_nxv8f64_nxv8i64
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f64.nxv8i64(
+; CHECK:       vsoxei64.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f64.nxv8i64(
     <vscale x 8 x double> %0,
     <vscale x 8 x double>* %1,
     <vscale x 8 x i64> %2,
@@ -1176,18 +1176,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i8.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1i8.nxv1i32(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i8.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i8.nxv1i32(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i32> %2,
@@ -1196,19 +1196,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i32(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i32(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i32> %2,
@@ -1218,18 +1218,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i8.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2i8.nxv2i32(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i8.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i8.nxv2i32(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i32> %2,
@@ -1238,19 +1238,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i32(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i32(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i32> %2,
@@ -1260,18 +1260,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i8.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4i8.nxv4i32(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i8.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i8.nxv4i32(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i32> %2,
@@ -1280,19 +1280,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i32(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i32(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i32> %2,
@@ -1302,18 +1302,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i8.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8i8.nxv8i32(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i8.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i8.nxv8i32(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i32> %2,
@@ -1322,19 +1322,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i32(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i32(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i32> %2,
@@ -1344,18 +1344,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i8.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16i8.nxv16i32(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i8.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i8.nxv16i32(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i32> %2,
@@ -1364,19 +1364,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i32(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i32(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i32> %2,
@@ -1386,18 +1386,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i16.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1i16.nxv1i32(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i16.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i16.nxv1i32(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i32> %2,
@@ -1406,19 +1406,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i32(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i32(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i32> %2,
@@ -1428,18 +1428,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i16.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2i16.nxv2i32(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i16.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i16.nxv2i32(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i32> %2,
@@ -1448,19 +1448,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i32(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i32(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i32> %2,
@@ -1470,18 +1470,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i16.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4i16.nxv4i32(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i16.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i16.nxv4i32(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i32> %2,
@@ -1490,19 +1490,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i32(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i32(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i32> %2,
@@ -1512,18 +1512,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i16.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8i16.nxv8i32(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i16.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i16.nxv8i32(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i32> %2,
@@ -1532,19 +1532,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i32(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i32(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i32> %2,
@@ -1554,18 +1554,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i16.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16i16.nxv16i32(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i16.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i16.nxv16i32(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i32> %2,
@@ -1574,19 +1574,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i32(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i32(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i32> %2,
@@ -1596,18 +1596,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i32.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1i32.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i32.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i32.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i32> %2,
@@ -1616,19 +1616,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i32> %2,
@@ -1638,18 +1638,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i32.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2i32.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i32.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i32.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i32> %2,
@@ -1658,19 +1658,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i32> %2,
@@ -1680,18 +1680,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i32.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4i32.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i32.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i32.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i32> %2,
@@ -1700,19 +1700,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i32> %2,
@@ -1722,18 +1722,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i32.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8i32.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i32.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i32.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i32> %2,
@@ -1742,19 +1742,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i32> %2,
@@ -1764,18 +1764,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i32.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16i32.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i32.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i32.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i32> %2,
@@ -1784,19 +1784,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i32> %2,
@@ -1806,18 +1806,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i64.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1i64.nxv1i32(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>*,
   <vscale x 1 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i64_nxv1i64_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i64_nxv1i64_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i64.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i64.nxv1i32(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i32> %2,
@@ -1826,19 +1826,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i64.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1i64.nxv1i32(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i64_nxv1i64_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i64_nxv1i64_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i64.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i64.nxv1i32(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i32> %2,
@@ -1848,18 +1848,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i64.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2i64.nxv2i32(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>*,
   <vscale x 2 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i64_nxv2i64_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i64_nxv2i64_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i64.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i64.nxv2i32(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64>* %1,
     <vscale x 2 x i32> %2,
@@ -1868,19 +1868,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i64.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2i64.nxv2i32(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i64_nxv2i64_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i64_nxv2i64_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i64.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i64.nxv2i32(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64>* %1,
     <vscale x 2 x i32> %2,
@@ -1890,18 +1890,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i64.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4i64.nxv4i32(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>*,
   <vscale x 4 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i64_nxv4i64_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i64_nxv4i64_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i64.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i64.nxv4i32(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64>* %1,
     <vscale x 4 x i32> %2,
@@ -1910,19 +1910,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i64.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4i64.nxv4i32(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i64_nxv4i64_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i64_nxv4i64_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i64.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i64.nxv4i32(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64>* %1,
     <vscale x 4 x i32> %2,
@@ -1932,18 +1932,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i64.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8i64.nxv8i32(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>*,
   <vscale x 8 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i64_nxv8i64_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i64_nxv8i64_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i64.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i64.nxv8i32(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64>* %1,
     <vscale x 8 x i32> %2,
@@ -1952,19 +1952,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i64.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8i64.nxv8i32(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i64_nxv8i64_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i64_nxv8i64_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i64.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i64.nxv8i32(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64>* %1,
     <vscale x 8 x i32> %2,
@@ -1974,18 +1974,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f16.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1f16.nxv1i32(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f16.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f16.nxv1i32(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i32> %2,
@@ -1994,19 +1994,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i32(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i32(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i32> %2,
@@ -2016,18 +2016,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f16.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2f16.nxv2i32(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f16.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f16.nxv2i32(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i32> %2,
@@ -2036,19 +2036,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i32(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i32(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i32> %2,
@@ -2058,18 +2058,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f16.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4f16.nxv4i32(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f16.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f16.nxv4i32(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i32> %2,
@@ -2078,19 +2078,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i32(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i32(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i32> %2,
@@ -2100,18 +2100,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f16.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8f16.nxv8i32(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f16.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f16.nxv8i32(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i32> %2,
@@ -2120,19 +2120,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i32(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i32(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i32> %2,
@@ -2142,18 +2142,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f16.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16f16.nxv16i32(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f16.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f16.nxv16i32(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i32> %2,
@@ -2162,19 +2162,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i32(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i32(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i32> %2,
@@ -2184,18 +2184,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f32.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1f32.nxv1i32(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f32.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f32.nxv1i32(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i32> %2,
@@ -2204,19 +2204,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i32(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i32(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i32> %2,
@@ -2226,18 +2226,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f32.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2f32.nxv2i32(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f32.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f32.nxv2i32(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i32> %2,
@@ -2246,19 +2246,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i32(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i32(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i32> %2,
@@ -2268,18 +2268,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f32.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4f32.nxv4i32(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f32.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f32.nxv4i32(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i32> %2,
@@ -2288,19 +2288,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i32(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i32(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i32> %2,
@@ -2310,18 +2310,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f32.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8f32.nxv8i32(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f32.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f32.nxv8i32(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i32> %2,
@@ -2330,19 +2330,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i32(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i32(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i32> %2,
@@ -2352,18 +2352,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f32.nxv16i32(
+declare void @llvm.riscv.vsoxe.nxv16f32.nxv16i32(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f32.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f32.nxv16i32(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i32> %2,
@@ -2372,19 +2372,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i32(
+declare void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i32(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i32(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i32> %2,
@@ -2394,18 +2394,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f64.nxv1i32(
+declare void @llvm.riscv.vsoxe.nxv1f64.nxv1i32(
   <vscale x 1 x double>,
   <vscale x 1 x double>*,
   <vscale x 1 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f64_nxv1f64_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f64_nxv1f64_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f64.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f64.nxv1i32(
     <vscale x 1 x double> %0,
     <vscale x 1 x double>* %1,
     <vscale x 1 x i32> %2,
@@ -2414,19 +2414,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f64.nxv1i32(
+declare void @llvm.riscv.vsoxe.mask.nxv1f64.nxv1i32(
   <vscale x 1 x double>,
   <vscale x 1 x double>*,
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f64_nxv1f64_nxv1i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f64_nxv1f64_nxv1i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f64.nxv1i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f64.nxv1i32(
     <vscale x 1 x double> %0,
     <vscale x 1 x double>* %1,
     <vscale x 1 x i32> %2,
@@ -2436,18 +2436,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f64.nxv2i32(
+declare void @llvm.riscv.vsoxe.nxv2f64.nxv2i32(
   <vscale x 2 x double>,
   <vscale x 2 x double>*,
   <vscale x 2 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f64_nxv2f64_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f64_nxv2f64_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f64.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f64.nxv2i32(
     <vscale x 2 x double> %0,
     <vscale x 2 x double>* %1,
     <vscale x 2 x i32> %2,
@@ -2456,19 +2456,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f64.nxv2i32(
+declare void @llvm.riscv.vsoxe.mask.nxv2f64.nxv2i32(
   <vscale x 2 x double>,
   <vscale x 2 x double>*,
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f64_nxv2f64_nxv2i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f64_nxv2f64_nxv2i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f64.nxv2i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f64.nxv2i32(
     <vscale x 2 x double> %0,
     <vscale x 2 x double>* %1,
     <vscale x 2 x i32> %2,
@@ -2478,18 +2478,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f64.nxv4i32(
+declare void @llvm.riscv.vsoxe.nxv4f64.nxv4i32(
   <vscale x 4 x double>,
   <vscale x 4 x double>*,
   <vscale x 4 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f64_nxv4f64_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f64_nxv4f64_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f64.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f64.nxv4i32(
     <vscale x 4 x double> %0,
     <vscale x 4 x double>* %1,
     <vscale x 4 x i32> %2,
@@ -2498,19 +2498,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f64.nxv4i32(
+declare void @llvm.riscv.vsoxe.mask.nxv4f64.nxv4i32(
   <vscale x 4 x double>,
   <vscale x 4 x double>*,
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f64_nxv4f64_nxv4i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f64_nxv4f64_nxv4i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f64.nxv4i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f64.nxv4i32(
     <vscale x 4 x double> %0,
     <vscale x 4 x double>* %1,
     <vscale x 4 x i32> %2,
@@ -2520,18 +2520,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f64.nxv8i32(
+declare void @llvm.riscv.vsoxe.nxv8f64.nxv8i32(
   <vscale x 8 x double>,
   <vscale x 8 x double>*,
   <vscale x 8 x i32>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f64_nxv8f64_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f64_nxv8f64_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f64.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f64.nxv8i32(
     <vscale x 8 x double> %0,
     <vscale x 8 x double>* %1,
     <vscale x 8 x i32> %2,
@@ -2540,19 +2540,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f64.nxv8i32(
+declare void @llvm.riscv.vsoxe.mask.nxv8f64.nxv8i32(
   <vscale x 8 x double>,
   <vscale x 8 x double>*,
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f64_nxv8f64_nxv8i32
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f64_nxv8f64_nxv8i32
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f64.nxv8i32(
+; CHECK:       vsoxei32.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f64.nxv8i32(
     <vscale x 8 x double> %0,
     <vscale x 8 x double>* %1,
     <vscale x 8 x i32> %2,
@@ -2562,18 +2562,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i8.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1i8.nxv1i16(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i8.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i8.nxv1i16(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i16> %2,
@@ -2582,19 +2582,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i16(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i16(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i16> %2,
@@ -2604,18 +2604,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i8.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2i8.nxv2i16(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i8.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i8.nxv2i16(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i16> %2,
@@ -2624,19 +2624,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i16(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i16(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i16> %2,
@@ -2646,18 +2646,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i8.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4i8.nxv4i16(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i8.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i8.nxv4i16(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i16> %2,
@@ -2666,19 +2666,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i16(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i16(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i16> %2,
@@ -2688,18 +2688,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i8.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8i8.nxv8i16(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i8.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i8.nxv8i16(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i16> %2,
@@ -2708,19 +2708,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i16(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i16(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i16> %2,
@@ -2730,18 +2730,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i8.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16i8.nxv16i16(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i8.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i8.nxv16i16(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i16> %2,
@@ -2750,19 +2750,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i16(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i16(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i16> %2,
@@ -2772,18 +2772,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32i8.nxv32i16(
+declare void @llvm.riscv.vsoxe.nxv32i8.nxv32i16(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>*,
   <vscale x 32 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32i8_nxv32i8_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32i8_nxv32i8_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32i8.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32i8.nxv32i16(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8>* %1,
     <vscale x 32 x i16> %2,
@@ -2792,19 +2792,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32i8.nxv32i16(
+declare void @llvm.riscv.vsoxe.mask.nxv32i8.nxv32i16(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>*,
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32i8_nxv32i8_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32i8_nxv32i8_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32i8.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32i8.nxv32i16(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8>* %1,
     <vscale x 32 x i16> %2,
@@ -2814,18 +2814,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i16.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1i16.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i16.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i16.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i16> %2,
@@ -2834,19 +2834,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i16> %2,
@@ -2856,18 +2856,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i16.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2i16.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i16.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i16.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i16> %2,
@@ -2876,19 +2876,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i16> %2,
@@ -2898,18 +2898,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i16.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4i16.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i16.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i16.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i16> %2,
@@ -2918,19 +2918,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i16> %2,
@@ -2940,18 +2940,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i16.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8i16.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i16.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i16.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i16> %2,
@@ -2960,19 +2960,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i16> %2,
@@ -2982,18 +2982,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i16.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16i16.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i16.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i16.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i16> %2,
@@ -3002,19 +3002,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i16> %2,
@@ -3024,18 +3024,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32i16.nxv32i16(
+declare void @llvm.riscv.vsoxe.nxv32i16.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>*,
   <vscale x 32 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32i16_nxv32i16_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32i16_nxv32i16_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32i16.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32i16.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16>* %1,
     <vscale x 32 x i16> %2,
@@ -3044,19 +3044,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32i16.nxv32i16(
+declare void @llvm.riscv.vsoxe.mask.nxv32i16.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>*,
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32i16_nxv32i16_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32i16_nxv32i16_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32i16.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32i16.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16>* %1,
     <vscale x 32 x i16> %2,
@@ -3066,18 +3066,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i32.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1i32.nxv1i16(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i32.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i32.nxv1i16(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i16> %2,
@@ -3086,19 +3086,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i16(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i16(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i16> %2,
@@ -3108,18 +3108,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i32.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2i32.nxv2i16(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i32.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i32.nxv2i16(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i16> %2,
@@ -3128,19 +3128,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i16(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i16(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i16> %2,
@@ -3150,18 +3150,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i32.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4i32.nxv4i16(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i32.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i32.nxv4i16(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i16> %2,
@@ -3170,19 +3170,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i16(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i16(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i16> %2,
@@ -3192,18 +3192,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i32.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8i32.nxv8i16(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i32.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i32.nxv8i16(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i16> %2,
@@ -3212,19 +3212,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i16(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i16(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i16> %2,
@@ -3234,18 +3234,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i32.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16i32.nxv16i16(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i32.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i32.nxv16i16(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i16> %2,
@@ -3254,19 +3254,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i16(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i16(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i16> %2,
@@ -3276,18 +3276,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i64.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1i64.nxv1i16(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>*,
   <vscale x 1 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i64_nxv1i64_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i64_nxv1i64_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i64.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i64.nxv1i16(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i16> %2,
@@ -3296,19 +3296,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i64.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1i64.nxv1i16(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i64_nxv1i64_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i64_nxv1i64_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i64.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i64.nxv1i16(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i16> %2,
@@ -3318,18 +3318,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i64.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2i64.nxv2i16(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>*,
   <vscale x 2 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i64_nxv2i64_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i64_nxv2i64_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i64.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i64.nxv2i16(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64>* %1,
     <vscale x 2 x i16> %2,
@@ -3338,19 +3338,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i64.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2i64.nxv2i16(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i64_nxv2i64_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i64_nxv2i64_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i64.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i64.nxv2i16(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64>* %1,
     <vscale x 2 x i16> %2,
@@ -3360,18 +3360,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i64.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4i64.nxv4i16(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>*,
   <vscale x 4 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i64_nxv4i64_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i64_nxv4i64_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i64.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i64.nxv4i16(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64>* %1,
     <vscale x 4 x i16> %2,
@@ -3380,19 +3380,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i64.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4i64.nxv4i16(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i64_nxv4i64_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i64_nxv4i64_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i64.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i64.nxv4i16(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64>* %1,
     <vscale x 4 x i16> %2,
@@ -3402,18 +3402,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i64.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8i64.nxv8i16(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>*,
   <vscale x 8 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i64_nxv8i64_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i64_nxv8i64_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i64.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i64.nxv8i16(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64>* %1,
     <vscale x 8 x i16> %2,
@@ -3422,19 +3422,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i64.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8i64.nxv8i16(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i64_nxv8i64_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i64_nxv8i64_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i64.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i64.nxv8i16(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64>* %1,
     <vscale x 8 x i16> %2,
@@ -3444,18 +3444,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f16.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1f16.nxv1i16(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f16.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f16.nxv1i16(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i16> %2,
@@ -3464,19 +3464,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i16(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i16(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i16> %2,
@@ -3486,18 +3486,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f16.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2f16.nxv2i16(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f16.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f16.nxv2i16(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i16> %2,
@@ -3506,19 +3506,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i16(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i16(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i16> %2,
@@ -3528,18 +3528,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f16.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4f16.nxv4i16(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f16.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f16.nxv4i16(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i16> %2,
@@ -3548,19 +3548,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i16(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i16(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i16> %2,
@@ -3570,18 +3570,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f16.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8f16.nxv8i16(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f16.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f16.nxv8i16(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i16> %2,
@@ -3590,19 +3590,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i16(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i16(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i16> %2,
@@ -3612,18 +3612,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f16.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16f16.nxv16i16(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f16.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f16.nxv16i16(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i16> %2,
@@ -3632,19 +3632,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i16(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i16(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i16> %2,
@@ -3654,18 +3654,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32f16.nxv32i16(
+declare void @llvm.riscv.vsoxe.nxv32f16.nxv32i16(
   <vscale x 32 x half>,
   <vscale x 32 x half>*,
   <vscale x 32 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32f16_nxv32f16_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32f16_nxv32f16_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32f16.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32f16.nxv32i16(
     <vscale x 32 x half> %0,
     <vscale x 32 x half>* %1,
     <vscale x 32 x i16> %2,
@@ -3674,19 +3674,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32f16.nxv32i16(
+declare void @llvm.riscv.vsoxe.mask.nxv32f16.nxv32i16(
   <vscale x 32 x half>,
   <vscale x 32 x half>*,
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32f16_nxv32f16_nxv32i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32f16_nxv32f16_nxv32i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32f16.nxv32i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32f16.nxv32i16(
     <vscale x 32 x half> %0,
     <vscale x 32 x half>* %1,
     <vscale x 32 x i16> %2,
@@ -3696,18 +3696,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f32.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1f32.nxv1i16(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f32.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f32.nxv1i16(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i16> %2,
@@ -3716,19 +3716,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i16(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i16(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i16> %2,
@@ -3738,18 +3738,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f32.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2f32.nxv2i16(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f32.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f32.nxv2i16(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i16> %2,
@@ -3758,19 +3758,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i16(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i16(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i16> %2,
@@ -3780,18 +3780,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f32.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4f32.nxv4i16(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f32.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f32.nxv4i16(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i16> %2,
@@ -3800,19 +3800,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i16(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i16(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i16> %2,
@@ -3822,18 +3822,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f32.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8f32.nxv8i16(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f32.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f32.nxv8i16(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i16> %2,
@@ -3842,19 +3842,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i16(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i16(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i16> %2,
@@ -3864,18 +3864,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f32.nxv16i16(
+declare void @llvm.riscv.vsoxe.nxv16f32.nxv16i16(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f32.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f32.nxv16i16(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i16> %2,
@@ -3884,19 +3884,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i16(
+declare void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i16(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i16(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i16> %2,
@@ -3906,18 +3906,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f64.nxv1i16(
+declare void @llvm.riscv.vsoxe.nxv1f64.nxv1i16(
   <vscale x 1 x double>,
   <vscale x 1 x double>*,
   <vscale x 1 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f64_nxv1f64_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f64_nxv1f64_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f64.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f64.nxv1i16(
     <vscale x 1 x double> %0,
     <vscale x 1 x double>* %1,
     <vscale x 1 x i16> %2,
@@ -3926,19 +3926,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f64.nxv1i16(
+declare void @llvm.riscv.vsoxe.mask.nxv1f64.nxv1i16(
   <vscale x 1 x double>,
   <vscale x 1 x double>*,
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f64_nxv1f64_nxv1i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f64_nxv1f64_nxv1i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f64.nxv1i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f64.nxv1i16(
     <vscale x 1 x double> %0,
     <vscale x 1 x double>* %1,
     <vscale x 1 x i16> %2,
@@ -3948,18 +3948,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f64.nxv2i16(
+declare void @llvm.riscv.vsoxe.nxv2f64.nxv2i16(
   <vscale x 2 x double>,
   <vscale x 2 x double>*,
   <vscale x 2 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f64_nxv2f64_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f64_nxv2f64_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f64.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f64.nxv2i16(
     <vscale x 2 x double> %0,
     <vscale x 2 x double>* %1,
     <vscale x 2 x i16> %2,
@@ -3968,19 +3968,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f64.nxv2i16(
+declare void @llvm.riscv.vsoxe.mask.nxv2f64.nxv2i16(
   <vscale x 2 x double>,
   <vscale x 2 x double>*,
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f64_nxv2f64_nxv2i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f64_nxv2f64_nxv2i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f64.nxv2i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f64.nxv2i16(
     <vscale x 2 x double> %0,
     <vscale x 2 x double>* %1,
     <vscale x 2 x i16> %2,
@@ -3990,18 +3990,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f64.nxv4i16(
+declare void @llvm.riscv.vsoxe.nxv4f64.nxv4i16(
   <vscale x 4 x double>,
   <vscale x 4 x double>*,
   <vscale x 4 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f64_nxv4f64_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f64_nxv4f64_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f64.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f64.nxv4i16(
     <vscale x 4 x double> %0,
     <vscale x 4 x double>* %1,
     <vscale x 4 x i16> %2,
@@ -4010,19 +4010,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f64.nxv4i16(
+declare void @llvm.riscv.vsoxe.mask.nxv4f64.nxv4i16(
   <vscale x 4 x double>,
   <vscale x 4 x double>*,
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f64_nxv4f64_nxv4i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f64_nxv4f64_nxv4i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f64.nxv4i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f64.nxv4i16(
     <vscale x 4 x double> %0,
     <vscale x 4 x double>* %1,
     <vscale x 4 x i16> %2,
@@ -4032,18 +4032,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f64.nxv8i16(
+declare void @llvm.riscv.vsoxe.nxv8f64.nxv8i16(
   <vscale x 8 x double>,
   <vscale x 8 x double>*,
   <vscale x 8 x i16>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f64_nxv8f64_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f64_nxv8f64_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f64.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f64.nxv8i16(
     <vscale x 8 x double> %0,
     <vscale x 8 x double>* %1,
     <vscale x 8 x i16> %2,
@@ -4052,19 +4052,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f64.nxv8i16(
+declare void @llvm.riscv.vsoxe.mask.nxv8f64.nxv8i16(
   <vscale x 8 x double>,
   <vscale x 8 x double>*,
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f64_nxv8f64_nxv8i16
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f64_nxv8f64_nxv8i16
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f64.nxv8i16(
+; CHECK:       vsoxei16.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f64.nxv8i16(
     <vscale x 8 x double> %0,
     <vscale x 8 x double>* %1,
     <vscale x 8 x i16> %2,
@@ -4074,18 +4074,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i8.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1i8.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i8_nxv1i8_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i8_nxv1i8_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i8.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i8.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i8> %2,
@@ -4094,19 +4094,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i8>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i8_nxv1i8_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i8_nxv1i8_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i8.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i8.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8>* %1,
     <vscale x 1 x i8> %2,
@@ -4116,18 +4116,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i8.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2i8.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i8_nxv2i8_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i8_nxv2i8_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i8.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i8.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i8> %2,
@@ -4136,19 +4136,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i8>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i8_nxv2i8_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i8_nxv2i8_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i8.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i8.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i8>* %1,
     <vscale x 2 x i8> %2,
@@ -4158,18 +4158,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i8.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4i8.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i8_nxv4i8_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i8_nxv4i8_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i8.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i8.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i8> %2,
@@ -4178,19 +4178,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i8>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i8_nxv4i8_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i8_nxv4i8_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i8.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i8.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i8>* %1,
     <vscale x 4 x i8> %2,
@@ -4200,18 +4200,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i8.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8i8.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i8_nxv8i8_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i8_nxv8i8_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i8.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i8.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i8> %2,
@@ -4220,19 +4220,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i8>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i8_nxv8i8_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i8_nxv8i8_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i8.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i8.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i8>* %1,
     <vscale x 8 x i8> %2,
@@ -4242,18 +4242,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i8.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16i8.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i8_nxv16i8_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i8_nxv16i8_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i8.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i8.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i8> %2,
@@ -4262,19 +4262,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i8>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i8_nxv16i8_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i8_nxv16i8_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i8.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i8.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i8>* %1,
     <vscale x 16 x i8> %2,
@@ -4284,18 +4284,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32i8.nxv32i8(
+declare void @llvm.riscv.vsoxe.nxv32i8.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>*,
   <vscale x 32 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32i8_nxv32i8_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32i8_nxv32i8_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32i8.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32i8.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8>* %1,
     <vscale x 32 x i8> %2,
@@ -4304,19 +4304,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32i8.nxv32i8(
+declare void @llvm.riscv.vsoxe.mask.nxv32i8.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i8>*,
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32i8_nxv32i8_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32i8_nxv32i8_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32i8.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32i8.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i8>* %1,
     <vscale x 32 x i8> %2,
@@ -4326,18 +4326,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv64i8.nxv64i8(
+declare void @llvm.riscv.vsoxe.nxv64i8.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>*,
   <vscale x 64 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv64i8_nxv64i8_nxv64i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv64i8_nxv64i8_nxv64i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv64i8.nxv64i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv64i8.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8>* %1,
     <vscale x 64 x i8> %2,
@@ -4346,19 +4346,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv64i8.nxv64i8(
+declare void @llvm.riscv.vsoxe.mask.nxv64i8.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i8>*,
   <vscale x 64 x i8>,
   <vscale x 64 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv64i8_nxv64i8_nxv64i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv64i8_nxv64i8_nxv64i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv64i8.nxv64i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv64i8.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i8>* %1,
     <vscale x 64 x i8> %2,
@@ -4368,18 +4368,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i16.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1i16.nxv1i8(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i16_nxv1i16_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i16_nxv1i16_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i16.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i16.nxv1i8(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i8> %2,
@@ -4388,19 +4388,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i8(
   <vscale x 1 x i16>,
   <vscale x 1 x i16>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i16_nxv1i16_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i16_nxv1i16_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i16.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i16.nxv1i8(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i16>* %1,
     <vscale x 1 x i8> %2,
@@ -4410,18 +4410,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i16.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2i16.nxv2i8(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i16_nxv2i16_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i16_nxv2i16_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i16.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i16.nxv2i8(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i8> %2,
@@ -4430,19 +4430,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i8(
   <vscale x 2 x i16>,
   <vscale x 2 x i16>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i16_nxv2i16_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i16_nxv2i16_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i16.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i16.nxv2i8(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i16>* %1,
     <vscale x 2 x i8> %2,
@@ -4452,18 +4452,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i16.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4i16.nxv4i8(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i16_nxv4i16_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i16_nxv4i16_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i16.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i16.nxv4i8(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i8> %2,
@@ -4472,19 +4472,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i8(
   <vscale x 4 x i16>,
   <vscale x 4 x i16>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i16_nxv4i16_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i16_nxv4i16_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i16.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i16.nxv4i8(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i16>* %1,
     <vscale x 4 x i8> %2,
@@ -4494,18 +4494,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i16.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8i16.nxv8i8(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i16_nxv8i16_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i16_nxv8i16_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i16.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i16.nxv8i8(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i8> %2,
@@ -4514,19 +4514,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i8(
   <vscale x 8 x i16>,
   <vscale x 8 x i16>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i16_nxv8i16_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i16_nxv8i16_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i16.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i16.nxv8i8(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i16>* %1,
     <vscale x 8 x i8> %2,
@@ -4536,18 +4536,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i16.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16i16.nxv16i8(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i16_nxv16i16_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i16_nxv16i16_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i16.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i16.nxv16i8(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i8> %2,
@@ -4556,19 +4556,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i8(
   <vscale x 16 x i16>,
   <vscale x 16 x i16>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i16_nxv16i16_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i16_nxv16i16_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i16.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i16.nxv16i8(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i16>* %1,
     <vscale x 16 x i8> %2,
@@ -4578,18 +4578,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32i16.nxv32i8(
+declare void @llvm.riscv.vsoxe.nxv32i16.nxv32i8(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>*,
   <vscale x 32 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32i16_nxv32i16_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32i16_nxv32i16_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32i16.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32i16.nxv32i8(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16>* %1,
     <vscale x 32 x i8> %2,
@@ -4598,19 +4598,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32i16.nxv32i8(
+declare void @llvm.riscv.vsoxe.mask.nxv32i16.nxv32i8(
   <vscale x 32 x i16>,
   <vscale x 32 x i16>*,
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32i16_nxv32i16_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32i16_nxv32i16_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32i16.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32i16.nxv32i8(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i16>* %1,
     <vscale x 32 x i8> %2,
@@ -4620,18 +4620,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i32.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1i32.nxv1i8(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i32_nxv1i32_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i32_nxv1i32_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i32.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i32.nxv1i8(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i8> %2,
@@ -4640,19 +4640,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i8(
   <vscale x 1 x i32>,
   <vscale x 1 x i32>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i32_nxv1i32_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i32_nxv1i32_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i32.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i32.nxv1i8(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i32>* %1,
     <vscale x 1 x i8> %2,
@@ -4662,18 +4662,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i32.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2i32.nxv2i8(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i32_nxv2i32_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i32_nxv2i32_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i32.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i32.nxv2i8(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i8> %2,
@@ -4682,19 +4682,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i8(
   <vscale x 2 x i32>,
   <vscale x 2 x i32>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i32_nxv2i32_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i32_nxv2i32_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i32.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i32.nxv2i8(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i32>* %1,
     <vscale x 2 x i8> %2,
@@ -4704,18 +4704,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i32.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4i32.nxv4i8(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i32_nxv4i32_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i32_nxv4i32_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i32.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i32.nxv4i8(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i8> %2,
@@ -4724,19 +4724,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i8(
   <vscale x 4 x i32>,
   <vscale x 4 x i32>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i32_nxv4i32_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i32_nxv4i32_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i32.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i32.nxv4i8(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i32>* %1,
     <vscale x 4 x i8> %2,
@@ -4746,18 +4746,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i32.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8i32.nxv8i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i32_nxv8i32_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i32_nxv8i32_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i32.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i32.nxv8i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i8> %2,
@@ -4766,19 +4766,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i8(
   <vscale x 8 x i32>,
   <vscale x 8 x i32>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i32_nxv8i32_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i32_nxv8i32_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i32.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i32.nxv8i8(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i32>* %1,
     <vscale x 8 x i8> %2,
@@ -4788,18 +4788,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16i32.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16i32.nxv16i8(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16i32_nxv16i32_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16i32_nxv16i32_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16i32.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16i32.nxv16i8(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i8> %2,
@@ -4808,19 +4808,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i8(
   <vscale x 16 x i32>,
   <vscale x 16 x i32>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16i32_nxv16i32_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16i32_nxv16i32_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16i32.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16i32.nxv16i8(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i32>* %1,
     <vscale x 16 x i8> %2,
@@ -4830,18 +4830,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1i64.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1i64.nxv1i8(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>*,
   <vscale x 1 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1i64_nxv1i64_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1i64_nxv1i64_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1i64.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1i64.nxv1i8(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i8> %2,
@@ -4850,19 +4850,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1i64.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1i64.nxv1i8(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1i64_nxv1i64_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1i64_nxv1i64_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1i64.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1i64.nxv1i8(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i8> %2,
@@ -4872,18 +4872,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2i64.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2i64.nxv2i8(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>*,
   <vscale x 2 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2i64_nxv2i64_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2i64_nxv2i64_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2i64.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2i64.nxv2i8(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64>* %1,
     <vscale x 2 x i8> %2,
@@ -4892,19 +4892,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2i64.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2i64.nxv2i8(
   <vscale x 2 x i64>,
   <vscale x 2 x i64>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2i64_nxv2i64_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2i64_nxv2i64_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2i64.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2i64.nxv2i8(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i64>* %1,
     <vscale x 2 x i8> %2,
@@ -4914,18 +4914,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4i64.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4i64.nxv4i8(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>*,
   <vscale x 4 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4i64_nxv4i64_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4i64_nxv4i64_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4i64.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4i64.nxv4i8(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64>* %1,
     <vscale x 4 x i8> %2,
@@ -4934,19 +4934,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4i64.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4i64.nxv4i8(
   <vscale x 4 x i64>,
   <vscale x 4 x i64>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4i64_nxv4i64_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4i64_nxv4i64_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4i64.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4i64.nxv4i8(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i64>* %1,
     <vscale x 4 x i8> %2,
@@ -4956,18 +4956,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8i64.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8i64.nxv8i8(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>*,
   <vscale x 8 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8i64_nxv8i64_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8i64_nxv8i64_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8i64.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8i64.nxv8i8(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64>* %1,
     <vscale x 8 x i8> %2,
@@ -4976,19 +4976,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8i64.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8i64.nxv8i8(
   <vscale x 8 x i64>,
   <vscale x 8 x i64>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8i64_nxv8i64_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8i64_nxv8i64_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8i64.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8i64.nxv8i8(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i64>* %1,
     <vscale x 8 x i8> %2,
@@ -4998,18 +4998,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f16.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1f16.nxv1i8(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f16_nxv1f16_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f16_nxv1f16_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f16.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f16.nxv1i8(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i8> %2,
@@ -5018,19 +5018,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i8(
   <vscale x 1 x half>,
   <vscale x 1 x half>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f16_nxv1f16_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f16_nxv1f16_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f16.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f16.nxv1i8(
     <vscale x 1 x half> %0,
     <vscale x 1 x half>* %1,
     <vscale x 1 x i8> %2,
@@ -5040,18 +5040,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f16.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2f16.nxv2i8(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f16_nxv2f16_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f16_nxv2f16_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f16.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f16.nxv2i8(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i8> %2,
@@ -5060,19 +5060,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i8(
   <vscale x 2 x half>,
   <vscale x 2 x half>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f16_nxv2f16_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f16_nxv2f16_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f16.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f16.nxv2i8(
     <vscale x 2 x half> %0,
     <vscale x 2 x half>* %1,
     <vscale x 2 x i8> %2,
@@ -5082,18 +5082,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f16.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4f16.nxv4i8(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f16_nxv4f16_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f16_nxv4f16_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f16.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f16.nxv4i8(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i8> %2,
@@ -5102,19 +5102,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i8(
   <vscale x 4 x half>,
   <vscale x 4 x half>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f16_nxv4f16_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f16_nxv4f16_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f16.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f16.nxv4i8(
     <vscale x 4 x half> %0,
     <vscale x 4 x half>* %1,
     <vscale x 4 x i8> %2,
@@ -5124,18 +5124,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f16.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8f16.nxv8i8(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f16_nxv8f16_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f16_nxv8f16_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f16.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f16.nxv8i8(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i8> %2,
@@ -5144,19 +5144,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i8(
   <vscale x 8 x half>,
   <vscale x 8 x half>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f16_nxv8f16_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f16_nxv8f16_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f16.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f16.nxv8i8(
     <vscale x 8 x half> %0,
     <vscale x 8 x half>* %1,
     <vscale x 8 x i8> %2,
@@ -5166,18 +5166,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f16.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16f16.nxv16i8(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f16_nxv16f16_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f16_nxv16f16_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f16.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f16.nxv16i8(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i8> %2,
@@ -5186,19 +5186,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i8(
   <vscale x 16 x half>,
   <vscale x 16 x half>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f16_nxv16f16_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f16_nxv16f16_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f16.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f16.nxv16i8(
     <vscale x 16 x half> %0,
     <vscale x 16 x half>* %1,
     <vscale x 16 x i8> %2,
@@ -5208,18 +5208,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv32f16.nxv32i8(
+declare void @llvm.riscv.vsoxe.nxv32f16.nxv32i8(
   <vscale x 32 x half>,
   <vscale x 32 x half>*,
   <vscale x 32 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv32f16_nxv32f16_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv32f16_nxv32f16_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv32f16.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv32f16.nxv32i8(
     <vscale x 32 x half> %0,
     <vscale x 32 x half>* %1,
     <vscale x 32 x i8> %2,
@@ -5228,19 +5228,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv32f16.nxv32i8(
+declare void @llvm.riscv.vsoxe.mask.nxv32f16.nxv32i8(
   <vscale x 32 x half>,
   <vscale x 32 x half>*,
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv32f16_nxv32f16_nxv32i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv32f16_nxv32f16_nxv32i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv32f16.nxv32i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv32f16.nxv32i8(
     <vscale x 32 x half> %0,
     <vscale x 32 x half>* %1,
     <vscale x 32 x i8> %2,
@@ -5250,18 +5250,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f32.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1f32.nxv1i8(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f32_nxv1f32_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f32_nxv1f32_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f32.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f32.nxv1i8(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i8> %2,
@@ -5270,19 +5270,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i8(
   <vscale x 1 x float>,
   <vscale x 1 x float>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f32_nxv1f32_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f32_nxv1f32_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f32.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f32.nxv1i8(
     <vscale x 1 x float> %0,
     <vscale x 1 x float>* %1,
     <vscale x 1 x i8> %2,
@@ -5292,18 +5292,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f32.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2f32.nxv2i8(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f32_nxv2f32_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f32_nxv2f32_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f32.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f32.nxv2i8(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i8> %2,
@@ -5312,19 +5312,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i8(
   <vscale x 2 x float>,
   <vscale x 2 x float>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f32_nxv2f32_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f32_nxv2f32_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f32.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f32.nxv2i8(
     <vscale x 2 x float> %0,
     <vscale x 2 x float>* %1,
     <vscale x 2 x i8> %2,
@@ -5334,18 +5334,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f32.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4f32.nxv4i8(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f32_nxv4f32_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f32_nxv4f32_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f32.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f32.nxv4i8(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i8> %2,
@@ -5354,19 +5354,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i8(
   <vscale x 4 x float>,
   <vscale x 4 x float>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f32_nxv4f32_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f32_nxv4f32_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f32.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f32.nxv4i8(
     <vscale x 4 x float> %0,
     <vscale x 4 x float>* %1,
     <vscale x 4 x i8> %2,
@@ -5376,18 +5376,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f32.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8f32.nxv8i8(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f32_nxv8f32_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f32_nxv8f32_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f32.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f32.nxv8i8(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i8> %2,
@@ -5396,19 +5396,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i8(
   <vscale x 8 x float>,
   <vscale x 8 x float>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f32_nxv8f32_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f32_nxv8f32_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f32.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f32.nxv8i8(
     <vscale x 8 x float> %0,
     <vscale x 8 x float>* %1,
     <vscale x 8 x i8> %2,
@@ -5418,18 +5418,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv16f32.nxv16i8(
+declare void @llvm.riscv.vsoxe.nxv16f32.nxv16i8(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv16f32_nxv16f32_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv16f32_nxv16f32_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv16f32.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv16f32.nxv16i8(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i8> %2,
@@ -5438,19 +5438,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i8(
+declare void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i8(
   <vscale x 16 x float>,
   <vscale x 16 x float>*,
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv16f32_nxv16f32_nxv16i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv16f32_nxv16f32_nxv16i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv16f32.nxv16i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv16f32.nxv16i8(
     <vscale x 16 x float> %0,
     <vscale x 16 x float>* %1,
     <vscale x 16 x i8> %2,
@@ -5460,18 +5460,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv1f64.nxv1i8(
+declare void @llvm.riscv.vsoxe.nxv1f64.nxv1i8(
   <vscale x 1 x double>,
   <vscale x 1 x double>*,
   <vscale x 1 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv1f64_nxv1f64_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv1f64_nxv1f64_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv1f64.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv1f64.nxv1i8(
     <vscale x 1 x double> %0,
     <vscale x 1 x double>* %1,
     <vscale x 1 x i8> %2,
@@ -5480,19 +5480,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv1f64.nxv1i8(
+declare void @llvm.riscv.vsoxe.mask.nxv1f64.nxv1i8(
   <vscale x 1 x double>,
   <vscale x 1 x double>*,
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv1f64_nxv1f64_nxv1i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv1f64_nxv1f64_nxv1i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv1f64.nxv1i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv1f64.nxv1i8(
     <vscale x 1 x double> %0,
     <vscale x 1 x double>* %1,
     <vscale x 1 x i8> %2,
@@ -5502,18 +5502,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv2f64.nxv2i8(
+declare void @llvm.riscv.vsoxe.nxv2f64.nxv2i8(
   <vscale x 2 x double>,
   <vscale x 2 x double>*,
   <vscale x 2 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv2f64_nxv2f64_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv2f64_nxv2f64_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv2f64.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv2f64.nxv2i8(
     <vscale x 2 x double> %0,
     <vscale x 2 x double>* %1,
     <vscale x 2 x i8> %2,
@@ -5522,19 +5522,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv2f64.nxv2i8(
+declare void @llvm.riscv.vsoxe.mask.nxv2f64.nxv2i8(
   <vscale x 2 x double>,
   <vscale x 2 x double>*,
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv2f64_nxv2f64_nxv2i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv2f64_nxv2f64_nxv2i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv2f64.nxv2i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv2f64.nxv2i8(
     <vscale x 2 x double> %0,
     <vscale x 2 x double>* %1,
     <vscale x 2 x i8> %2,
@@ -5544,18 +5544,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv4f64.nxv4i8(
+declare void @llvm.riscv.vsoxe.nxv4f64.nxv4i8(
   <vscale x 4 x double>,
   <vscale x 4 x double>*,
   <vscale x 4 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv4f64_nxv4f64_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv4f64_nxv4f64_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv4f64.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv4f64.nxv4i8(
     <vscale x 4 x double> %0,
     <vscale x 4 x double>* %1,
     <vscale x 4 x i8> %2,
@@ -5564,19 +5564,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv4f64.nxv4i8(
+declare void @llvm.riscv.vsoxe.mask.nxv4f64.nxv4i8(
   <vscale x 4 x double>,
   <vscale x 4 x double>*,
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv4f64_nxv4f64_nxv4i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv4f64_nxv4f64_nxv4i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv4f64.nxv4i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv4f64.nxv4i8(
     <vscale x 4 x double> %0,
     <vscale x 4 x double>* %1,
     <vscale x 4 x i8> %2,
@@ -5586,18 +5586,18 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.nxv8f64.nxv8i8(
+declare void @llvm.riscv.vsoxe.nxv8f64.nxv8i8(
   <vscale x 8 x double>,
   <vscale x 8 x double>*,
   <vscale x 8 x i8>,
   i64);
 
-define void @intrinsic_vsxe_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+define void @intrinsic_vsoxe_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_v_nxv8f64_nxv8f64_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_v_nxv8f64_nxv8f64_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
-  call void @llvm.riscv.vsxe.nxv8f64.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}
+  call void @llvm.riscv.vsoxe.nxv8f64.nxv8i8(
     <vscale x 8 x double> %0,
     <vscale x 8 x double>* %1,
     <vscale x 8 x i8> %2,
@@ -5606,19 +5606,19 @@
   ret void
 }
 
-declare void @llvm.riscv.vsxe.mask.nxv8f64.nxv8i8(
+declare void @llvm.riscv.vsoxe.mask.nxv8f64.nxv8i8(
   <vscale x 8 x double>,
   <vscale x 8 x double>*,
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   i64);
 
-define void @intrinsic_vsxe_mask_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define void @intrinsic_vsoxe_mask_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vsxe_mask_v_nxv8f64_nxv8f64_nxv8i8
+; CHECK-LABEL: intrinsic_vsoxe_mask_v_nxv8f64_nxv8f64_nxv8i8
 ; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
-; CHECK:       vsxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
-  call void @llvm.riscv.vsxe.mask.nxv8f64.nxv8i8(
+; CHECK:       vsoxei8.v {{v[0-9]+}}, (a0), {{v[0-9]+}}, v0.t
+  call void @llvm.riscv.vsoxe.mask.nxv8f64.nxv8i8(
     <vscale x 8 x double> %0,
     <vscale x 8 x double>* %1,
     <vscale x 8 x i8> %2,
diff --git a/llvm/test/MC/RISCV/rvv/aliases.s b/llvm/test/MC/RISCV/rvv/aliases.s
--- a/llvm/test/MC/RISCV/rvv/aliases.s
+++ b/llvm/test/MC/RISCV/rvv/aliases.s
@@ -54,6 +54,18 @@
 # ALIAS:    vmnot.m v0, v1                  # encoding: [0x57,0xa0,0x10,0x76]
 # NO-ALIAS: vmnand.mm       v0, v1, v1      # encoding: [0x57,0xa0,0x10,0x76]
 vmnot.m v0, v1
+# ALIAS:    vl1r.v          v0, (a0)        # encoding: [0x07,0x00,0x85,0x22]
+# NO-ALIAS: vl1re8.v        v0, (a0)        # encoding: [0x07,0x00,0x85,0x22]
+vl1r.v v0, (a0) 
+# ALIAS:    vl2r.v          v0, (a0)        # encoding: [0x07,0x00,0x85,0x42]
+# NO-ALIAS: vl2re8.v        v0, (a0)        # encoding: [0x07,0x00,0x85,0x42]
+vl2r.v v0, (a0) 
+# ALIAS:    vl4r.v          v0, (a0)        # encoding: [0x07,0x00,0x85,0x82]
+# NO-ALIAS: vl4re8.v        v0, (a0)        # encoding: [0x07,0x00,0x85,0x82]
+vl4r.v v0, (a0) 
+# ALIAS:    vl8r.v          v0, (a0)        # encoding: [0x07,0x00,0x85,0x02]
+# NO-ALIAS: vl8re8.v        v0, (a0)        # encoding: [0x07,0x00,0x85,0x02]
+vl8r.v v0, (a0) 
 # ALIAS:    vneg.v          v2, v1, v0.t    # encoding: [0x57,0x41,0x10,0x0c]
 # NO-ALIAS: vrsub.vx        v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0x0c]
 vneg.v v2, v1, v0.t 
diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s
--- a/llvm/test/MC/RISCV/rvv/load.s
+++ b/llvm/test/MC/RISCV/rvv/load.s
@@ -1,12 +1,12 @@
 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN:   --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
-# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN:   | llvm-objdump -d --mattr=+experimental-v - --riscv-no-aliases \
+# RUN:   | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vle8.v v8, (a0), v0.t
 # CHECK-INST: vle8.v v8, (a0), v0.t
@@ -296,104 +296,290 @@
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 b5 1a <unknown>
 
-vlxei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei8.v v8, (a0), v4, v0.t
+vluxei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 04 <unknown>
+
+vluxei8.v v8, (a0), v4
+# CHECK-INST: vluxei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 06 <unknown>
+
+vluxei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 04 <unknown>
+
+vluxei16.v v8, (a0), v4
+# CHECK-INST: vluxei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 06 <unknown>
+
+vluxei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 04 <unknown>
+
+vluxei32.v v8, (a0), v4
+# CHECK-INST: vluxei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 06 <unknown>
+
+vluxei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 04 <unknown>
+
+vluxei64.v v8, (a0), v4
+# CHECK-INST: vluxei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 06 <unknown>
+
+vloxei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxei8.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x04,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 45 0c <unknown>
 
-vlxei8.v v8, (a0), v4
-# CHECK-INST: vlxei8.v v8, (a0), v4
+vloxei8.v v8, (a0), v4
+# CHECK-INST: vloxei8.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x04,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 45 0e <unknown>
 
-vlxei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei16.v v8, (a0), v4, v0.t
+vloxei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxei16.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x54,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 45 0c <unknown>
 
-vlxei16.v v8, (a0), v4
-# CHECK-INST: vlxei16.v v8, (a0), v4
+vloxei16.v v8, (a0), v4
+# CHECK-INST: vloxei16.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x54,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 45 0e <unknown>
 
-vlxei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei32.v v8, (a0), v4, v0.t
+vloxei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxei32.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x64,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 45 0c <unknown>
 
-vlxei32.v v8, (a0), v4
-# CHECK-INST: vlxei32.v v8, (a0), v4
+vloxei32.v v8, (a0), v4
+# CHECK-INST: vloxei32.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x64,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 45 0e <unknown>
 
-vlxei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei64.v v8, (a0), v4, v0.t
+vloxei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxei64.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x74,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 45 0c <unknown>
 
-vlxei64.v v8, (a0), v4
-# CHECK-INST: vlxei64.v v8, (a0), v4
+vloxei64.v v8, (a0), v4
+# CHECK-INST: vloxei64.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 45 0e <unknown>
 
-vlxei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+vl1re8.v v8, (a0)
+# CHECK-INST: vl1re8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 22 <unknown>
+
+vl1re16.v v8, (a0)
+# CHECK-INST: vl1re16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 22 <unknown>
+
+vl1re32.v v8, (a0)
+# CHECK-INST: vl1re32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 22 <unknown>
+
+vl1re64.v v8, (a0)
+# CHECK-INST: vl1re64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 22 <unknown>
+
+vl1re128.v v8, (a0)
+# CHECK-INST: vl1re128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 32 <unknown>
+
+vl1re256.v v8, (a0)
+# CHECK-INST: vl1re256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 32 <unknown>
+
+vl1re512.v v8, (a0)
+# CHECK-INST: vl1re512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 32 <unknown>
+
+vl1re1024.v v8, (a0)
+# CHECK-INST: vl1re1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 32 <unknown>
+
+vl2re8.v v8, (a0)
+# CHECK-INST: vl2re8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 42 <unknown>
+
+vl2re16.v v8, (a0)
+# CHECK-INST: vl2re16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 42 <unknown>
+
+vl2re32.v v8, (a0)
+# CHECK-INST: vl2re32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 42 <unknown>
+
+vl2re64.v v8, (a0)
+# CHECK-INST: vl2re64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 42 <unknown>
+
+vl2re128.v v8, (a0)
+# CHECK-INST: vl2re128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 52 <unknown>
+
+vl2re256.v v8, (a0)
+# CHECK-INST: vl2re256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 52 <unknown>
+
+vl2re512.v v8, (a0)
+# CHECK-INST: vl2re512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 52 <unknown>
+
+vl2re1024.v v8, (a0)
+# CHECK-INST: vl2re1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x52]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+# CHECK-UNKNOWN: 07 74 85 52 <unknown>
 
-vlxei128.v v8, (a0), v4
-# CHECK-INST: vlxei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+vl4re8.v v8, (a0)
+# CHECK-INST: vl4re8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+# CHECK-UNKNOWN: 07 04 85 82 <unknown>
 
-vlxei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+vl4re16.v v8, (a0)
+# CHECK-INST: vl4re16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+# CHECK-UNKNOWN: 07 54 85 82 <unknown>
 
-vlxei256.v v8, (a0), v4
-# CHECK-INST: vlxei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+vl4re32.v v8, (a0)
+# CHECK-INST: vl4re32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+# CHECK-UNKNOWN: 07 64 85 82 <unknown>
 
-vlxei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+vl4re64.v v8, (a0)
+# CHECK-INST: vl4re64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+# CHECK-UNKNOWN: 07 74 85 82 <unknown>
 
-vlxei512.v v8, (a0), v4
-# CHECK-INST: vlxei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+vl4re128.v v8, (a0)
+# CHECK-INST: vl4re128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x92]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+# CHECK-UNKNOWN: 07 04 85 92 <unknown>
 
-vlxei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x1c]
+vl4re256.v v8, (a0)
+# CHECK-INST: vl4re256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x92]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 74 45 1c <unknown>
+# CHECK-UNKNOWN: 07 54 85 92 <unknown>
 
-vlxei1024.v v8, (a0), v4
-# CHECK-INST: vlxei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x1e]
+vl4re512.v v8, (a0)
+# CHECK-INST: vl4re512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x92]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 74 45 1e <unknown>
+# CHECK-UNKNOWN: 07 64 85 92 <unknown>
 
-vl1r.v v8, (a0)
-# CHECK-INST: vl1r.v v8, (a0)
+vl4re1024.v v8, (a0)
+# CHECK-INST: vl4re1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 92 <unknown>
+
+vl8re8.v v8, (a0)
+# CHECK-INST: vl8re8.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x85,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 85 02 <unknown>
+
+vl8re16.v v8, (a0)
+# CHECK-INST: vl8re16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 02 <unknown>
+
+vl8re32.v v8, (a0)
+# CHECK-INST: vl8re32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 02 <unknown>
+
+vl8re64.v v8, (a0)
+# CHECK-INST: vl8re64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 02 <unknown>
+
+vl8re128.v v8, (a0)
+# CHECK-INST: vl8re128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 12 <unknown>
+
+vl8re256.v v8, (a0)
+# CHECK-INST: vl8re256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 12 <unknown>
+
+vl8re512.v v8, (a0)
+# CHECK-INST: vl8re512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 12 <unknown>
+
+vl8re1024.v v8, (a0)
+# CHECK-INST: vl8re1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 12 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s
--- a/llvm/test/MC/RISCV/rvv/store.s
+++ b/llvm/test/MC/RISCV/rvv/store.s
@@ -1,12 +1,12 @@
 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN:   --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
-# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN:   | llvm-objdump -d --mattr=+experimental-v - --riscv-no-aliases \
+# RUN:   | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vse8.v v24, (a0), v0.t
 # CHECK-INST: vse8.v v24, (a0), v0.t
@@ -200,104 +200,122 @@
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c b5 1a <unknown>
 
-vsxei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei8.v v24, (a0), v4, v0.t
+vsuxei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 45 04 <unknown>
+
+vsuxei8.v v24, (a0), v4
+# CHECK-INST: vsuxei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 45 06 <unknown>
+
+vsuxei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 45 04 <unknown>
+
+vsuxei16.v v24, (a0), v4
+# CHECK-INST: vsuxei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 45 06 <unknown>
+
+vsuxei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 45 04 <unknown>
+
+vsuxei32.v v24, (a0), v4
+# CHECK-INST: vsuxei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 45 06 <unknown>
+
+vsuxei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 45 04 <unknown>
+
+vsuxei64.v v24, (a0), v4
+# CHECK-INST: vsuxei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 45 06 <unknown>
+
+vsoxei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxei8.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 45 0c <unknown>
 
-vsxei8.v v24, (a0), v4
-# CHECK-INST: vsxei8.v v24, (a0), v4
+vsoxei8.v v24, (a0), v4
+# CHECK-INST: vsoxei8.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 45 0e <unknown>
 
-vsxei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei16.v v24, (a0), v4, v0.t
+vsoxei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxei16.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 45 0c <unknown>
 
-vsxei16.v v24, (a0), v4
-# CHECK-INST: vsxei16.v v24, (a0), v4
+vsoxei16.v v24, (a0), v4
+# CHECK-INST: vsoxei16.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 45 0e <unknown>
 
-vsxei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei32.v v24, (a0), v4, v0.t
+vsoxei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxei32.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 45 0c <unknown>
 
-vsxei32.v v24, (a0), v4
-# CHECK-INST: vsxei32.v v24, (a0), v4
+vsoxei32.v v24, (a0), v4
+# CHECK-INST: vsoxei32.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 45 0e <unknown>
 
-vsxei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei64.v v24, (a0), v4, v0.t
+vsoxei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxei64.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 45 0c <unknown>
 
-vsxei64.v v24, (a0), v4
-# CHECK-INST: vsxei64.v v24, (a0), v4
+vsoxei64.v v24, (a0), v4
+# CHECK-INST: vsoxei64.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 45 0e <unknown>
 
-vsxei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x1c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 0c 45 1c <unknown>
-
-vsxei128.v v24, (a0), v4
-# CHECK-INST: vsxei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x1e]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 0c 45 1e <unknown>
-
-vsxei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x1c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 5c 45 1c <unknown>
-
-vsxei256.v v24, (a0), v4
-# CHECK-INST: vsxei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x1e]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 5c 45 1e <unknown>
-
-vsxei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x1c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 6c 45 1c <unknown>
-
-vsxei512.v v24, (a0), v4
-# CHECK-INST: vsxei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x1e]
+vs1r.v v24, (a0)
+# CHECK-INST: vs1r.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x22]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 6c 45 1e <unknown>
+# CHECK-UNKNOWN: 27 0c 85 22 <unknown>
 
-vsxei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x1c]
+vs2r.v v24, (a0)
+# CHECK-INST: vs2r.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x42]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 7c 45 1c <unknown>
+# CHECK-UNKNOWN: 27 0c 85 42 <unknown>
 
-vsxei1024.v v24, (a0), v4
-# CHECK-INST: vsxei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x1e]
+vs4r.v v24, (a0)
+# CHECK-INST: vs4r.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 7c 45 1e <unknown>
+# CHECK-UNKNOWN: 27 0c 85 82 <unknown>
 
-vs1r.v v24, (a0)
-# CHECK-INST: vs1r.v v24, (a0)
+vs8r.v v24, (a0)
+# CHECK-INST: vs8r.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x0c,0x85,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 85 02 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvlsseg.s b/llvm/test/MC/RISCV/rvv/zvlsseg.s
--- a/llvm/test/MC/RISCV/rvv/zvlsseg.s
+++ b/llvm/test/MC/RISCV/rvv/zvlsseg.s
@@ -1,4713 +1,4717 @@
-# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvlsseg %s \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:   --mattr=+experimental-zvlsseg --riscv-no-aliases \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvlsseg %s \
-# RUN:        | llvm-objdump -d --mattr=+experimental-zvlsseg - \
-# RUN:        | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvlsseg %s \
-# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \
+# RUN:   --mattr=+experimental-zvlsseg %s \
+# RUN:   | llvm-objdump -d --mattr=+experimental-v --mattr=+experimental-zvlsseg \
+# RUN:   --riscv-no-aliases - \
+# RUN:   | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \
+# RUN:   --mattr=+experimental-zvlsseg %s \
+# RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vlseg2e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 20 <unknown>
 
 vlseg2e8.v v8, (a0)
 # CHECK-INST: vlseg2e8.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 22 <unknown>
 
+vlseg2e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 20 <unknown>
+
 vlseg2e16.v v8, (a0)
 # CHECK-INST: vlseg2e16.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 22 <unknown>
 
+vlseg2e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 20 <unknown>
+
 vlseg2e32.v v8, (a0)
 # CHECK-INST: vlseg2e32.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 22 <unknown>
 
+vlseg2e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 20 <unknown>
+
 vlseg2e64.v v8, (a0)
 # CHECK-INST: vlseg2e64.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 22 <unknown>
 
+vlseg2e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 30 <unknown>
+
 vlseg2e128.v v8, (a0)
 # CHECK-INST: vlseg2e128.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 32 <unknown>
 
+vlseg2e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 30 <unknown>
+
 vlseg2e256.v v8, (a0)
 # CHECK-INST: vlseg2e256.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 32 <unknown>
 
+vlseg2e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 30 <unknown>
+
 vlseg2e512.v v8, (a0)
 # CHECK-INST: vlseg2e512.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 32 <unknown>
 
+vlseg2e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 30 <unknown>
+
 vlseg2e1024.v v8, (a0)
 # CHECK-INST: vlseg2e1024.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 32 <unknown>
 
-vlseg2e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 20 <unknown>
+vlseg2e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 21 <unknown>
 
-vlseg2e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 20 <unknown>
+vlseg2e8ff.v v8, (a0)
+# CHECK-INST: vlseg2e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 23 <unknown>
 
-vlseg2e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 20 <unknown>
+vlseg2e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 21 <unknown>
 
-vlseg2e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 20 <unknown>
+vlseg2e16ff.v v8, (a0)
+# CHECK-INST: vlseg2e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 23 <unknown>
 
-vlseg2e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 30 <unknown>
+vlseg2e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 21 <unknown>
 
-vlseg2e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 30 <unknown>
+vlseg2e32ff.v v8, (a0)
+# CHECK-INST: vlseg2e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 23 <unknown>
 
-vlseg2e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 30 <unknown>
+vlseg2e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 21 <unknown>
 
-vlseg2e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 30 <unknown>
+vlseg2e64ff.v v8, (a0)
+# CHECK-INST: vlseg2e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 23 <unknown>
 
-vlseg3e8.v v8, (a0)
-# CHECK-INST: vlseg3e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 42 <unknown>
+vlseg2e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 31 <unknown>
 
-vlseg3e16.v v8, (a0)
-# CHECK-INST: vlseg3e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 42 <unknown>
+vlseg2e128ff.v v8, (a0)
+# CHECK-INST: vlseg2e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 33 <unknown>
 
-vlseg3e32.v v8, (a0)
-# CHECK-INST: vlseg3e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 42 <unknown>
+vlseg2e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 31 <unknown>
 
-vlseg3e64.v v8, (a0)
-# CHECK-INST: vlseg3e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 42 <unknown>
+vlseg2e256ff.v v8, (a0)
+# CHECK-INST: vlseg2e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 33 <unknown>
 
-vlseg3e128.v v8, (a0)
-# CHECK-INST: vlseg3e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 52 <unknown>
+vlseg2e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 31 <unknown>
 
-vlseg3e256.v v8, (a0)
-# CHECK-INST: vlseg3e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 52 <unknown>
+vlseg2e512ff.v v8, (a0)
+# CHECK-INST: vlseg2e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 33 <unknown>
 
-vlseg3e512.v v8, (a0)
-# CHECK-INST: vlseg3e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 52 <unknown>
+vlseg2e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 31 <unknown>
 
-vlseg3e1024.v v8, (a0)
-# CHECK-INST: vlseg3e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 52 <unknown>
+vlseg2e1024ff.v v8, (a0)
+# CHECK-INST: vlseg2e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 33 <unknown>
 
-vlseg3e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 40 <unknown>
+vlsseg2e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 28 <unknown>
 
-vlseg3e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 40 <unknown>
+vlsseg2e8.v v8, (a0), a1
+# CHECK-INST: vlsseg2e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 2a <unknown>
 
-vlseg3e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 40 <unknown>
+vlsseg2e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 28 <unknown>
 
-vlseg3e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 40 <unknown>
+vlsseg2e16.v v8, (a0), a1
+# CHECK-INST: vlsseg2e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 2a <unknown>
 
-vlseg3e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 50 <unknown>
+vlsseg2e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 28 <unknown>
 
-vlseg3e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 50 <unknown>
+vlsseg2e32.v v8, (a0), a1
+# CHECK-INST: vlsseg2e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 2a <unknown>
 
-vlseg3e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 50 <unknown>
+vlsseg2e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 28 <unknown>
 
-vlseg3e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 50 <unknown>
+vlsseg2e64.v v8, (a0), a1
+# CHECK-INST: vlsseg2e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 2a <unknown>
 
-vlseg4e8.v v8, (a0)
-# CHECK-INST: vlseg4e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 62 <unknown>
+vlsseg2e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 38 <unknown>
 
-vlseg4e16.v v8, (a0)
-# CHECK-INST: vlseg4e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 62 <unknown>
+vlsseg2e128.v v8, (a0), a1
+# CHECK-INST: vlsseg2e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 3a <unknown>
 
-vlseg4e32.v v8, (a0)
-# CHECK-INST: vlseg4e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 62 <unknown>
+vlsseg2e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 38 <unknown>
 
-vlseg4e64.v v8, (a0)
-# CHECK-INST: vlseg4e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 62 <unknown>
+vlsseg2e256.v v8, (a0), a1
+# CHECK-INST: vlsseg2e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 3a <unknown>
 
-vlseg4e128.v v8, (a0)
-# CHECK-INST: vlseg4e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 72 <unknown>
+vlsseg2e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 38 <unknown>
 
-vlseg4e256.v v8, (a0)
-# CHECK-INST: vlseg4e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 72 <unknown>
+vlsseg2e512.v v8, (a0), a1
+# CHECK-INST: vlsseg2e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 3a <unknown>
 
-vlseg4e512.v v8, (a0)
-# CHECK-INST: vlseg4e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 72 <unknown>
+vlsseg2e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 38 <unknown>
 
-vlseg4e1024.v v8, (a0)
-# CHECK-INST: vlseg4e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 72 <unknown>
+vlsseg2e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg2e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 3a <unknown>
 
-vlseg4e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 60 <unknown>
+vluxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 24 <unknown>
+
+vluxseg2ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg2ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 26 <unknown>
+
+vluxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 24 <unknown>
+
+vluxseg2ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg2ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 26 <unknown>
+
+vluxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 24 <unknown>
+
+vluxseg2ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg2ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 26 <unknown>
+
+vluxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 24 <unknown>
+
+vluxseg2ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg2ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 26 <unknown>
+
+vloxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 2c <unknown>
 
-vlseg4e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 60 <unknown>
+vloxseg2ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg2ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 2e <unknown>
 
-vlseg4e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 60 <unknown>
+vloxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 2c <unknown>
 
-vlseg4e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 60 <unknown>
+vloxseg2ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg2ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 2e <unknown>
 
-vlseg4e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 70 <unknown>
+vloxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 2c <unknown>
 
-vlseg4e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 70 <unknown>
+vloxseg2ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg2ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 2e <unknown>
 
-vlseg4e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 70 <unknown>
+vloxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 2c <unknown>
 
-vlseg4e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 70 <unknown>
+vloxseg2ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg2ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 2e <unknown>
 
-vlseg5e8.v v8, (a0)
-# CHECK-INST: vlseg5e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 82 <unknown>
+vlseg3e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 40 <unknown>
 
-vlseg5e16.v v8, (a0)
-# CHECK-INST: vlseg5e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 82 <unknown>
+vlseg3e8.v v8, (a0)
+# CHECK-INST: vlseg3e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 42 <unknown>
 
-vlseg5e32.v v8, (a0)
-# CHECK-INST: vlseg5e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 82 <unknown>
+vlseg3e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 40 <unknown>
 
-vlseg5e64.v v8, (a0)
-# CHECK-INST: vlseg5e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 82 <unknown>
+vlseg3e16.v v8, (a0)
+# CHECK-INST: vlseg3e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 42 <unknown>
 
-vlseg5e128.v v8, (a0)
-# CHECK-INST: vlseg5e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 92 <unknown>
+vlseg3e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 40 <unknown>
 
-vlseg5e256.v v8, (a0)
-# CHECK-INST: vlseg5e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 92 <unknown>
+vlseg3e32.v v8, (a0)
+# CHECK-INST: vlseg3e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 42 <unknown>
 
-vlseg5e512.v v8, (a0)
-# CHECK-INST: vlseg5e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 92 <unknown>
+vlseg3e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 40 <unknown>
 
-vlseg5e1024.v v8, (a0)
-# CHECK-INST: vlseg5e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 92 <unknown>
+vlseg3e64.v v8, (a0)
+# CHECK-INST: vlseg3e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 42 <unknown>
 
-vlseg5e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 80 <unknown>
+vlseg3e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 50 <unknown>
 
-vlseg5e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 80 <unknown>
+vlseg3e128.v v8, (a0)
+# CHECK-INST: vlseg3e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 52 <unknown>
 
-vlseg5e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 80 <unknown>
+vlseg3e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 50 <unknown>
 
-vlseg5e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 80 <unknown>
+vlseg3e256.v v8, (a0)
+# CHECK-INST: vlseg3e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 52 <unknown>
 
-vlseg5e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 90 <unknown>
+vlseg3e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 50 <unknown>
 
-vlseg5e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 90 <unknown>
+vlseg3e512.v v8, (a0)
+# CHECK-INST: vlseg3e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 52 <unknown>
 
-vlseg5e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 90 <unknown>
+vlseg3e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 50 <unknown>
 
-vlseg5e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 90 <unknown>
+vlseg3e1024.v v8, (a0)
+# CHECK-INST: vlseg3e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 52 <unknown>
 
-vlseg6e8.v v8, (a0)
-# CHECK-INST: vlseg6e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 a2 <unknown>
+vlseg3e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 41 <unknown>
 
-vlseg6e16.v v8, (a0)
-# CHECK-INST: vlseg6e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 a2 <unknown>
+vlseg3e8ff.v v8, (a0)
+# CHECK-INST: vlseg3e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 43 <unknown>
 
-vlseg6e32.v v8, (a0)
-# CHECK-INST: vlseg6e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 a2 <unknown>
+vlseg3e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 41 <unknown>
 
-vlseg6e64.v v8, (a0)
-# CHECK-INST: vlseg6e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 a2 <unknown>
+vlseg3e16ff.v v8, (a0)
+# CHECK-INST: vlseg3e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 43 <unknown>
 
-vlseg6e128.v v8, (a0)
-# CHECK-INST: vlseg6e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 b2 <unknown>
+vlseg3e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 41 <unknown>
 
-vlseg6e256.v v8, (a0)
-# CHECK-INST: vlseg6e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 b2 <unknown>
+vlseg3e32ff.v v8, (a0)
+# CHECK-INST: vlseg3e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 43 <unknown>
 
-vlseg6e512.v v8, (a0)
-# CHECK-INST: vlseg6e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 b2 <unknown>
+vlseg3e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 41 <unknown>
 
-vlseg6e1024.v v8, (a0)
-# CHECK-INST: vlseg6e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 b2 <unknown>
+vlseg3e64ff.v v8, (a0)
+# CHECK-INST: vlseg3e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 43 <unknown>
 
-vlseg6e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 a0 <unknown>
+vlseg3e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 51 <unknown>
 
-vlseg6e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 a0 <unknown>
+vlseg3e128ff.v v8, (a0)
+# CHECK-INST: vlseg3e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 53 <unknown>
 
-vlseg6e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 a0 <unknown>
+vlseg3e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 51 <unknown>
 
-vlseg6e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 a0 <unknown>
+vlseg3e256ff.v v8, (a0)
+# CHECK-INST: vlseg3e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 53 <unknown>
 
-vlseg6e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 b0 <unknown>
+vlseg3e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 51 <unknown>
 
-vlseg6e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 b0 <unknown>
+vlseg3e512ff.v v8, (a0)
+# CHECK-INST: vlseg3e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 53 <unknown>
 
-vlseg6e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 b0 <unknown>
+vlseg3e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 51 <unknown>
 
-vlseg6e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 b0 <unknown>
+vlseg3e1024ff.v v8, (a0)
+# CHECK-INST: vlseg3e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 53 <unknown>
 
-vlseg7e8.v v8, (a0)
-# CHECK-INST: vlseg7e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 c2 <unknown>
+vlsseg3e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 48 <unknown>
 
-vlseg7e16.v v8, (a0)
-# CHECK-INST: vlseg7e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 c2 <unknown>
+vlsseg3e8.v v8, (a0), a1
+# CHECK-INST: vlsseg3e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 4a <unknown>
 
-vlseg7e32.v v8, (a0)
-# CHECK-INST: vlseg7e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 c2 <unknown>
+vlsseg3e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 48 <unknown>
 
-vlseg7e64.v v8, (a0)
-# CHECK-INST: vlseg7e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 c2 <unknown>
+vlsseg3e16.v v8, (a0), a1
+# CHECK-INST: vlsseg3e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 4a <unknown>
 
-vlseg7e128.v v8, (a0)
-# CHECK-INST: vlseg7e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 d2 <unknown>
+vlsseg3e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 48 <unknown>
 
-vlseg7e256.v v8, (a0)
-# CHECK-INST: vlseg7e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 d2 <unknown>
+vlsseg3e32.v v8, (a0), a1
+# CHECK-INST: vlsseg3e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 4a <unknown>
 
-vlseg7e512.v v8, (a0)
-# CHECK-INST: vlseg7e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 d2 <unknown>
+vlsseg3e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 48 <unknown>
 
-vlseg7e1024.v v8, (a0)
-# CHECK-INST: vlseg7e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 d2 <unknown>
+vlsseg3e64.v v8, (a0), a1
+# CHECK-INST: vlsseg3e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 4a <unknown>
 
-vlseg7e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 c0 <unknown>
+vlsseg3e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 58 <unknown>
 
-vlseg7e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 c0 <unknown>
+vlsseg3e128.v v8, (a0), a1
+# CHECK-INST: vlsseg3e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 5a <unknown>
 
-vlseg7e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 c0 <unknown>
+vlsseg3e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 58 <unknown>
 
-vlseg7e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 c0 <unknown>
+vlsseg3e256.v v8, (a0), a1
+# CHECK-INST: vlsseg3e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 5a <unknown>
 
-vlseg7e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 d0 <unknown>
+vlsseg3e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 58 <unknown>
 
-vlseg7e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 d0 <unknown>
+vlsseg3e512.v v8, (a0), a1
+# CHECK-INST: vlsseg3e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 5a <unknown>
 
-vlseg7e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 d0 <unknown>
+vlsseg3e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 58 <unknown>
 
-vlseg7e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 d0 <unknown>
+vlsseg3e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg3e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 5a <unknown>
 
-vlseg8e8.v v8, (a0)
-# CHECK-INST: vlseg8e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 e2 <unknown>
+vluxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 44 <unknown>
+
+vluxseg3ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg3ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 46 <unknown>
+
+vluxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 44 <unknown>
+
+vluxseg3ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg3ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 46 <unknown>
+
+vluxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 44 <unknown>
+
+vluxseg3ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg3ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 46 <unknown>
+
+vluxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 44 <unknown>
+
+vluxseg3ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg3ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 46 <unknown>
+
+vloxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 4c <unknown>
 
-vlseg8e16.v v8, (a0)
-# CHECK-INST: vlseg8e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 e2 <unknown>
+vloxseg3ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg3ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 4e <unknown>
 
-vlseg8e32.v v8, (a0)
-# CHECK-INST: vlseg8e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 e2 <unknown>
+vloxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 4c <unknown>
 
-vlseg8e64.v v8, (a0)
-# CHECK-INST: vlseg8e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 e2 <unknown>
+vloxseg3ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg3ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 4e <unknown>
 
-vlseg8e128.v v8, (a0)
-# CHECK-INST: vlseg8e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 f2 <unknown>
+vloxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 4c <unknown>
 
-vlseg8e256.v v8, (a0)
-# CHECK-INST: vlseg8e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 f2 <unknown>
+vloxseg3ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg3ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 4e <unknown>
 
-vlseg8e512.v v8, (a0)
-# CHECK-INST: vlseg8e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 f2 <unknown>
+vloxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 4c <unknown>
 
-vlseg8e1024.v v8, (a0)
-# CHECK-INST: vlseg8e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 f2 <unknown>
+vloxseg3ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg3ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 4e <unknown>
 
-vlseg8e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 e0 <unknown>
+vlseg4e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 60 <unknown>
 
-vlseg8e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 e0 <unknown>
+vlseg4e8.v v8, (a0)
+# CHECK-INST: vlseg4e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 62 <unknown>
 
-vlseg8e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 e0 <unknown>
+vlseg4e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 60 <unknown>
 
-vlseg8e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 e0 <unknown>
+vlseg4e16.v v8, (a0)
+# CHECK-INST: vlseg4e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 62 <unknown>
 
-vlseg8e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 f0 <unknown>
+vlseg4e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 60 <unknown>
 
-vlseg8e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 f0 <unknown>
+vlseg4e32.v v8, (a0)
+# CHECK-INST: vlseg4e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 62 <unknown>
 
-vlseg8e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 f0 <unknown>
+vlseg4e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 60 <unknown>
 
-vlseg8e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 f0 <unknown>
+vlseg4e64.v v8, (a0)
+# CHECK-INST: vlseg4e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 62 <unknown>
 
-vlsseg2e8.v v8, (a0), a1
-# CHECK-INST: vlsseg2e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 2a <unknown>
+vlseg4e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 70 <unknown>
 
-vlsseg2e16.v v8, (a0), a1
-# CHECK-INST: vlsseg2e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 2a <unknown>
+vlseg4e128.v v8, (a0)
+# CHECK-INST: vlseg4e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 72 <unknown>
 
-vlsseg2e32.v v8, (a0), a1
-# CHECK-INST: vlsseg2e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 2a <unknown>
+vlseg4e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 70 <unknown>
 
-vlsseg2e64.v v8, (a0), a1
-# CHECK-INST: vlsseg2e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 2a <unknown>
+vlseg4e256.v v8, (a0)
+# CHECK-INST: vlseg4e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 72 <unknown>
 
-vlsseg2e128.v v8, (a0), a1
-# CHECK-INST: vlsseg2e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 3a <unknown>
+vlseg4e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 70 <unknown>
 
-vlsseg2e256.v v8, (a0), a1
-# CHECK-INST: vlsseg2e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 3a <unknown>
+vlseg4e512.v v8, (a0)
+# CHECK-INST: vlseg4e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 72 <unknown>
 
-vlsseg2e512.v v8, (a0), a1
-# CHECK-INST: vlsseg2e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 3a <unknown>
+vlseg4e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 70 <unknown>
 
-vlsseg2e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg2e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 3a <unknown>
+vlseg4e1024.v v8, (a0)
+# CHECK-INST: vlseg4e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 72 <unknown>
 
-vlsseg2e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 28 <unknown>
+vlseg4e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 61 <unknown>
 
-vlsseg2e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 28 <unknown>
+vlseg4e8ff.v v8, (a0)
+# CHECK-INST: vlseg4e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 63 <unknown>
 
-vlsseg2e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 28 <unknown>
+vlseg4e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 61 <unknown>
 
-vlsseg2e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 28 <unknown>
+vlseg4e16ff.v v8, (a0)
+# CHECK-INST: vlseg4e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 63 <unknown>
 
-vlsseg2e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 38 <unknown>
+vlseg4e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 61 <unknown>
 
-vlsseg2e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 38 <unknown>
+vlseg4e32ff.v v8, (a0)
+# CHECK-INST: vlseg4e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 63 <unknown>
 
-vlsseg2e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 38 <unknown>
+vlseg4e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 61 <unknown>
 
-vlsseg2e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 38 <unknown>
+vlseg4e64ff.v v8, (a0)
+# CHECK-INST: vlseg4e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 63 <unknown>
 
-vlsseg3e8.v v8, (a0), a1
-# CHECK-INST: vlsseg3e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 4a <unknown>
+vlseg4e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 71 <unknown>
 
-vlsseg3e16.v v8, (a0), a1
-# CHECK-INST: vlsseg3e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 4a <unknown>
+vlseg4e128ff.v v8, (a0)
+# CHECK-INST: vlseg4e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 73 <unknown>
 
-vlsseg3e32.v v8, (a0), a1
-# CHECK-INST: vlsseg3e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 4a <unknown>
+vlseg4e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 71 <unknown>
 
-vlsseg3e64.v v8, (a0), a1
-# CHECK-INST: vlsseg3e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 4a <unknown>
+vlseg4e256ff.v v8, (a0)
+# CHECK-INST: vlseg4e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 73 <unknown>
 
-vlsseg3e128.v v8, (a0), a1
-# CHECK-INST: vlsseg3e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 5a <unknown>
+vlseg4e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 71 <unknown>
 
-vlsseg3e256.v v8, (a0), a1
-# CHECK-INST: vlsseg3e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 5a <unknown>
+vlseg4e512ff.v v8, (a0)
+# CHECK-INST: vlseg4e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 73 <unknown>
 
-vlsseg3e512.v v8, (a0), a1
-# CHECK-INST: vlsseg3e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 5a <unknown>
+vlseg4e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 71 <unknown>
 
-vlsseg3e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg3e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 5a <unknown>
-
-vlsseg3e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 48 <unknown>
-
-vlsseg3e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 48 <unknown>
-
-vlsseg3e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 48 <unknown>
-
-vlsseg3e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 48 <unknown>
-
-vlsseg3e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 58 <unknown>
-
-vlsseg3e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 58 <unknown>
-
-vlsseg3e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 58 <unknown>
+vlseg4e1024ff.v v8, (a0)
+# CHECK-INST: vlseg4e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 73 <unknown>
 
-vlsseg3e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 58 <unknown>
+vlsseg4e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 68 <unknown>
 
 vlsseg4e8.v v8, (a0), a1
 # CHECK-INST: vlsseg4e8.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x04,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 b5 6a <unknown>
 
+vlsseg4e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 68 <unknown>
+
 vlsseg4e16.v v8, (a0), a1
 # CHECK-INST: vlsseg4e16.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x54,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 b5 6a <unknown>
 
+vlsseg4e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 68 <unknown>
+
 vlsseg4e32.v v8, (a0), a1
 # CHECK-INST: vlsseg4e32.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x64,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 b5 6a <unknown>
 
+vlsseg4e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 68 <unknown>
+
 vlsseg4e64.v v8, (a0), a1
 # CHECK-INST: vlsseg4e64.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x74,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 b5 6a <unknown>
 
+vlsseg4e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 78 <unknown>
+
 vlsseg4e128.v v8, (a0), a1
 # CHECK-INST: vlsseg4e128.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x04,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 b5 7a <unknown>
 
+vlsseg4e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 78 <unknown>
+
 vlsseg4e256.v v8, (a0), a1
 # CHECK-INST: vlsseg4e256.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x54,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 b5 7a <unknown>
 
+vlsseg4e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 78 <unknown>
+
 vlsseg4e512.v v8, (a0), a1
 # CHECK-INST: vlsseg4e512.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x64,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 b5 7a <unknown>
 
+vlsseg4e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 78 <unknown>
+
 vlsseg4e1024.v v8, (a0), a1
 # CHECK-INST: vlsseg4e1024.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x74,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 b5 7a <unknown>
 
-vlsseg4e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 68 <unknown>
+vluxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 64 <unknown>
+
+vluxseg4ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg4ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 66 <unknown>
+
+vluxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 64 <unknown>
+
+vluxseg4ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg4ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 66 <unknown>
+
+vluxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 64 <unknown>
+
+vluxseg4ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg4ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 66 <unknown>
+
+vluxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 64 <unknown>
+
+vluxseg4ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg4ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 66 <unknown>
+
+vloxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 6c <unknown>
 
-vlsseg4e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 68 <unknown>
+vloxseg4ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg4ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 6e <unknown>
 
-vlsseg4e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 68 <unknown>
+vloxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 6c <unknown>
 
-vlsseg4e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 68 <unknown>
+vloxseg4ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg4ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 6e <unknown>
 
-vlsseg4e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 78 <unknown>
+vloxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 6c <unknown>
 
-vlsseg4e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 78 <unknown>
+vloxseg4ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg4ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 6e <unknown>
 
-vlsseg4e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 78 <unknown>
+vloxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 6c <unknown>
 
-vlsseg4e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 78 <unknown>
+vloxseg4ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg4ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 6e <unknown>
 
-vlsseg5e8.v v8, (a0), a1
-# CHECK-INST: vlsseg5e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 8a <unknown>
+vlseg5e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 80 <unknown>
 
-vlsseg5e16.v v8, (a0), a1
-# CHECK-INST: vlsseg5e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 8a <unknown>
+vlseg5e8.v v8, (a0)
+# CHECK-INST: vlseg5e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 82 <unknown>
 
-vlsseg5e32.v v8, (a0), a1
-# CHECK-INST: vlsseg5e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 8a <unknown>
+vlseg5e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 80 <unknown>
 
-vlsseg5e64.v v8, (a0), a1
-# CHECK-INST: vlsseg5e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 8a <unknown>
+vlseg5e16.v v8, (a0)
+# CHECK-INST: vlseg5e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 82 <unknown>
 
-vlsseg5e128.v v8, (a0), a1
-# CHECK-INST: vlsseg5e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 9a <unknown>
+vlseg5e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 80 <unknown>
 
-vlsseg5e256.v v8, (a0), a1
-# CHECK-INST: vlsseg5e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 9a <unknown>
+vlseg5e32.v v8, (a0)
+# CHECK-INST: vlseg5e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 82 <unknown>
 
-vlsseg5e512.v v8, (a0), a1
-# CHECK-INST: vlsseg5e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 9a <unknown>
+vlseg5e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 80 <unknown>
 
-vlsseg5e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg5e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 9a <unknown>
+vlseg5e64.v v8, (a0)
+# CHECK-INST: vlseg5e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 82 <unknown>
 
-vlsseg5e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 88 <unknown>
+vlseg5e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 90 <unknown>
 
-vlsseg5e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 88 <unknown>
+vlseg5e128.v v8, (a0)
+# CHECK-INST: vlseg5e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 92 <unknown>
 
-vlsseg5e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 88 <unknown>
+vlseg5e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 90 <unknown>
 
-vlsseg5e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 88 <unknown>
+vlseg5e256.v v8, (a0)
+# CHECK-INST: vlseg5e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 92 <unknown>
 
-vlsseg5e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 98 <unknown>
+vlseg5e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 90 <unknown>
 
-vlsseg5e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 98 <unknown>
+vlseg5e512.v v8, (a0)
+# CHECK-INST: vlseg5e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 92 <unknown>
 
-vlsseg5e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 98 <unknown>
+vlseg5e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 90 <unknown>
 
-vlsseg5e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 98 <unknown>
-
-vlsseg6e8.v v8, (a0), a1
-# CHECK-INST: vlsseg6e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 aa <unknown>
-
-vlsseg6e16.v v8, (a0), a1
-# CHECK-INST: vlsseg6e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 aa <unknown>
-
-vlsseg6e32.v v8, (a0), a1
-# CHECK-INST: vlsseg6e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 aa <unknown>
-
-vlsseg6e64.v v8, (a0), a1
-# CHECK-INST: vlsseg6e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 aa <unknown>
-
-vlsseg6e128.v v8, (a0), a1
-# CHECK-INST: vlsseg6e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 ba <unknown>
-
-vlsseg6e256.v v8, (a0), a1
-# CHECK-INST: vlsseg6e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 ba <unknown>
-
-vlsseg6e512.v v8, (a0), a1
-# CHECK-INST: vlsseg6e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 ba <unknown>
-
-vlsseg6e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg6e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 ba <unknown>
-
-vlsseg6e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 a8 <unknown>
-
-vlsseg6e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 a8 <unknown>
-
-vlsseg6e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 a8 <unknown>
-
-vlsseg6e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 a8 <unknown>
-
-vlsseg6e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 b8 <unknown>
-
-vlsseg6e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 b8 <unknown>
-
-vlsseg6e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 b8 <unknown>
-
-vlsseg6e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 b8 <unknown>
-
-vlsseg7e8.v v8, (a0), a1
-# CHECK-INST: vlsseg7e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 ca <unknown>
-
-vlsseg7e16.v v8, (a0), a1
-# CHECK-INST: vlsseg7e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 ca <unknown>
-
-vlsseg7e32.v v8, (a0), a1
-# CHECK-INST: vlsseg7e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 ca <unknown>
-
-vlsseg7e64.v v8, (a0), a1
-# CHECK-INST: vlsseg7e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 ca <unknown>
-
-vlsseg7e128.v v8, (a0), a1
-# CHECK-INST: vlsseg7e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 da <unknown>
-
-vlsseg7e256.v v8, (a0), a1
-# CHECK-INST: vlsseg7e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 da <unknown>
-
-vlsseg7e512.v v8, (a0), a1
-# CHECK-INST: vlsseg7e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 da <unknown>
-
-vlsseg7e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg7e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 da <unknown>
-
-vlsseg7e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 c8 <unknown>
-
-vlsseg7e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 c8 <unknown>
-
-vlsseg7e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 c8 <unknown>
-
-vlsseg7e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 c8 <unknown>
-
-vlsseg7e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 d8 <unknown>
-
-vlsseg7e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 d8 <unknown>
-
-vlsseg7e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 d8 <unknown>
-
-vlsseg7e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 d8 <unknown>
-
-vlsseg8e8.v v8, (a0), a1
-# CHECK-INST: vlsseg8e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 ea <unknown>
-
-vlsseg8e16.v v8, (a0), a1
-# CHECK-INST: vlsseg8e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 ea <unknown>
-
-vlsseg8e32.v v8, (a0), a1
-# CHECK-INST: vlsseg8e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 ea <unknown>
-
-vlsseg8e64.v v8, (a0), a1
-# CHECK-INST: vlsseg8e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 ea <unknown>
-
-vlsseg8e128.v v8, (a0), a1
-# CHECK-INST: vlsseg8e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 fa <unknown>
-
-vlsseg8e256.v v8, (a0), a1
-# CHECK-INST: vlsseg8e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 fa <unknown>
-
-vlsseg8e512.v v8, (a0), a1
-# CHECK-INST: vlsseg8e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 fa <unknown>
-
-vlsseg8e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg8e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 fa <unknown>
-
-vlsseg8e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 e8 <unknown>
-
-vlsseg8e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 e8 <unknown>
-
-vlsseg8e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 e8 <unknown>
-
-vlsseg8e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 e8 <unknown>
-
-vlsseg8e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 f8 <unknown>
-
-vlsseg8e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 f8 <unknown>
-
-vlsseg8e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 f8 <unknown>
-
-vlsseg8e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 f8 <unknown>
-
-vlxseg2ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 2e <unknown>
-
-vlxseg2ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 2e <unknown>
-
-vlxseg2ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 2e <unknown>
-
-vlxseg2ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 2e <unknown>
-
-vlxseg2ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 3e <unknown>
-
-vlxseg2ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 3e <unknown>
-
-vlxseg2ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 3e <unknown>
-
-vlxseg2ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 3e <unknown>
-
-vlxseg2ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 2c <unknown>
-
-vlxseg2ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 2c <unknown>
-
-vlxseg2ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 2c <unknown>
-
-vlxseg2ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 2c <unknown>
-
-vlxseg2ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 3c <unknown>
-
-vlxseg2ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 3c <unknown>
-
-vlxseg2ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 3c <unknown>
-
-vlxseg2ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 3c <unknown>
-
-vlxseg3ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 4e <unknown>
-
-vlxseg3ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 4e <unknown>
-
-vlxseg3ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 4e <unknown>
-
-vlxseg3ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 4e <unknown>
-
-vlxseg3ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 5e <unknown>
-
-vlxseg3ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 5e <unknown>
-
-vlxseg3ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 5e <unknown>
-
-vlxseg3ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 5e <unknown>
-
-vlxseg3ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 4c <unknown>
-
-vlxseg3ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 4c <unknown>
-
-vlxseg3ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 4c <unknown>
-
-vlxseg3ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 4c <unknown>
-
-vlxseg3ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 5c <unknown>
-
-vlxseg3ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 5c <unknown>
-
-vlxseg3ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 5c <unknown>
-
-vlxseg3ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 5c <unknown>
-
-vlxseg4ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 6e <unknown>
-
-vlxseg4ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 6e <unknown>
-
-vlxseg4ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 6e <unknown>
-
-vlxseg4ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 6e <unknown>
-
-vlxseg4ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 7e <unknown>
-
-vlxseg4ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 7e <unknown>
-
-vlxseg4ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 7e <unknown>
-
-vlxseg4ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 7e <unknown>
-
-vlxseg4ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 6c <unknown>
-
-vlxseg4ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 6c <unknown>
-
-vlxseg4ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 6c <unknown>
-
-vlxseg4ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 6c <unknown>
-
-vlxseg4ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 7c <unknown>
-
-vlxseg4ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 7c <unknown>
-
-vlxseg4ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 7c <unknown>
-
-vlxseg4ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 7c <unknown>
-
-vlxseg5ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 8e <unknown>
-
-vlxseg5ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 8e <unknown>
-
-vlxseg5ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 8e <unknown>
-
-vlxseg5ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 8e <unknown>
-
-vlxseg5ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 9e <unknown>
-
-vlxseg5ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 9e <unknown>
-
-vlxseg5ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 9e <unknown>
-
-vlxseg5ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 9e <unknown>
-
-vlxseg5ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 8c <unknown>
-
-vlxseg5ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 8c <unknown>
-
-vlxseg5ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 8c <unknown>
-
-vlxseg5ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 8c <unknown>
-
-vlxseg5ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 9c <unknown>
-
-vlxseg5ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 9c <unknown>
-
-vlxseg5ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 9c <unknown>
-
-vlxseg5ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 9c <unknown>
-
-vlxseg6ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ae <unknown>
-
-vlxseg6ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ae <unknown>
-
-vlxseg6ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ae <unknown>
-
-vlxseg6ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ae <unknown>
-
-vlxseg6ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 be <unknown>
-
-vlxseg6ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 be <unknown>
-
-vlxseg6ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 be <unknown>
-
-vlxseg6ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 be <unknown>
-
-vlxseg6ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ac <unknown>
-
-vlxseg6ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ac <unknown>
-
-vlxseg6ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ac <unknown>
-
-vlxseg6ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ac <unknown>
-
-vlxseg6ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 bc <unknown>
-
-vlxseg6ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 bc <unknown>
-
-vlxseg6ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 bc <unknown>
-
-vlxseg6ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 bc <unknown>
-
-vlxseg7ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ce <unknown>
-
-vlxseg7ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ce <unknown>
-
-vlxseg7ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ce <unknown>
-
-vlxseg7ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ce <unknown>
-
-vlxseg7ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 de <unknown>
-
-vlxseg7ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 de <unknown>
-
-vlxseg7ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 de <unknown>
-
-vlxseg7ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 de <unknown>
-
-vlxseg7ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 cc <unknown>
-
-vlxseg7ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 cc <unknown>
-
-vlxseg7ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 cc <unknown>
-
-vlxseg7ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 cc <unknown>
-
-vlxseg7ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 dc <unknown>
-
-vlxseg7ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 dc <unknown>
-
-vlxseg7ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 dc <unknown>
-
-vlxseg7ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 dc <unknown>
-
-vlxseg8ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ee <unknown>
-
-vlxseg8ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ee <unknown>
-
-vlxseg8ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ee <unknown>
-
-vlxseg8ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ee <unknown>
-
-vlxseg8ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 fe <unknown>
-
-vlxseg8ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 fe <unknown>
-
-vlxseg8ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 fe <unknown>
-
-vlxseg8ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 fe <unknown>
-
-vlxseg8ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ec <unknown>
-
-vlxseg8ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ec <unknown>
-
-vlxseg8ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ec <unknown>
-
-vlxseg8ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ec <unknown>
-
-vlxseg8ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 fc <unknown>
-
-vlxseg8ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 fc <unknown>
-
-vlxseg8ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 fc <unknown>
-
-vlxseg8ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 fc <unknown>
-
-vlseg2e8ff.v v8, (a0)
-# CHECK-INST: vlseg2e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 23 <unknown>
-
-vlseg2e16ff.v v8, (a0)
-# CHECK-INST: vlseg2e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 23 <unknown>
-
-vlseg2e32ff.v v8, (a0)
-# CHECK-INST: vlseg2e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 23 <unknown>
-
-vlseg2e64ff.v v8, (a0)
-# CHECK-INST: vlseg2e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 23 <unknown>
-
-vlseg2e128ff.v v8, (a0)
-# CHECK-INST: vlseg2e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x33]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 33 <unknown>
-
-vlseg2e256ff.v v8, (a0)
-# CHECK-INST: vlseg2e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x33]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 33 <unknown>
-
-vlseg2e512ff.v v8, (a0)
-# CHECK-INST: vlseg2e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x33]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 33 <unknown>
-
-vlseg2e1024ff.v v8, (a0)
-# CHECK-INST: vlseg2e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x33]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 33 <unknown>
-
-vlseg2e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 21 <unknown>
-
-vlseg2e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 21 <unknown>
-
-vlseg2e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 21 <unknown>
-
-vlseg2e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 21 <unknown>
-
-vlseg2e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x31]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 31 <unknown>
-
-vlseg2e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x31]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 31 <unknown>
-
-vlseg2e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x31]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 31 <unknown>
-
-vlseg2e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x31]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 31 <unknown>
-
-vlseg3e8ff.v v8, (a0)
-# CHECK-INST: vlseg3e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 43 <unknown>
-
-vlseg3e16ff.v v8, (a0)
-# CHECK-INST: vlseg3e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 43 <unknown>
-
-vlseg3e32ff.v v8, (a0)
-# CHECK-INST: vlseg3e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 43 <unknown>
-
-vlseg3e64ff.v v8, (a0)
-# CHECK-INST: vlseg3e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 43 <unknown>
-
-vlseg3e128ff.v v8, (a0)
-# CHECK-INST: vlseg3e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x53]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 53 <unknown>
-
-vlseg3e256ff.v v8, (a0)
-# CHECK-INST: vlseg3e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x53]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 53 <unknown>
-
-vlseg3e512ff.v v8, (a0)
-# CHECK-INST: vlseg3e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x53]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 53 <unknown>
-
-vlseg3e1024ff.v v8, (a0)
-# CHECK-INST: vlseg3e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x53]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 53 <unknown>
-
-vlseg3e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 41 <unknown>
-
-vlseg3e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 41 <unknown>
-
-vlseg3e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 41 <unknown>
-
-vlseg3e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 41 <unknown>
-
-vlseg3e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x51]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 51 <unknown>
-
-vlseg3e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x51]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 51 <unknown>
-
-vlseg3e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x51]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 51 <unknown>
-
-vlseg3e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x51]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 51 <unknown>
-
-vlseg4e8ff.v v8, (a0)
-# CHECK-INST: vlseg4e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 63 <unknown>
-
-vlseg4e16ff.v v8, (a0)
-# CHECK-INST: vlseg4e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 63 <unknown>
-
-vlseg4e32ff.v v8, (a0)
-# CHECK-INST: vlseg4e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 63 <unknown>
-
-vlseg4e64ff.v v8, (a0)
-# CHECK-INST: vlseg4e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 63 <unknown>
-
-vlseg4e128ff.v v8, (a0)
-# CHECK-INST: vlseg4e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x73]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 73 <unknown>
-
-vlseg4e256ff.v v8, (a0)
-# CHECK-INST: vlseg4e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x73]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 73 <unknown>
-
-vlseg4e512ff.v v8, (a0)
-# CHECK-INST: vlseg4e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x73]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 73 <unknown>
-
-vlseg4e1024ff.v v8, (a0)
-# CHECK-INST: vlseg4e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x73]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 73 <unknown>
-
-vlseg4e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 61 <unknown>
-
-vlseg4e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 61 <unknown>
-
-vlseg4e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 61 <unknown>
-
-vlseg4e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 61 <unknown>
-
-vlseg4e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x71]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 71 <unknown>
-
-vlseg4e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x71]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 71 <unknown>
-
-vlseg4e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x71]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 71 <unknown>
+vlseg5e1024.v v8, (a0)
+# CHECK-INST: vlseg5e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 92 <unknown>
 
-vlseg4e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x71]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 71 <unknown>
+vlseg5e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 81 <unknown>
 
 vlseg5e8ff.v v8, (a0)
 # CHECK-INST: vlseg5e8ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 83 <unknown>
 
+vlseg5e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 81 <unknown>
+
 vlseg5e16ff.v v8, (a0)
 # CHECK-INST: vlseg5e16ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 83 <unknown>
 
+vlseg5e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 81 <unknown>
+
 vlseg5e32ff.v v8, (a0)
 # CHECK-INST: vlseg5e32ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 83 <unknown>
 
+vlseg5e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 81 <unknown>
+
 vlseg5e64ff.v v8, (a0)
 # CHECK-INST: vlseg5e64ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 83 <unknown>
 
+vlseg5e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 91 <unknown>
+
 vlseg5e128ff.v v8, (a0)
 # CHECK-INST: vlseg5e128ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0x93]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 93 <unknown>
 
+vlseg5e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 91 <unknown>
+
 vlseg5e256ff.v v8, (a0)
 # CHECK-INST: vlseg5e256ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0x93]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 93 <unknown>
 
+vlseg5e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 91 <unknown>
+
 vlseg5e512ff.v v8, (a0)
 # CHECK-INST: vlseg5e512ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0x93]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 93 <unknown>
 
+vlseg5e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 91 <unknown>
+
 vlseg5e1024ff.v v8, (a0)
 # CHECK-INST: vlseg5e1024ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0x93]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 93 <unknown>
 
-vlseg5e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 81 <unknown>
+vlsseg5e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 88 <unknown>
 
-vlseg5e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 81 <unknown>
+vlsseg5e8.v v8, (a0), a1
+# CHECK-INST: vlsseg5e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 8a <unknown>
 
-vlseg5e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 81 <unknown>
+vlsseg5e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 88 <unknown>
 
-vlseg5e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 81 <unknown>
+vlsseg5e16.v v8, (a0), a1
+# CHECK-INST: vlsseg5e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 8a <unknown>
 
-vlseg5e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x91]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 91 <unknown>
+vlsseg5e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 88 <unknown>
+
+vlsseg5e32.v v8, (a0), a1
+# CHECK-INST: vlsseg5e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 8a <unknown>
+
+vlsseg5e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 88 <unknown>
+
+vlsseg5e64.v v8, (a0), a1
+# CHECK-INST: vlsseg5e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 8a <unknown>
+
+vlsseg5e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 98 <unknown>
+
+vlsseg5e128.v v8, (a0), a1
+# CHECK-INST: vlsseg5e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 9a <unknown>
+
+vlsseg5e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 98 <unknown>
+
+vlsseg5e256.v v8, (a0), a1
+# CHECK-INST: vlsseg5e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 9a <unknown>
+
+vlsseg5e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 98 <unknown>
+
+vlsseg5e512.v v8, (a0), a1
+# CHECK-INST: vlsseg5e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 9a <unknown>
+
+vlsseg5e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 98 <unknown>
+
+vlsseg5e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg5e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 9a <unknown>
+
+vluxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 84 <unknown>
+
+vluxseg5ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg5ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 86 <unknown>
+
+vluxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 84 <unknown>
+
+vluxseg5ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg5ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 86 <unknown>
+
+vluxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 84 <unknown>
+
+vluxseg5ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg5ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 86 <unknown>
+
+vluxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 84 <unknown>
+
+vluxseg5ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg5ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 86 <unknown>
+
+vloxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 8c <unknown>
+
+vloxseg5ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg5ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 8e <unknown>
+
+vloxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 8c <unknown>
+
+vloxseg5ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg5ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 8e <unknown>
+
+vloxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 8c <unknown>
+
+vloxseg5ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg5ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 8e <unknown>
+
+vloxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 8c <unknown>
+
+vloxseg5ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg5ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 8e <unknown>
+
+vlseg6e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 a0 <unknown>
+
+vlseg6e8.v v8, (a0)
+# CHECK-INST: vlseg6e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 a2 <unknown>
+
+vlseg6e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 a0 <unknown>
+
+vlseg6e16.v v8, (a0)
+# CHECK-INST: vlseg6e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 a2 <unknown>
+
+vlseg6e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 a0 <unknown>
+
+vlseg6e32.v v8, (a0)
+# CHECK-INST: vlseg6e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 a2 <unknown>
+
+vlseg6e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 a0 <unknown>
+
+vlseg6e64.v v8, (a0)
+# CHECK-INST: vlseg6e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 a2 <unknown>
+
+vlseg6e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 b0 <unknown>
+
+vlseg6e128.v v8, (a0)
+# CHECK-INST: vlseg6e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 b2 <unknown>
+
+vlseg6e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 b0 <unknown>
+
+vlseg6e256.v v8, (a0)
+# CHECK-INST: vlseg6e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 b2 <unknown>
+
+vlseg6e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 b0 <unknown>
 
-vlseg5e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x91]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 91 <unknown>
+vlseg6e512.v v8, (a0)
+# CHECK-INST: vlseg6e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 b2 <unknown>
 
-vlseg5e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x91]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 91 <unknown>
+vlseg6e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 b0 <unknown>
 
-vlseg5e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x91]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 91 <unknown>
+vlseg6e1024.v v8, (a0)
+# CHECK-INST: vlseg6e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 b2 <unknown>
+
+vlseg6e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 a1 <unknown>
 
 vlseg6e8ff.v v8, (a0)
 # CHECK-INST: vlseg6e8ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 a3 <unknown>
 
+vlseg6e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 a1 <unknown>
+
 vlseg6e16ff.v v8, (a0)
 # CHECK-INST: vlseg6e16ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 a3 <unknown>
 
+vlseg6e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 a1 <unknown>
+
 vlseg6e32ff.v v8, (a0)
 # CHECK-INST: vlseg6e32ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 a3 <unknown>
 
+vlseg6e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 a1 <unknown>
+
 vlseg6e64ff.v v8, (a0)
 # CHECK-INST: vlseg6e64ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 a3 <unknown>
 
+vlseg6e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 b1 <unknown>
+
 vlseg6e128ff.v v8, (a0)
 # CHECK-INST: vlseg6e128ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0xb3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 b3 <unknown>
 
+vlseg6e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 b1 <unknown>
+
 vlseg6e256ff.v v8, (a0)
 # CHECK-INST: vlseg6e256ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0xb3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 b3 <unknown>
 
+vlseg6e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 b1 <unknown>
+
 vlseg6e512ff.v v8, (a0)
 # CHECK-INST: vlseg6e512ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0xb3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 b3 <unknown>
 
+vlseg6e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 b1 <unknown>
+
 vlseg6e1024ff.v v8, (a0)
 # CHECK-INST: vlseg6e1024ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0xb3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 b3 <unknown>
 
-vlseg6e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 a1 <unknown>
+vlsseg6e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 a8 <unknown>
 
-vlseg6e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 a1 <unknown>
+vlsseg6e8.v v8, (a0), a1
+# CHECK-INST: vlsseg6e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 aa <unknown>
 
-vlseg6e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 a1 <unknown>
+vlsseg6e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 a8 <unknown>
 
-vlseg6e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 a1 <unknown>
+vlsseg6e16.v v8, (a0), a1
+# CHECK-INST: vlsseg6e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 aa <unknown>
 
-vlseg6e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xb1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 b1 <unknown>
+vlsseg6e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 a8 <unknown>
 
-vlseg6e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xb1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 b1 <unknown>
+vlsseg6e32.v v8, (a0), a1
+# CHECK-INST: vlsseg6e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 aa <unknown>
 
-vlseg6e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xb1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 b1 <unknown>
+vlsseg6e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 a8 <unknown>
 
-vlseg6e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xb1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 b1 <unknown>
+vlsseg6e64.v v8, (a0), a1
+# CHECK-INST: vlsseg6e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 aa <unknown>
 
-vlseg7e8ff.v v8, (a0)
-# CHECK-INST: vlseg7e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 c3 <unknown>
+vlsseg6e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 b8 <unknown>
 
-vlseg7e16ff.v v8, (a0)
-# CHECK-INST: vlseg7e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 c3 <unknown>
+vlsseg6e128.v v8, (a0), a1
+# CHECK-INST: vlsseg6e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 ba <unknown>
 
-vlseg7e32ff.v v8, (a0)
-# CHECK-INST: vlseg7e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 c3 <unknown>
+vlsseg6e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 b8 <unknown>
+
+vlsseg6e256.v v8, (a0), a1
+# CHECK-INST: vlsseg6e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 ba <unknown>
+
+vlsseg6e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 b8 <unknown>
+
+vlsseg6e512.v v8, (a0), a1
+# CHECK-INST: vlsseg6e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 ba <unknown>
+
+vlsseg6e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 b8 <unknown>
+
+vlsseg6e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg6e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 ba <unknown>
+
+vluxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 a4 <unknown>
+
+vluxseg6ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg6ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 a6 <unknown>
+
+vluxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 a4 <unknown>
+
+vluxseg6ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg6ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 a6 <unknown>
+
+vluxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 a4 <unknown>
+
+vluxseg6ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg6ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 a6 <unknown>
+
+vluxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 a4 <unknown>
+
+vluxseg6ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg6ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 a6 <unknown>
+
+vloxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ac <unknown>
+
+vloxseg6ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg6ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ae <unknown>
+
+vloxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ac <unknown>
+
+vloxseg6ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg6ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ae <unknown>
+
+vloxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ac <unknown>
+
+vloxseg6ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg6ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ae <unknown>
+
+vloxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ac <unknown>
+
+vloxseg6ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg6ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ae <unknown>
+
+vlseg7e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 c0 <unknown>
+
+vlseg7e8.v v8, (a0)
+# CHECK-INST: vlseg7e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 c2 <unknown>
+
+vlseg7e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 c0 <unknown>
+
+vlseg7e16.v v8, (a0)
+# CHECK-INST: vlseg7e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 c2 <unknown>
+
+vlseg7e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 c0 <unknown>
+
+vlseg7e32.v v8, (a0)
+# CHECK-INST: vlseg7e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 c2 <unknown>
+
+vlseg7e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 c0 <unknown>
+
+vlseg7e64.v v8, (a0)
+# CHECK-INST: vlseg7e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 c2 <unknown>
+
+vlseg7e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 d0 <unknown>
+
+vlseg7e128.v v8, (a0)
+# CHECK-INST: vlseg7e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 d2 <unknown>
+
+vlseg7e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 d0 <unknown>
 
-vlseg7e64ff.v v8, (a0)
-# CHECK-INST: vlseg7e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 c3 <unknown>
+vlseg7e256.v v8, (a0)
+# CHECK-INST: vlseg7e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 d2 <unknown>
 
-vlseg7e128ff.v v8, (a0)
-# CHECK-INST: vlseg7e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xd3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 d3 <unknown>
+vlseg7e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 d0 <unknown>
 
-vlseg7e256ff.v v8, (a0)
-# CHECK-INST: vlseg7e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xd3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 d3 <unknown>
+vlseg7e512.v v8, (a0)
+# CHECK-INST: vlseg7e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 d2 <unknown>
 
-vlseg7e512ff.v v8, (a0)
-# CHECK-INST: vlseg7e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xd3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 d3 <unknown>
+vlseg7e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 d0 <unknown>
 
-vlseg7e1024ff.v v8, (a0)
-# CHECK-INST: vlseg7e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xd3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 d3 <unknown>
+vlseg7e1024.v v8, (a0)
+# CHECK-INST: vlseg7e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 d2 <unknown>
 
 vlseg7e8ff.v v8, (a0), v0.t
 # CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x04,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 c1 <unknown>
 
+vlseg7e8ff.v v8, (a0)
+# CHECK-INST: vlseg7e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 c3 <unknown>
+
 vlseg7e16ff.v v8, (a0), v0.t
 # CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x54,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 c1 <unknown>
 
+vlseg7e16ff.v v8, (a0)
+# CHECK-INST: vlseg7e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 c3 <unknown>
+
 vlseg7e32ff.v v8, (a0), v0.t
 # CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x64,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 c1 <unknown>
 
+vlseg7e32ff.v v8, (a0)
+# CHECK-INST: vlseg7e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 c3 <unknown>
+
 vlseg7e64ff.v v8, (a0), v0.t
 # CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x74,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 c1 <unknown>
 
+vlseg7e64ff.v v8, (a0)
+# CHECK-INST: vlseg7e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 c3 <unknown>
+
 vlseg7e128ff.v v8, (a0), v0.t
 # CHECK-INST: vlseg7e128ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x04,0x05,0xd1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 d1 <unknown>
 
+vlseg7e128ff.v v8, (a0)
+# CHECK-INST: vlseg7e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 d3 <unknown>
+
 vlseg7e256ff.v v8, (a0), v0.t
 # CHECK-INST: vlseg7e256ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x54,0x05,0xd1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 d1 <unknown>
 
-vlseg7e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xd1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 d1 <unknown>
-
-vlseg7e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xd1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 d1 <unknown>
-
-vlseg8e8ff.v v8, (a0)
-# CHECK-INST: vlseg8e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 e3 <unknown>
-
-vlseg8e16ff.v v8, (a0)
-# CHECK-INST: vlseg8e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 e3 <unknown>
-
-vlseg8e32ff.v v8, (a0)
-# CHECK-INST: vlseg8e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 e3 <unknown>
-
-vlseg8e64ff.v v8, (a0)
-# CHECK-INST: vlseg8e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 e3 <unknown>
-
-vlseg8e128ff.v v8, (a0)
-# CHECK-INST: vlseg8e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xf3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 f3 <unknown>
-
-vlseg8e256ff.v v8, (a0)
-# CHECK-INST: vlseg8e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xf3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 f3 <unknown>
-
-vlseg8e512ff.v v8, (a0)
-# CHECK-INST: vlseg8e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xf3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 f3 <unknown>
-
-vlseg8e1024ff.v v8, (a0)
-# CHECK-INST: vlseg8e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xf3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 f3 <unknown>
-
-vlseg8e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 e1 <unknown>
-
-vlseg8e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 e1 <unknown>
-
-vlseg8e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 e1 <unknown>
-
-vlseg8e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 e1 <unknown>
-
-vlseg8e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xf1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 f1 <unknown>
-
-vlseg8e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xf1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 f1 <unknown>
-
-vlseg8e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xf1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 f1 <unknown>
-
-vlseg8e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xf1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 f1 <unknown>
-
-vsseg2e8.v v24, (a0)
-# CHECK-INST: vsseg2e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 22 <unknown>
-
-vsseg2e16.v v24, (a0)
-# CHECK-INST: vsseg2e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 22 <unknown>
-
-vsseg2e32.v v24, (a0)
-# CHECK-INST: vsseg2e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 22 <unknown>
-
-vsseg2e64.v v24, (a0)
-# CHECK-INST: vsseg2e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 22 <unknown>
-
-vsseg2e128.v v24, (a0)
-# CHECK-INST: vsseg2e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 32 <unknown>
-
-vsseg2e256.v v24, (a0)
-# CHECK-INST: vsseg2e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 32 <unknown>
-
-vsseg2e512.v v24, (a0)
-# CHECK-INST: vsseg2e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 32 <unknown>
-
-vsseg2e1024.v v24, (a0)
-# CHECK-INST: vsseg2e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 32 <unknown>
-
-vsseg2e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg2e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 20 <unknown>
-
-vsseg2e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg2e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 20 <unknown>
-
-vsseg2e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg2e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 20 <unknown>
-
-vsseg2e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg2e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 20 <unknown>
-
-vsseg2e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg2e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 30 <unknown>
-
-vsseg2e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg2e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 30 <unknown>
-
-vsseg2e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg2e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 30 <unknown>
-
-vsseg2e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg2e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 30 <unknown>
-
-vsseg3e8.v v24, (a0)
-# CHECK-INST: vsseg3e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 42 <unknown>
-
-vsseg3e16.v v24, (a0)
-# CHECK-INST: vsseg3e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 42 <unknown>
-
-vsseg3e32.v v24, (a0)
-# CHECK-INST: vsseg3e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 42 <unknown>
-
-vsseg3e64.v v24, (a0)
-# CHECK-INST: vsseg3e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 42 <unknown>
-
-vsseg3e128.v v24, (a0)
-# CHECK-INST: vsseg3e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 52 <unknown>
+vlseg7e256ff.v v8, (a0)
+# CHECK-INST: vlseg7e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 d3 <unknown>
 
-vsseg3e256.v v24, (a0)
-# CHECK-INST: vsseg3e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 52 <unknown>
+vlseg7e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 d1 <unknown>
 
-vsseg3e512.v v24, (a0)
-# CHECK-INST: vsseg3e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 52 <unknown>
+vlseg7e512ff.v v8, (a0)
+# CHECK-INST: vlseg7e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 d3 <unknown>
 
-vsseg3e1024.v v24, (a0)
-# CHECK-INST: vsseg3e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 52 <unknown>
+vlseg7e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 d1 <unknown>
 
-vsseg3e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 40 <unknown>
+vlseg7e1024ff.v v8, (a0)
+# CHECK-INST: vlseg7e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 d3 <unknown>
 
-vsseg3e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 40 <unknown>
+vlsseg7e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 c8 <unknown>
 
-vsseg3e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 40 <unknown>
+vlsseg7e8.v v8, (a0), a1
+# CHECK-INST: vlsseg7e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 ca <unknown>
 
-vsseg3e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 40 <unknown>
+vlsseg7e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 c8 <unknown>
 
-vsseg3e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 50 <unknown>
+vlsseg7e16.v v8, (a0), a1
+# CHECK-INST: vlsseg7e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 ca <unknown>
 
-vsseg3e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 50 <unknown>
+vlsseg7e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 c8 <unknown>
 
-vsseg3e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 50 <unknown>
+vlsseg7e32.v v8, (a0), a1
+# CHECK-INST: vlsseg7e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 ca <unknown>
 
-vsseg3e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 50 <unknown>
+vlsseg7e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 c8 <unknown>
 
-vsseg4e8.v v24, (a0)
-# CHECK-INST: vsseg4e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 62 <unknown>
+vlsseg7e64.v v8, (a0), a1
+# CHECK-INST: vlsseg7e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 ca <unknown>
 
-vsseg4e16.v v24, (a0)
-# CHECK-INST: vsseg4e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 62 <unknown>
+vlsseg7e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 d8 <unknown>
 
-vsseg4e32.v v24, (a0)
-# CHECK-INST: vsseg4e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 62 <unknown>
+vlsseg7e128.v v8, (a0), a1
+# CHECK-INST: vlsseg7e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 da <unknown>
 
-vsseg4e64.v v24, (a0)
-# CHECK-INST: vsseg4e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 62 <unknown>
+vlsseg7e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 d8 <unknown>
 
-vsseg4e128.v v24, (a0)
-# CHECK-INST: vsseg4e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 72 <unknown>
+vlsseg7e256.v v8, (a0), a1
+# CHECK-INST: vlsseg7e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 da <unknown>
 
-vsseg4e256.v v24, (a0)
-# CHECK-INST: vsseg4e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 72 <unknown>
+vlsseg7e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 d8 <unknown>
 
-vsseg4e512.v v24, (a0)
-# CHECK-INST: vsseg4e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 72 <unknown>
+vlsseg7e512.v v8, (a0), a1
+# CHECK-INST: vlsseg7e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 da <unknown>
 
-vsseg4e1024.v v24, (a0)
-# CHECK-INST: vsseg4e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 72 <unknown>
+vlsseg7e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 d8 <unknown>
 
-vsseg4e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 60 <unknown>
+vlsseg7e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg7e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 da <unknown>
 
-vsseg4e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 60 <unknown>
+vluxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 c4 <unknown>
+
+vluxseg7ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg7ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 c6 <unknown>
+
+vluxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 c4 <unknown>
+
+vluxseg7ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg7ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 c6 <unknown>
+
+vluxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 c4 <unknown>
+
+vluxseg7ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg7ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 c6 <unknown>
+
+vluxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 c4 <unknown>
+
+vluxseg7ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg7ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 c6 <unknown>
+
+vloxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 cc <unknown>
 
-vsseg4e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 60 <unknown>
+vloxseg7ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg7ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ce <unknown>
 
-vsseg4e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 60 <unknown>
+vloxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 cc <unknown>
 
-vsseg4e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 70 <unknown>
+vloxseg7ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg7ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ce <unknown>
 
-vsseg4e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 70 <unknown>
+vloxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 cc <unknown>
 
-vsseg4e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 70 <unknown>
+vloxseg7ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg7ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ce <unknown>
 
-vsseg4e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 70 <unknown>
+vloxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 cc <unknown>
 
-vsseg5e8.v v24, (a0)
-# CHECK-INST: vsseg5e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 82 <unknown>
+vloxseg7ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg7ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ce <unknown>
 
-vsseg5e16.v v24, (a0)
-# CHECK-INST: vsseg5e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 82 <unknown>
+vlseg8e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 e0 <unknown>
 
-vsseg5e32.v v24, (a0)
-# CHECK-INST: vsseg5e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 82 <unknown>
+vlseg8e8.v v8, (a0)
+# CHECK-INST: vlseg8e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 e2 <unknown>
 
-vsseg5e64.v v24, (a0)
-# CHECK-INST: vsseg5e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 82 <unknown>
+vlseg8e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 e0 <unknown>
 
-vsseg5e128.v v24, (a0)
-# CHECK-INST: vsseg5e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 92 <unknown>
+vlseg8e16.v v8, (a0)
+# CHECK-INST: vlseg8e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 e2 <unknown>
 
-vsseg5e256.v v24, (a0)
-# CHECK-INST: vsseg5e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 92 <unknown>
+vlseg8e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 e0 <unknown>
 
-vsseg5e512.v v24, (a0)
-# CHECK-INST: vsseg5e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 92 <unknown>
+vlseg8e32.v v8, (a0)
+# CHECK-INST: vlseg8e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 e2 <unknown>
 
-vsseg5e1024.v v24, (a0)
-# CHECK-INST: vsseg5e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 92 <unknown>
+vlseg8e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 e0 <unknown>
 
-vsseg5e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 80 <unknown>
+vlseg8e64.v v8, (a0)
+# CHECK-INST: vlseg8e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 e2 <unknown>
 
-vsseg5e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 80 <unknown>
+vlseg8e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 f0 <unknown>
 
-vsseg5e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 80 <unknown>
+vlseg8e128.v v8, (a0)
+# CHECK-INST: vlseg8e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 f2 <unknown>
 
-vsseg5e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 80 <unknown>
+vlseg8e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 f0 <unknown>
 
-vsseg5e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 90 <unknown>
+vlseg8e256.v v8, (a0)
+# CHECK-INST: vlseg8e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 f2 <unknown>
 
-vsseg5e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 90 <unknown>
+vlseg8e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 f0 <unknown>
 
-vsseg5e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 90 <unknown>
+vlseg8e512.v v8, (a0)
+# CHECK-INST: vlseg8e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 f2 <unknown>
 
-vsseg5e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 90 <unknown>
+vlseg8e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 f0 <unknown>
 
-vsseg6e8.v v24, (a0)
-# CHECK-INST: vsseg6e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 a2 <unknown>
+vlseg8e1024.v v8, (a0)
+# CHECK-INST: vlseg8e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 f2 <unknown>
 
-vsseg6e16.v v24, (a0)
-# CHECK-INST: vsseg6e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 a2 <unknown>
+vlseg8e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 e1 <unknown>
 
-vsseg6e32.v v24, (a0)
-# CHECK-INST: vsseg6e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 a2 <unknown>
+vlseg8e8ff.v v8, (a0)
+# CHECK-INST: vlseg8e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 e3 <unknown>
 
-vsseg6e64.v v24, (a0)
-# CHECK-INST: vsseg6e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 a2 <unknown>
+vlseg8e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 e1 <unknown>
 
-vsseg6e128.v v24, (a0)
-# CHECK-INST: vsseg6e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 b2 <unknown>
+vlseg8e16ff.v v8, (a0)
+# CHECK-INST: vlseg8e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 e3 <unknown>
 
-vsseg6e256.v v24, (a0)
-# CHECK-INST: vsseg6e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 b2 <unknown>
+vlseg8e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 e1 <unknown>
 
-vsseg6e512.v v24, (a0)
-# CHECK-INST: vsseg6e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 b2 <unknown>
+vlseg8e32ff.v v8, (a0)
+# CHECK-INST: vlseg8e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 e3 <unknown>
 
-vsseg6e1024.v v24, (a0)
-# CHECK-INST: vsseg6e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 b2 <unknown>
+vlseg8e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 e1 <unknown>
 
-vsseg6e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 a0 <unknown>
+vlseg8e64ff.v v8, (a0)
+# CHECK-INST: vlseg8e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 e3 <unknown>
 
-vsseg6e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 a0 <unknown>
+vlseg8e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 f1 <unknown>
 
-vsseg6e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 a0 <unknown>
+vlseg8e128ff.v v8, (a0)
+# CHECK-INST: vlseg8e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 f3 <unknown>
 
-vsseg6e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 a0 <unknown>
+vlseg8e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 f1 <unknown>
 
-vsseg6e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 b0 <unknown>
+vlseg8e256ff.v v8, (a0)
+# CHECK-INST: vlseg8e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 f3 <unknown>
 
-vsseg6e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 b0 <unknown>
+vlseg8e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 f1 <unknown>
 
-vsseg6e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 b0 <unknown>
+vlseg8e512ff.v v8, (a0)
+# CHECK-INST: vlseg8e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 f3 <unknown>
 
-vsseg6e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 b0 <unknown>
+vlseg8e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 f1 <unknown>
 
-vsseg7e8.v v24, (a0)
-# CHECK-INST: vsseg7e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 c2 <unknown>
+vlseg8e1024ff.v v8, (a0)
+# CHECK-INST: vlseg8e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 f3 <unknown>
 
-vsseg7e16.v v24, (a0)
-# CHECK-INST: vsseg7e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 c2 <unknown>
+vlsseg8e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 e8 <unknown>
 
-vsseg7e32.v v24, (a0)
-# CHECK-INST: vsseg7e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 c2 <unknown>
+vlsseg8e8.v v8, (a0), a1
+# CHECK-INST: vlsseg8e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 ea <unknown>
 
-vsseg7e64.v v24, (a0)
-# CHECK-INST: vsseg7e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 c2 <unknown>
+vlsseg8e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 e8 <unknown>
 
-vsseg7e128.v v24, (a0)
-# CHECK-INST: vsseg7e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 d2 <unknown>
+vlsseg8e16.v v8, (a0), a1
+# CHECK-INST: vlsseg8e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 ea <unknown>
 
-vsseg7e256.v v24, (a0)
-# CHECK-INST: vsseg7e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 d2 <unknown>
+vlsseg8e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 e8 <unknown>
 
-vsseg7e512.v v24, (a0)
-# CHECK-INST: vsseg7e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 d2 <unknown>
+vlsseg8e32.v v8, (a0), a1
+# CHECK-INST: vlsseg8e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 ea <unknown>
 
-vsseg7e1024.v v24, (a0)
-# CHECK-INST: vsseg7e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 d2 <unknown>
+vlsseg8e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 e8 <unknown>
 
-vsseg7e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 c0 <unknown>
+vlsseg8e64.v v8, (a0), a1
+# CHECK-INST: vlsseg8e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 ea <unknown>
 
-vsseg7e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 c0 <unknown>
+vlsseg8e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 f8 <unknown>
 
-vsseg7e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 c0 <unknown>
+vlsseg8e128.v v8, (a0), a1
+# CHECK-INST: vlsseg8e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 fa <unknown>
 
-vsseg7e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 c0 <unknown>
+vlsseg8e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 f8 <unknown>
 
-vsseg7e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 d0 <unknown>
+vlsseg8e256.v v8, (a0), a1
+# CHECK-INST: vlsseg8e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 fa <unknown>
 
-vsseg7e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 d0 <unknown>
+vlsseg8e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 f8 <unknown>
 
-vsseg7e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 d0 <unknown>
+vlsseg8e512.v v8, (a0), a1
+# CHECK-INST: vlsseg8e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 fa <unknown>
 
-vsseg7e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 d0 <unknown>
+vlsseg8e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 f8 <unknown>
 
-vsseg8e8.v v24, (a0)
-# CHECK-INST: vsseg8e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 e2 <unknown>
+vlsseg8e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg8e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 fa <unknown>
 
-vsseg8e16.v v24, (a0)
-# CHECK-INST: vsseg8e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 e2 <unknown>
+vluxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 e4 <unknown>
+
+vluxseg8ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg8ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 e6 <unknown>
+
+vluxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 e4 <unknown>
+
+vluxseg8ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg8ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 e6 <unknown>
+
+vluxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 e4 <unknown>
+
+vluxseg8ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg8ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 e6 <unknown>
+
+vluxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 e4 <unknown>
+
+vluxseg8ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg8ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 e6 <unknown>
+
+vloxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ec <unknown>
 
-vsseg8e32.v v24, (a0)
-# CHECK-INST: vsseg8e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 e2 <unknown>
+vloxseg8ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg8ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ee <unknown>
 
-vsseg8e64.v v24, (a0)
-# CHECK-INST: vsseg8e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 e2 <unknown>
+vloxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ec <unknown>
 
-vsseg8e128.v v24, (a0)
-# CHECK-INST: vsseg8e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 f2 <unknown>
+vloxseg8ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg8ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ee <unknown>
 
-vsseg8e256.v v24, (a0)
-# CHECK-INST: vsseg8e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 f2 <unknown>
+vloxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ec <unknown>
 
-vsseg8e512.v v24, (a0)
-# CHECK-INST: vsseg8e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 f2 <unknown>
+vloxseg8ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg8ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ee <unknown>
 
-vsseg8e1024.v v24, (a0)
-# CHECK-INST: vsseg8e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 f2 <unknown>
+vloxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ec <unknown>
 
-vsseg8e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 e0 <unknown>
+vloxseg8ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg8ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ee <unknown>
 
-vsseg8e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 e0 <unknown>
+vsseg2e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 20 <unknown>
 
-vsseg8e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 e0 <unknown>
+vsseg2e8.v v24, (a0)
+# CHECK-INST: vsseg2e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 22 <unknown>
 
-vsseg8e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 e0 <unknown>
+vsseg2e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 20 <unknown>
 
-vsseg8e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 f0 <unknown>
+vsseg2e16.v v24, (a0)
+# CHECK-INST: vsseg2e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 22 <unknown>
 
-vsseg8e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 f0 <unknown>
+vsseg2e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 20 <unknown>
 
-vsseg8e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 f0 <unknown>
+vsseg2e32.v v24, (a0)
+# CHECK-INST: vsseg2e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 22 <unknown>
 
-vsseg8e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 f0 <unknown>
+vsseg2e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 20 <unknown>
 
-vssseg2e8.v v24, (a0), a1
-# CHECK-INST: vssseg2e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 2a <unknown>
+vsseg2e64.v v24, (a0)
+# CHECK-INST: vsseg2e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 22 <unknown>
 
-vssseg2e16.v v24, (a0), a1
-# CHECK-INST: vssseg2e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 2a <unknown>
+vsseg2e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 30 <unknown>
 
-vssseg2e32.v v24, (a0), a1
-# CHECK-INST: vssseg2e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 2a <unknown>
+vsseg2e128.v v24, (a0)
+# CHECK-INST: vsseg2e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 32 <unknown>
 
-vssseg2e64.v v24, (a0), a1
-# CHECK-INST: vssseg2e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 2a <unknown>
+vsseg2e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 30 <unknown>
 
-vssseg2e128.v v24, (a0), a1
-# CHECK-INST: vssseg2e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 3a <unknown>
+vsseg2e256.v v24, (a0)
+# CHECK-INST: vsseg2e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 32 <unknown>
 
-vssseg2e256.v v24, (a0), a1
-# CHECK-INST: vssseg2e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 3a <unknown>
+vsseg2e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 30 <unknown>
 
-vssseg2e512.v v24, (a0), a1
-# CHECK-INST: vssseg2e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 3a <unknown>
+vsseg2e512.v v24, (a0)
+# CHECK-INST: vsseg2e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 32 <unknown>
 
-vssseg2e1024.v v24, (a0), a1
-# CHECK-INST: vssseg2e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 3a <unknown>
+vsseg2e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 30 <unknown>
+
+vsseg2e1024.v v24, (a0)
+# CHECK-INST: vsseg2e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 32 <unknown>
 
 vssseg2e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 28 <unknown>
 
+vssseg2e8.v v24, (a0), a1
+# CHECK-INST: vssseg2e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 2a <unknown>
+
 vssseg2e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 28 <unknown>
 
+vssseg2e16.v v24, (a0), a1
+# CHECK-INST: vssseg2e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 2a <unknown>
+
 vssseg2e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 28 <unknown>
 
+vssseg2e32.v v24, (a0), a1
+# CHECK-INST: vssseg2e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 2a <unknown>
+
 vssseg2e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 28 <unknown>
 
+vssseg2e64.v v24, (a0), a1
+# CHECK-INST: vssseg2e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 2a <unknown>
+
 vssseg2e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg2e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 38 <unknown>
 
+vssseg2e128.v v24, (a0), a1
+# CHECK-INST: vssseg2e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 3a <unknown>
+
 vssseg2e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg2e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 38 <unknown>
 
+vssseg2e256.v v24, (a0), a1
+# CHECK-INST: vssseg2e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 3a <unknown>
+
 vssseg2e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg2e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 38 <unknown>
 
+vssseg2e512.v v24, (a0), a1
+# CHECK-INST: vssseg2e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 3a <unknown>
+
 vssseg2e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg2e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 38 <unknown>
 
+vssseg2e1024.v v24, (a0), a1
+# CHECK-INST: vssseg2e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 3a <unknown>
+
+vsuxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 24 <unknown>
+
+vsuxseg2ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg2ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 26 <unknown>
+
+vsuxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 24 <unknown>
+
+vsuxseg2ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg2ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 26 <unknown>
+
+vsuxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 24 <unknown>
+
+vsuxseg2ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg2ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 26 <unknown>
+
+vsuxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 24 <unknown>
+
+vsuxseg2ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg2ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 26 <unknown>
+
+vsoxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 2c <unknown>
+
+vsoxseg2ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg2ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 2e <unknown>
+
+vsoxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 2c <unknown>
+
+vsoxseg2ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg2ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 2e <unknown>
+
+vsoxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 2c <unknown>
+
+vsoxseg2ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg2ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 2e <unknown>
+
+vsoxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 2c <unknown>
+
+vsoxseg2ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg2ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 2e <unknown>
+
+vsseg3e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 40 <unknown>
+
+vsseg3e8.v v24, (a0)
+# CHECK-INST: vsseg3e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 42 <unknown>
+
+vsseg3e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 40 <unknown>
+
+vsseg3e16.v v24, (a0)
+# CHECK-INST: vsseg3e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 42 <unknown>
+
+vsseg3e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 40 <unknown>
+
+vsseg3e32.v v24, (a0)
+# CHECK-INST: vsseg3e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 42 <unknown>
+
+vsseg3e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 40 <unknown>
+
+vsseg3e64.v v24, (a0)
+# CHECK-INST: vsseg3e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 42 <unknown>
+
+vsseg3e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 50 <unknown>
+
+vsseg3e128.v v24, (a0)
+# CHECK-INST: vsseg3e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 52 <unknown>
+
+vsseg3e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 50 <unknown>
+
+vsseg3e256.v v24, (a0)
+# CHECK-INST: vsseg3e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 52 <unknown>
+
+vsseg3e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 50 <unknown>
+
+vsseg3e512.v v24, (a0)
+# CHECK-INST: vsseg3e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 52 <unknown>
+
+vsseg3e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 50 <unknown>
+
+vsseg3e1024.v v24, (a0)
+# CHECK-INST: vsseg3e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 52 <unknown>
+
+vssseg3e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 48 <unknown>
+
 vssseg3e8.v v24, (a0), a1
 # CHECK-INST: vssseg3e8.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 4a <unknown>
 
+vssseg3e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 48 <unknown>
+
 vssseg3e16.v v24, (a0), a1
 # CHECK-INST: vssseg3e16.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 4a <unknown>
 
+vssseg3e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 48 <unknown>
+
 vssseg3e32.v v24, (a0), a1
 # CHECK-INST: vssseg3e32.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 4a <unknown>
 
+vssseg3e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 48 <unknown>
+
 vssseg3e64.v v24, (a0), a1
 # CHECK-INST: vssseg3e64.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 4a <unknown>
 
+vssseg3e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 58 <unknown>
+
 vssseg3e128.v v24, (a0), a1
 # CHECK-INST: vssseg3e128.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 5a <unknown>
 
+vssseg3e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 58 <unknown>
+
 vssseg3e256.v v24, (a0), a1
 # CHECK-INST: vssseg3e256.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 5a <unknown>
 
+vssseg3e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 58 <unknown>
+
 vssseg3e512.v v24, (a0), a1
 # CHECK-INST: vssseg3e512.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 5a <unknown>
 
-vssseg3e1024.v v24, (a0), a1
-# CHECK-INST: vssseg3e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 5a <unknown>
+vssseg3e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 58 <unknown>
+
+vssseg3e1024.v v24, (a0), a1
+# CHECK-INST: vssseg3e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 5a <unknown>
+
+vsuxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 44 <unknown>
+
+vsuxseg3ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg3ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 46 <unknown>
+
+vsuxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 44 <unknown>
+
+vsuxseg3ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg3ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 46 <unknown>
+
+vsuxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 44 <unknown>
+
+vsuxseg3ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg3ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 46 <unknown>
+
+vsuxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 44 <unknown>
+
+vsuxseg3ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg3ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 46 <unknown>
+
+vsoxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 4c <unknown>
+
+vsoxseg3ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg3ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 4e <unknown>
+
+vsoxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 4c <unknown>
+
+vsoxseg3ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg3ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 4e <unknown>
+
+vsoxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 4c <unknown>
+
+vsoxseg3ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg3ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 4e <unknown>
+
+vsoxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 4c <unknown>
+
+vsoxseg3ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg3ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 4e <unknown>
+
+vsseg4e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 60 <unknown>
+
+vsseg4e8.v v24, (a0)
+# CHECK-INST: vsseg4e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 62 <unknown>
+
+vsseg4e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 60 <unknown>
+
+vsseg4e16.v v24, (a0)
+# CHECK-INST: vsseg4e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 62 <unknown>
+
+vsseg4e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 60 <unknown>
+
+vsseg4e32.v v24, (a0)
+# CHECK-INST: vsseg4e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 62 <unknown>
+
+vsseg4e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 60 <unknown>
+
+vsseg4e64.v v24, (a0)
+# CHECK-INST: vsseg4e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 62 <unknown>
+
+vsseg4e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 70 <unknown>
 
-vssseg3e8.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 48 <unknown>
+vsseg4e128.v v24, (a0)
+# CHECK-INST: vsseg4e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 72 <unknown>
 
-vssseg3e16.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 48 <unknown>
+vsseg4e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 70 <unknown>
 
-vssseg3e32.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 48 <unknown>
+vsseg4e256.v v24, (a0)
+# CHECK-INST: vsseg4e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 72 <unknown>
 
-vssseg3e64.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 48 <unknown>
+vsseg4e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 70 <unknown>
 
-vssseg3e128.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg3e128.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 58 <unknown>
+vsseg4e512.v v24, (a0)
+# CHECK-INST: vsseg4e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 72 <unknown>
 
-vssseg3e256.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg3e256.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 58 <unknown>
+vsseg4e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 70 <unknown>
 
-vssseg3e512.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg3e512.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 58 <unknown>
+vsseg4e1024.v v24, (a0)
+# CHECK-INST: vsseg4e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 72 <unknown>
 
-vssseg3e1024.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg3e1024.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 58 <unknown>
+vssseg4e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 68 <unknown>
 
 vssseg4e8.v v24, (a0), a1
 # CHECK-INST: vssseg4e8.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 6a <unknown>
 
+vssseg4e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 68 <unknown>
+
 vssseg4e16.v v24, (a0), a1
 # CHECK-INST: vssseg4e16.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 6a <unknown>
 
+vssseg4e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 68 <unknown>
+
 vssseg4e32.v v24, (a0), a1
 # CHECK-INST: vssseg4e32.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 6a <unknown>
 
+vssseg4e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 68 <unknown>
+
 vssseg4e64.v v24, (a0), a1
 # CHECK-INST: vssseg4e64.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 6a <unknown>
 
+vssseg4e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 78 <unknown>
+
 vssseg4e128.v v24, (a0), a1
 # CHECK-INST: vssseg4e128.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 7a <unknown>
 
+vssseg4e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 78 <unknown>
+
 vssseg4e256.v v24, (a0), a1
 # CHECK-INST: vssseg4e256.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 7a <unknown>
 
+vssseg4e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 78 <unknown>
+
 vssseg4e512.v v24, (a0), a1
 # CHECK-INST: vssseg4e512.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 7a <unknown>
 
+vssseg4e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 78 <unknown>
+
 vssseg4e1024.v v24, (a0), a1
 # CHECK-INST: vssseg4e1024.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 7a <unknown>
 
-vssseg4e8.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 68 <unknown>
+vsuxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 64 <unknown>
+
+vsuxseg4ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg4ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 66 <unknown>
+
+vsuxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 64 <unknown>
+
+vsuxseg4ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg4ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 66 <unknown>
+
+vsuxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 64 <unknown>
+
+vsuxseg4ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg4ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 66 <unknown>
+
+vsuxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 64 <unknown>
+
+vsuxseg4ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg4ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 66 <unknown>
+
+vsoxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 6c <unknown>
 
-vssseg4e16.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 68 <unknown>
+vsoxseg4ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg4ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 6e <unknown>
 
-vssseg4e32.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 68 <unknown>
+vsoxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 6c <unknown>
 
-vssseg4e64.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 68 <unknown>
+vsoxseg4ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg4ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 6e <unknown>
 
-vssseg4e128.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg4e128.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 78 <unknown>
+vsoxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 6c <unknown>
 
-vssseg4e256.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg4e256.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 78 <unknown>
+vsoxseg4ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg4ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 6e <unknown>
 
-vssseg4e512.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg4e512.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 78 <unknown>
+vsoxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 6c <unknown>
 
-vssseg4e1024.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg4e1024.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 78 <unknown>
+vsoxseg4ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg4ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 6e <unknown>
 
-vssseg5e8.v v24, (a0), a1
-# CHECK-INST: vssseg5e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 8a <unknown>
+vsseg5e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 80 <unknown>
 
-vssseg5e16.v v24, (a0), a1
-# CHECK-INST: vssseg5e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 8a <unknown>
+vsseg5e8.v v24, (a0)
+# CHECK-INST: vsseg5e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 82 <unknown>
 
-vssseg5e32.v v24, (a0), a1
-# CHECK-INST: vssseg5e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 8a <unknown>
+vsseg5e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 80 <unknown>
 
-vssseg5e64.v v24, (a0), a1
-# CHECK-INST: vssseg5e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 8a <unknown>
+vsseg5e16.v v24, (a0)
+# CHECK-INST: vsseg5e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 82 <unknown>
 
-vssseg5e128.v v24, (a0), a1
-# CHECK-INST: vssseg5e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 9a <unknown>
+vsseg5e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 80 <unknown>
 
-vssseg5e256.v v24, (a0), a1
-# CHECK-INST: vssseg5e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 9a <unknown>
+vsseg5e32.v v24, (a0)
+# CHECK-INST: vsseg5e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 82 <unknown>
 
-vssseg5e512.v v24, (a0), a1
-# CHECK-INST: vssseg5e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 9a <unknown>
+vsseg5e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 80 <unknown>
 
-vssseg5e1024.v v24, (a0), a1
-# CHECK-INST: vssseg5e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 9a <unknown>
+vsseg5e64.v v24, (a0)
+# CHECK-INST: vsseg5e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 82 <unknown>
+
+vsseg5e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 90 <unknown>
+
+vsseg5e128.v v24, (a0)
+# CHECK-INST: vsseg5e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 92 <unknown>
+
+vsseg5e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 90 <unknown>
+
+vsseg5e256.v v24, (a0)
+# CHECK-INST: vsseg5e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 92 <unknown>
+
+vsseg5e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 90 <unknown>
+
+vsseg5e512.v v24, (a0)
+# CHECK-INST: vsseg5e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 92 <unknown>
+
+vsseg5e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 90 <unknown>
+
+vsseg5e1024.v v24, (a0)
+# CHECK-INST: vsseg5e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 92 <unknown>
 
 vssseg5e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 88 <unknown>
 
+vssseg5e8.v v24, (a0), a1
+# CHECK-INST: vssseg5e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 8a <unknown>
+
 vssseg5e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 88 <unknown>
 
+vssseg5e16.v v24, (a0), a1
+# CHECK-INST: vssseg5e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 8a <unknown>
+
 vssseg5e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 88 <unknown>
 
+vssseg5e32.v v24, (a0), a1
+# CHECK-INST: vssseg5e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 8a <unknown>
+
 vssseg5e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 88 <unknown>
 
+vssseg5e64.v v24, (a0), a1
+# CHECK-INST: vssseg5e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 8a <unknown>
+
 vssseg5e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 98 <unknown>
 
+vssseg5e128.v v24, (a0), a1
+# CHECK-INST: vssseg5e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 9a <unknown>
+
 vssseg5e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 98 <unknown>
 
+vssseg5e256.v v24, (a0), a1
+# CHECK-INST: vssseg5e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 9a <unknown>
+
 vssseg5e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 98 <unknown>
 
+vssseg5e512.v v24, (a0), a1
+# CHECK-INST: vssseg5e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 9a <unknown>
+
 vssseg5e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 98 <unknown>
 
+vssseg5e1024.v v24, (a0), a1
+# CHECK-INST: vssseg5e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 9a <unknown>
+
+vsuxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 84 <unknown>
+
+vsuxseg5ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg5ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 86 <unknown>
+
+vsuxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 84 <unknown>
+
+vsuxseg5ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg5ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 86 <unknown>
+
+vsuxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 84 <unknown>
+
+vsuxseg5ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg5ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 86 <unknown>
+
+vsuxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 84 <unknown>
+
+vsuxseg5ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg5ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 86 <unknown>
+
+vsoxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 8c <unknown>
+
+vsoxseg5ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg5ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 8e <unknown>
+
+vsoxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 8c <unknown>
+
+vsoxseg5ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg5ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 8e <unknown>
+
+vsoxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 8c <unknown>
+
+vsoxseg5ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg5ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 8e <unknown>
+
+vsoxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 8c <unknown>
+
+vsoxseg5ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg5ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 8e <unknown>
+
+vsseg6e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 a0 <unknown>
+
+vsseg6e8.v v24, (a0)
+# CHECK-INST: vsseg6e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 a2 <unknown>
+
+vsseg6e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 a0 <unknown>
+
+vsseg6e16.v v24, (a0)
+# CHECK-INST: vsseg6e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 a2 <unknown>
+
+vsseg6e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 a0 <unknown>
+
+vsseg6e32.v v24, (a0)
+# CHECK-INST: vsseg6e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 a2 <unknown>
+
+vsseg6e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 a0 <unknown>
+
+vsseg6e64.v v24, (a0)
+# CHECK-INST: vsseg6e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 a2 <unknown>
+
+vsseg6e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 b0 <unknown>
+
+vsseg6e128.v v24, (a0)
+# CHECK-INST: vsseg6e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 b2 <unknown>
+
+vsseg6e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 b0 <unknown>
+
+vsseg6e256.v v24, (a0)
+# CHECK-INST: vsseg6e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 b2 <unknown>
+
+vsseg6e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 b0 <unknown>
+
+vsseg6e512.v v24, (a0)
+# CHECK-INST: vsseg6e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 b2 <unknown>
+
+vsseg6e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 b0 <unknown>
+
+vsseg6e1024.v v24, (a0)
+# CHECK-INST: vsseg6e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 b2 <unknown>
+
+vssseg6e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 a8 <unknown>
+
 vssseg6e8.v v24, (a0), a1
 # CHECK-INST: vssseg6e8.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 aa <unknown>
 
-vssseg6e16.v v24, (a0), a1
-# CHECK-INST: vssseg6e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 aa <unknown>
+vssseg6e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 a8 <unknown>
+
+vssseg6e16.v v24, (a0), a1
+# CHECK-INST: vssseg6e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 aa <unknown>
+
+vssseg6e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 a8 <unknown>
+
+vssseg6e32.v v24, (a0), a1
+# CHECK-INST: vssseg6e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 aa <unknown>
+
+vssseg6e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 a8 <unknown>
+
+vssseg6e64.v v24, (a0), a1
+# CHECK-INST: vssseg6e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 aa <unknown>
+
+vssseg6e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 b8 <unknown>
+
+vssseg6e128.v v24, (a0), a1
+# CHECK-INST: vssseg6e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 ba <unknown>
+
+vssseg6e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 b8 <unknown>
+
+vssseg6e256.v v24, (a0), a1
+# CHECK-INST: vssseg6e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 ba <unknown>
+
+vssseg6e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 b8 <unknown>
+
+vssseg6e512.v v24, (a0), a1
+# CHECK-INST: vssseg6e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 ba <unknown>
+
+vssseg6e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 b8 <unknown>
+
+vssseg6e1024.v v24, (a0), a1
+# CHECK-INST: vssseg6e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 ba <unknown>
+
+vsuxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 a4 <unknown>
+
+vsuxseg6ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg6ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 a6 <unknown>
+
+vsuxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 a4 <unknown>
+
+vsuxseg6ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg6ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 a6 <unknown>
+
+vsuxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 a4 <unknown>
+
+vsuxseg6ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 a6 <unknown>
+
+vsuxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 a4 <unknown>
+
+vsuxseg6ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg6ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 a6 <unknown>
+
+vsoxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 ac <unknown>
+
+vsoxseg6ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg6ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 ae <unknown>
+
+vsoxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 ac <unknown>
+
+vsoxseg6ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg6ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 ae <unknown>
+
+vsoxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 ac <unknown>
+
+vsoxseg6ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg6ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 ae <unknown>
+
+vsoxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 ac <unknown>
+
+vsoxseg6ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg6ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 ae <unknown>
+
+vsseg7e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 c0 <unknown>
+
+vsseg7e8.v v24, (a0)
+# CHECK-INST: vsseg7e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 c2 <unknown>
+
+vsseg7e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 c0 <unknown>
 
-vssseg6e32.v v24, (a0), a1
-# CHECK-INST: vssseg6e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 aa <unknown>
+vsseg7e16.v v24, (a0)
+# CHECK-INST: vsseg7e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 c2 <unknown>
 
-vssseg6e64.v v24, (a0), a1
-# CHECK-INST: vssseg6e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 aa <unknown>
+vsseg7e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 c0 <unknown>
 
-vssseg6e128.v v24, (a0), a1
-# CHECK-INST: vssseg6e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 ba <unknown>
+vsseg7e32.v v24, (a0)
+# CHECK-INST: vsseg7e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 c2 <unknown>
 
-vssseg6e256.v v24, (a0), a1
-# CHECK-INST: vssseg6e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 ba <unknown>
+vsseg7e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 c0 <unknown>
 
-vssseg6e512.v v24, (a0), a1
-# CHECK-INST: vssseg6e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 ba <unknown>
+vsseg7e64.v v24, (a0)
+# CHECK-INST: vsseg7e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 c2 <unknown>
 
-vssseg6e1024.v v24, (a0), a1
-# CHECK-INST: vssseg6e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 ba <unknown>
+vsseg7e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 d0 <unknown>
 
-vssseg6e8.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 a8 <unknown>
+vsseg7e128.v v24, (a0)
+# CHECK-INST: vsseg7e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 d2 <unknown>
 
-vssseg6e16.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 a8 <unknown>
+vsseg7e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 d0 <unknown>
 
-vssseg6e32.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 a8 <unknown>
+vsseg7e256.v v24, (a0)
+# CHECK-INST: vsseg7e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 d2 <unknown>
 
-vssseg6e64.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 a8 <unknown>
+vsseg7e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 d0 <unknown>
 
-vssseg6e128.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg6e128.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 b8 <unknown>
+vsseg7e512.v v24, (a0)
+# CHECK-INST: vsseg7e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 d2 <unknown>
 
-vssseg6e256.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg6e256.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 b8 <unknown>
+vsseg7e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 d0 <unknown>
 
-vssseg6e512.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg6e512.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 b8 <unknown>
+vsseg7e1024.v v24, (a0)
+# CHECK-INST: vsseg7e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 d2 <unknown>
 
-vssseg6e1024.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg6e1024.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 b8 <unknown>
+vssseg7e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 c8 <unknown>
 
 vssseg7e8.v v24, (a0), a1
 # CHECK-INST: vssseg7e8.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 ca <unknown>
 
+vssseg7e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 c8 <unknown>
+
 vssseg7e16.v v24, (a0), a1
 # CHECK-INST: vssseg7e16.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 ca <unknown>
 
+vssseg7e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 c8 <unknown>
+
 vssseg7e32.v v24, (a0), a1
 # CHECK-INST: vssseg7e32.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 ca <unknown>
 
+vssseg7e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 c8 <unknown>
+
 vssseg7e64.v v24, (a0), a1
 # CHECK-INST: vssseg7e64.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 ca <unknown>
 
+vssseg7e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 d8 <unknown>
+
 vssseg7e128.v v24, (a0), a1
 # CHECK-INST: vssseg7e128.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 da <unknown>
 
+vssseg7e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 d8 <unknown>
+
 vssseg7e256.v v24, (a0), a1
 # CHECK-INST: vssseg7e256.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 da <unknown>
 
+vssseg7e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 d8 <unknown>
+
 vssseg7e512.v v24, (a0), a1
 # CHECK-INST: vssseg7e512.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 da <unknown>
 
+vssseg7e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 d8 <unknown>
+
 vssseg7e1024.v v24, (a0), a1
 # CHECK-INST: vssseg7e1024.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 da <unknown>
 
-vssseg7e8.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 c8 <unknown>
+vsuxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 c4 <unknown>
+
+vsuxseg7ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg7ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 c6 <unknown>
+
+vsuxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 c4 <unknown>
+
+vsuxseg7ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg7ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 c6 <unknown>
+
+vsuxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 c4 <unknown>
+
+vsuxseg7ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg7ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 c6 <unknown>
+
+vsuxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 c4 <unknown>
+
+vsuxseg7ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg7ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 c6 <unknown>
+
+vsoxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 cc <unknown>
 
-vssseg7e16.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 c8 <unknown>
+vsoxseg7ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg7ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 ce <unknown>
 
-vssseg7e32.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 c8 <unknown>
+vsoxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 cc <unknown>
 
-vssseg7e64.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 c8 <unknown>
+vsoxseg7ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 ce <unknown>
 
-vssseg7e128.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg7e128.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 d8 <unknown>
+vsoxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 cc <unknown>
 
-vssseg7e256.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg7e256.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 d8 <unknown>
+vsoxseg7ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg7ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 ce <unknown>
 
-vssseg7e512.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg7e512.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 d8 <unknown>
+vsoxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 cc <unknown>
 
-vssseg7e1024.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg7e1024.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 d8 <unknown>
+vsoxseg7ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg7ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 ce <unknown>
 
-vssseg8e8.v v24, (a0), a1
-# CHECK-INST: vssseg8e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 ea <unknown>
+vsseg8e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 e0 <unknown>
 
-vssseg8e16.v v24, (a0), a1
-# CHECK-INST: vssseg8e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 ea <unknown>
+vsseg8e8.v v24, (a0)
+# CHECK-INST: vsseg8e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 e2 <unknown>
+
+vsseg8e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 e0 <unknown>
+
+vsseg8e16.v v24, (a0)
+# CHECK-INST: vsseg8e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 e2 <unknown>
+
+vsseg8e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 e0 <unknown>
+
+vsseg8e32.v v24, (a0)
+# CHECK-INST: vsseg8e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 e2 <unknown>
+
+vsseg8e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 e0 <unknown>
+
+vsseg8e64.v v24, (a0)
+# CHECK-INST: vsseg8e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 e2 <unknown>
+
+vsseg8e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 f0 <unknown>
 
-vssseg8e32.v v24, (a0), a1
-# CHECK-INST: vssseg8e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 ea <unknown>
+vsseg8e128.v v24, (a0)
+# CHECK-INST: vsseg8e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 f2 <unknown>
 
-vssseg8e64.v v24, (a0), a1
-# CHECK-INST: vssseg8e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 ea <unknown>
+vsseg8e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 f0 <unknown>
 
-vssseg8e128.v v24, (a0), a1
-# CHECK-INST: vssseg8e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 fa <unknown>
+vsseg8e256.v v24, (a0)
+# CHECK-INST: vsseg8e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 f2 <unknown>
 
-vssseg8e256.v v24, (a0), a1
-# CHECK-INST: vssseg8e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 fa <unknown>
+vsseg8e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 f0 <unknown>
 
-vssseg8e512.v v24, (a0), a1
-# CHECK-INST: vssseg8e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 fa <unknown>
+vsseg8e512.v v24, (a0)
+# CHECK-INST: vsseg8e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 f2 <unknown>
 
-vssseg8e1024.v v24, (a0), a1
-# CHECK-INST: vssseg8e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 fa <unknown>
+vsseg8e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 f0 <unknown>
+
+vsseg8e1024.v v24, (a0)
+# CHECK-INST: vsseg8e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 f2 <unknown>
 
 vssseg8e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 e8 <unknown>
 
+vssseg8e8.v v24, (a0), a1
+# CHECK-INST: vssseg8e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 ea <unknown>
+
 vssseg8e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 e8 <unknown>
 
+vssseg8e16.v v24, (a0), a1
+# CHECK-INST: vssseg8e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 ea <unknown>
+
 vssseg8e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 e8 <unknown>
 
+vssseg8e32.v v24, (a0), a1
+# CHECK-INST: vssseg8e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 ea <unknown>
+
 vssseg8e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 e8 <unknown>
 
+vssseg8e64.v v24, (a0), a1
+# CHECK-INST: vssseg8e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 ea <unknown>
+
 vssseg8e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 f8 <unknown>
 
+vssseg8e128.v v24, (a0), a1
+# CHECK-INST: vssseg8e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 fa <unknown>
+
 vssseg8e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 f8 <unknown>
 
+vssseg8e256.v v24, (a0), a1
+# CHECK-INST: vssseg8e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 fa <unknown>
+
 vssseg8e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 f8 <unknown>
 
+vssseg8e512.v v24, (a0), a1
+# CHECK-INST: vssseg8e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 fa <unknown>
+
 vssseg8e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 f8 <unknown>
 
-vsxseg2ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 2e <unknown>
-
-vsxseg2ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 2e <unknown>
-
-vsxseg2ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 2e <unknown>
-
-vsxseg2ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 2e <unknown>
-
-vsxseg2ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 3e <unknown>
-
-vsxseg2ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 3e <unknown>
-
-vsxseg2ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 3e <unknown>
-
-vsxseg2ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 3e <unknown>
-
-vsxseg2ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 2c <unknown>
-
-vsxseg2ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 2c <unknown>
-
-vsxseg2ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 2c <unknown>
-
-vsxseg2ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 2c <unknown>
-
-vsxseg2ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 3c <unknown>
-
-vsxseg2ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 3c <unknown>
-
-vsxseg2ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 3c <unknown>
-
-vsxseg2ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 3c <unknown>
-
-vsxseg3ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 4e <unknown>
-
-vsxseg3ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 4e <unknown>
-
-vsxseg3ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 4e <unknown>
-
-vsxseg3ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 4e <unknown>
-
-vsxseg3ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 5e <unknown>
-
-vsxseg3ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 5e <unknown>
-
-vsxseg3ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 5e <unknown>
-
-vsxseg3ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 5e <unknown>
-
-vsxseg3ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 4c <unknown>
-
-vsxseg3ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 4c <unknown>
-
-vsxseg3ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 4c <unknown>
-
-vsxseg3ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 4c <unknown>
-
-vsxseg3ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 5c <unknown>
-
-vsxseg3ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 5c <unknown>
-
-vsxseg3ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 5c <unknown>
-
-vsxseg3ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 5c <unknown>
-
-vsxseg4ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 6e <unknown>
-
-vsxseg4ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 6e <unknown>
-
-vsxseg4ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 6e <unknown>
-
-vsxseg4ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 6e <unknown>
-
-vsxseg4ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 7e <unknown>
-
-vsxseg4ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 7e <unknown>
-
-vsxseg4ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 7e <unknown>
-
-vsxseg4ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 7e <unknown>
-
-vsxseg4ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 6c <unknown>
-
-vsxseg4ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 6c <unknown>
-
-vsxseg4ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 6c <unknown>
-
-vsxseg4ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 6c <unknown>
-
-vsxseg4ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 7c <unknown>
-
-vsxseg4ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 7c <unknown>
-
-vsxseg4ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 7c <unknown>
-
-vsxseg4ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 7c <unknown>
-
-vsxseg5ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 8e <unknown>
-
-vsxseg5ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 8e <unknown>
-
-vsxseg5ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 8e <unknown>
-
-vsxseg5ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 8e <unknown>
-
-vsxseg5ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 9e <unknown>
-
-vsxseg5ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 9e <unknown>
-
-vsxseg5ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 9e <unknown>
-
-vsxseg5ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 9e <unknown>
-
-vsxseg5ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 8c <unknown>
-
-vsxseg5ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 8c <unknown>
-
-vsxseg5ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 8c <unknown>
-
-vsxseg5ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 8c <unknown>
-
-vsxseg5ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 9c <unknown>
-
-vsxseg5ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 9c <unknown>
-
-vsxseg5ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 9c <unknown>
-
-vsxseg5ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 9c <unknown>
-
-vsxseg6ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 ae <unknown>
-
-vsxseg6ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 ae <unknown>
-
-vsxseg6ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 ae <unknown>
-
-vsxseg6ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 ae <unknown>
-
-vsxseg6ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 be <unknown>
-
-vsxseg6ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 be <unknown>
-
-vsxseg6ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 be <unknown>
-
-vsxseg6ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 be <unknown>
-
-vsxseg6ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 ac <unknown>
-
-vsxseg6ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 ac <unknown>
-
-vsxseg6ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 ac <unknown>
-
-vsxseg6ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 ac <unknown>
-
-vsxseg6ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 bc <unknown>
-
-vsxseg6ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 bc <unknown>
-
-vsxseg6ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 bc <unknown>
-
-vsxseg6ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 bc <unknown>
-
-vsxseg7ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 ce <unknown>
-
-vsxseg7ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 ce <unknown>
-
-vsxseg7ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 ce <unknown>
-
-vsxseg7ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 ce <unknown>
-
-vsxseg7ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 de <unknown>
-
-vsxseg7ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 de <unknown>
-
-vsxseg7ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 de <unknown>
-
-vsxseg7ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 de <unknown>
-
-vsxseg7ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 cc <unknown>
-
-vsxseg7ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 cc <unknown>
-
-vsxseg7ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 cc <unknown>
+vssseg8e1024.v v24, (a0), a1
+# CHECK-INST: vssseg8e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 fa <unknown>
 
-vsxseg7ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 cc <unknown>
+vsuxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 e4 <unknown>
+
+vsuxseg8ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg8ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 e6 <unknown>
+
+vsuxseg8ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg8ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 e4 <unknown>
+
+vsuxseg8ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg8ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 e6 <unknown>
+
+vsuxseg8ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg8ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 e4 <unknown>
+
+vsuxseg8ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg8ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 e6 <unknown>
+
+vsuxseg8ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg8ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 e4 <unknown>
+
+vsuxseg8ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg8ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 e6 <unknown>
+
+vsoxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 ec <unknown>
 
-vsxseg7ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 dc <unknown>
-
-vsxseg7ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 dc <unknown>
-
-vsxseg7ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 dc <unknown>
-
-vsxseg7ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 dc <unknown>
-
-vsxseg8ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei8.v v24, (a0), v4
+vsoxseg8ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg8ei8.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x0c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c 45 ee <unknown>
 
-vsxseg8ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 ee <unknown>
-
-vsxseg8ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 ee <unknown>
-
-vsxseg8ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 ee <unknown>
-
-vsxseg8ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 fe <unknown>
-
-vsxseg8ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 fe <unknown>
-
-vsxseg8ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 fe <unknown>
-
-vsxseg8ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 fe <unknown>
-
-vsxseg8ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 ec <unknown>
-
-vsxseg8ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei16.v v24, (a0), v4, v0.t
+vsoxseg8ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg8ei16.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c 45 ec <unknown>
 
-vsxseg8ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei32.v v24, (a0), v4, v0.t
+vsoxseg8ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg8ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 ee <unknown>
+
+vsoxseg8ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg8ei32.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c 45 ec <unknown>
 
-vsxseg8ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei64.v v24, (a0), v4, v0.t
+vsoxseg8ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg8ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 ee <unknown>
+
+vsoxseg8ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c 45 ec <unknown>
 
-vsxseg8ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 fc <unknown>
-
-vsxseg8ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 fc <unknown>
-
-vsxseg8ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 fc <unknown>
-
-vsxseg8ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 fc <unknown>
\ No newline at end of file
+vsoxseg8ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 ee <unknown>