diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -49,6 +49,37 @@ def InstFormatCJ : InstFormat<16>; def InstFormatOther : InstFormat<17>; +// Illegal instructions: +// +// * The destination vector register group for a masked vector instruction +// cannot overlap the source mask register (v0), unless the destination vector +// register is being written with a mask value (e.g., comparisons) or the +// scalar result of a reduction. +// +// * Widening: The destination EEW is greater than the source EEW, the source +// EMUL is at least 1. The destination vector register group cannot overlap +// with the source vector register groups besides the highest-numbered part of +// the destination register group. +// +// * Narrowing: The destination EEW is smaller than the source EEW. The +// destination vector register group cannot overlap with the source vector +// register groups besides the lowest-numbered part of the source register +// group. +// +// * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the +// source register and, if masked, cannot overlap the mask register ('v0'). +// +// * viota: The destination register cannot overlap the source register and, +// if masked, cannot overlap the mask register ('v0'). +// +// * v[f]slide[1]up: The destination vector register group for vslideup cannot +// overlap the source vector register group. +// +// * vrgather: The destination vector register group cannot overlap with the +// source vector register groups. +// +// * vcompress: The destination vector register group cannot overlap the +// source vector register group or the source mask register class RISCVVConstraint val> { bits<4> Value = val; } @@ -66,13 +97,9 @@ def WidenCvt : RISCVVConstraint; -def Narrow : RISCVVConstraint; -def NarrowCvt : RISCVVConstraint; +def NarrowCvt : RISCVVConstraint; -def Vmadc : RISCVVConstraint; def Iota : RISCVVConstraint; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -551,15 +551,15 @@ // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>; -let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in { +let RVVConstraint = NoConstraint in { defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>; defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>; -} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc +} // RVVConstraint = NoConstraint defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>; -let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in { +let RVVConstraint = NoConstraint in { defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>; defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>; -} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc +} // RVVConstraint = NoConstraint // Vector Bitwise Logical Instructions defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>; @@ -942,17 +942,14 @@ "vfirst.m", "$vd, $vs2$vm">; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 +let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { // vmsbf.m set-before-first mask bit defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>; - // vmsif.m set-including-first mask bit defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>; - // vmsof.m set-only-first mask bit defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>; - // Vector Iota Instruction -let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota @@ -991,12 +988,9 @@ // Vector Slide Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>; -} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp -defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>; - -let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>; } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp +defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>; defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>; } // Predicates = [HasStdExtV] diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -58,49 +58,6 @@ VS1Constraint = 0b0010, VMConstraint = 0b0100, OneInput = 0b1000, - - // Illegal instructions: - // - // * The destination vector register group for a masked vector instruction - // cannot overlap the source mask register (v0), unless the destination vector - // register is being written with a mask value (e.g., comparisons) or the - // scalar result of a reduction. - // - // * Widening: The destination vector register group cannot overlap a source - // vector register group of a different EEW - // - // * Narrowing: The destination vector register group cannot overlap the - // first source vector register group - // - // * For vadc and vsbc, an illegal instruction exception is raised if the - // destination vector register is v0. - // - // * For vmadc and vmsbc, an illegal instruction exception is raised if the - // destination vector register overlaps a source vector register group. - // - // * viota: An illegal instruction exception is raised if the destination - // vector register group overlaps the source vector mask register. If the - // instruction is masked, an illegal instruction exception is issued if the - // destination vector register group overlaps v0. - // - // * v[f]slide[1]up: The destination vector register group for vslideup cannot - // overlap the source vector register group. - // - // * vrgather: The destination vector register group cannot overlap with the - // source vector register groups. - // - // * vcompress: The destination vector register group cannot overlap the - // source vector register group or the source mask register - WidenV = VS2Constraint | VS1Constraint | VMConstraint, - WidenW = VS1Constraint | VMConstraint, - WidenCvt = VS2Constraint | VMConstraint | OneInput, - Narrow = VS2Constraint | VMConstraint, - NarrowCvt = VS2Constraint | VMConstraint | OneInput, - Vmadc = VS2Constraint | VS1Constraint, - Iota = VS2Constraint | VMConstraint | OneInput, - SlideUp = VS2Constraint | VMConstraint, - Vrgather = VS2Constraint | VS1Constraint | VMConstraint, - Vcompress = VS2Constraint | VS1Constraint, }; // RISC-V Specific Machine Operand Flags diff --git a/llvm/test/MC/RISCV/rvv/add.s b/llvm/test/MC/RISCV/rvv/add.s --- a/llvm/test/MC/RISCV/rvv/add.s +++ b/llvm/test/MC/RISCV/rvv/add.s @@ -146,6 +146,18 @@ # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 57 04 4a 40 +vadc.vvm v4, v4, v20, v0 +# CHECK-INST: vadc.vvm v4, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x02,0x4a,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 02 4a 40 + +vadc.vvm v8, v4, v8, v0 +# CHECK-INST: vadc.vvm v8, v4, v8, v0 +# CHECK-ENCODING: [0x57,0x04,0x44,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 44 40 + vadc.vxm v8, v4, a0, v0 # CHECK-INST: vadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x40] @@ -164,6 +176,18 @@ # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 57 04 4a 44 +vmadc.vvm v4, v4, v20, v0 +# CHECK-INST: vmadc.vvm v4, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x02,0x4a,0x44] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 02 4a 44 + +vmadc.vvm v8, v4, v8, v0 +# CHECK-INST: vmadc.vvm v8, v4, v8, v0 +# CHECK-ENCODING: [0x57,0x04,0x44,0x44] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 44 44 + vmadc.vxm v8, v4, a0, v0 # CHECK-INST: vmadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x44] diff --git a/llvm/test/MC/RISCV/rvv/convert.s b/llvm/test/MC/RISCV/rvv/convert.s --- a/llvm/test/MC/RISCV/rvv/convert.s +++ b/llvm/test/MC/RISCV/rvv/convert.s @@ -173,6 +173,12 @@ # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' # CHECK-UNKNOWN: 57 14 48 48 +vfncvt.xu.f.w v4, v4, v0.t +# CHECK-INST: vfncvt.xu.f.w v4, v4, v0.t +# CHECK-ENCODING: [0x57,0x12,0x48,0x48] +# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V' +# CHECK-UNKNOWN: 57 12 48 48 + vfncvt.xu.f.w v8, v4 # CHECK-INST: vfncvt.xu.f.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x48,0x4a] diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s --- a/llvm/test/MC/RISCV/rvv/invalid.s +++ b/llvm/test/MC/RISCV/rvv/invalid.s @@ -133,78 +133,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vslide1up.vx v2, v2, a0 -vnsrl.wv v2, v2, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnsrl.wv v2, v2, v4 - -vnsrl.wx v2, v2, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnsrl.wx v2, v2, a0 - -vnsrl.wi v2, v2, 31 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnsrl.wi v2, v2, 31 - -vnsra.wv v2, v2, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnsra.wv v2, v2, v4 - -vnsra.wx v2, v2, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnsra.wx v2, v2, a0 - -vnsra.wi v2, v2, 31 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnsra.wi v2, v2, 31 - -vnclipu.wv v2, v2, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnclipu.wv v2, v2, v4 - -vnclipu.wx v2, v2, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnclipu.wx v2, v2, a0 - -vnclipu.wi v2, v2, 31 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnclipu.wi v2, v2, 31 - -vnclip.wv v2, v2, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnclip.wv v2, v2, v4 - -vnclip.wx v2, v2, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnclip.wx v2, v2, a0 - -vnclip.wi v2, v2, 31 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnclip.wi v2, v2, 31 - -vfncvt.xu.f.w v2, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.xu.f.w v2, v2 - -vfncvt.x.f.w v2, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.x.f.w v2, v2 - -vfncvt.f.xu.w v2, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.f.xu.w v2, v2 - -vfncvt.f.x.w v2, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.f.x.w v2, v2 - -vfncvt.f.f.w v2, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.f.f.w v2, v2 - -vfncvt.rod.f.f.w v2, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v2, v2 - vrgather.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vrgather.vv v0, v2, v4, v0.t @@ -589,14 +517,6 @@ # CHECK-ERROR: The destination vector register group cannot be V0. # CHECK-ERROR-LABEL: vadc.vvm v0, v2, v4, v0 -vmadc.vvm v2, v2, v4, v0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vmadc.vvm v2, v2, v4, v0 - -vmadc.vvm v4, v2, v4, v0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vmadc.vvm v4, v2, v4, v0 - vadd.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vadd.vv v0, v2, v4, v0.t diff --git a/llvm/test/MC/RISCV/rvv/shift.s b/llvm/test/MC/RISCV/rvv/shift.s --- a/llvm/test/MC/RISCV/rvv/shift.s +++ b/llvm/test/MC/RISCV/rvv/shift.s @@ -122,6 +122,12 @@ # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 57 04 4a b0 +vnsrl.wv v4, v4, v20, v0.t +# CHECK-INST: vnsrl.wv v4, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x02,0x4a,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 02 4a b0 + vnsrl.wv v8, v4, v20 # CHECK-INST: vnsrl.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb2] diff --git a/llvm/test/MC/RISCV/rvv/sub.s b/llvm/test/MC/RISCV/rvv/sub.s --- a/llvm/test/MC/RISCV/rvv/sub.s +++ b/llvm/test/MC/RISCV/rvv/sub.s @@ -158,6 +158,18 @@ # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 57 04 4a 48 +vsbc.vvm v4, v4, v20, v0 +# CHECK-INST: vsbc.vvm v4, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x02,0x4a,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 02 4a 48 + +vsbc.vvm v8, v4, v8, v0 +# CHECK-INST: vsbc.vvm v8, v4, v8, v0 +# CHECK-ENCODING: [0x57,0x04,0x44,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 44 48 + vsbc.vxm v8, v4, a0, v0 # CHECK-INST: vsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x48] @@ -170,6 +182,18 @@ # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 57 04 4a 4c +vmsbc.vvm v4, v4, v20, v0 +# CHECK-INST: vmsbc.vvm v4, v4, v20, v0 +# CHECK-ENCODING: [0x57,0x02,0x4a,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 02 4a 4c + +vmsbc.vvm v8, v4, v8, v0 +# CHECK-INST: vmsbc.vvm v8, v4, v8, v0 +# CHECK-ENCODING: [0x57,0x04,0x44,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 04 44 4c + vmsbc.vxm v8, v4, a0, v0 # CHECK-INST: vmsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4c]