diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -71,8 +71,6 @@ def NarrowCvt : RISCVVConstraint; -def Vmadc : RISCVVConstraint; def Iota : RISCVVConstraint; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -551,15 +551,15 @@ // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>; -let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in { +let RVVConstraint = NoConstraint in { defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>; defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>; -} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc +} // RVVConstraint = NoConstraint defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>; -let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in { +let RVVConstraint = NoConstraint in { defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>; defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>; -} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc +} // RVVConstraint = NoConstraint // Vector Bitwise Logical Instructions defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>; @@ -942,17 +942,14 @@ "vfirst.m", "$vd, $vs2$vm">; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 +let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { // vmsbf.m set-before-first mask bit defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>; - // vmsif.m set-including-first mask bit defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>; - // vmsof.m set-only-first mask bit defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>; - // Vector Iota Instruction -let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota @@ -991,12 +988,9 @@ // Vector Slide Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>; -} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp -defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>; - -let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>; } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp +defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>; defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>; } // Predicates = [HasStdExtV] diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -66,22 +66,21 @@ // register is being written with a mask value (e.g., comparisons) or the // scalar result of a reduction. // - // * Widening: The destination vector register group cannot overlap a source - // vector register group of a different EEW + // * Widening: The destination EEW is greater than the source EEW, the source + // EMUL is at least 1. The destination vector register group cannot overlap + // with the source vector register groups besides the highest-numbered part of + // the destination register group. // - // * Narrowing: The destination vector register group cannot overlap the - // first source vector register group + // * Narrowing: The destination EEW is smaller than the source EEW. The + // destination vector register group cannot overlap with the source vector + // register groups besides the lowest-numbered part of the source register + // group. // - // * For vadc and vsbc, an illegal instruction exception is raised if the - // destination vector register is v0. + // * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the + // source register and, if masked, cannot overlap the mask register ('v0'). // - // * For vmadc and vmsbc, an illegal instruction exception is raised if the - // destination vector register overlaps a source vector register group. - // - // * viota: An illegal instruction exception is raised if the destination - // vector register group overlaps the source vector mask register. If the - // instruction is masked, an illegal instruction exception is issued if the - // destination vector register group overlaps v0. + // * viota: The destination register cannot overlap the source register and, + // if masked, cannot overlap the mask register ('v0'). // // * v[f]slide[1]up: The destination vector register group for vslideup cannot // overlap the source vector register group. @@ -94,12 +93,11 @@ WidenV = VS2Constraint | VS1Constraint | VMConstraint, WidenW = VS1Constraint | VMConstraint, WidenCvt = VS2Constraint | VMConstraint | OneInput, - Narrow = VS2Constraint | VMConstraint, - NarrowCvt = VS2Constraint | VMConstraint | OneInput, - Vmadc = VS2Constraint | VS1Constraint, + Narrow = VMConstraint, + NarrowCvt = VMConstraint | OneInput, Iota = VS2Constraint | VMConstraint | OneInput, - SlideUp = VS2Constraint | VMConstraint, - Vrgather = VS2Constraint | VS1Constraint | VMConstraint, + SlideUp = VS2Constraint, + Vrgather = VS2Constraint | VS1Constraint, Vcompress = VS2Constraint | VS1Constraint, }; diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s --- a/llvm/test/MC/RISCV/rvv/invalid.s +++ b/llvm/test/MC/RISCV/rvv/invalid.s @@ -589,14 +589,6 @@ # CHECK-ERROR: The destination vector register group cannot be V0. # CHECK-ERROR-LABEL: vadc.vvm v0, v2, v4, v0 -vmadc.vvm v2, v2, v4, v0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vmadc.vvm v2, v2, v4, v0 - -vmadc.vvm v4, v2, v4, v0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vmadc.vvm v4, v2, v4, v0 - vadd.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vadd.vv v0, v2, v4, v0.t