Index: lib/Target/Mips/MipsMSAInstrInfo.td =================================================================== --- lib/Target/Mips/MipsMSAInstrInfo.td +++ lib/Target/Mips/MipsMSAInstrInfo.td @@ -63,6 +63,9 @@ def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; +def immZExt4Ptr : ImmLeaf(Imm);}]>; +def immZExt6Ptr : ImmLeaf(Imm);}]>; + // Operands // The immediate of an LSA instruction needs special handling @@ -84,6 +87,14 @@ let PrintMethod = "printUnsignedImm8"; } +def uimm4_ptr : Operand { + let PrintMethod = "printUnsignedImm8"; +} + +def uimm6_ptr : Operand { + let PrintMethod = "printUnsignedImm8"; +} + def uimm8 : Operand { let PrintMethod = "printUnsignedImm8"; } @@ -1273,9 +1284,9 @@ RegisterOperand ROWS, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROD:$rd); - dag InOperandList = (ins ROWS:$ws, uimm4:$n); + dag InOperandList = (ins ROWS:$ws, uimm4_ptr:$n); string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); - list Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))]; + list Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4Ptr:$n))]; InstrItinClass Itinerary = itin; } @@ -1293,8 +1304,8 @@ class MSA_COPY_PSEUDO_BASE : - MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n), - [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> { + MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4_ptr:$n), + [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4Ptr:$n))]> { bit usesCustomInserter = 1; } @@ -1479,29 +1490,30 @@ RegisterOperand ROWD, RegisterOperand ROS, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); - dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n); + dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6_ptr:$n); string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); list Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, - immZExt6:$n))]; + immZExt6Ptr:$n))]; InstrItinClass Itinerary = itin; string Constraints = "$wd = $wd_in"; } class MSA_INSERT_PSEUDO_BASE : - MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs), + MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6_ptr:$n, ROFS:$fs), [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, - immZExt6:$n))]> { + immZExt6Ptr:$n))]> { bit usesCustomInserter = 1; string Constraints = "$wd = $wd_in"; } class MSA_INSERT_VIDX_PSEUDO_BASE : - MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, GPR32Opnd:$n, ROFS:$fs), + RegisterOperand ROWD, RegisterOperand ROFS, + RegisterOperand ROIdx> : + MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, - GPR32Opnd:$n))]> { + ROIdx:$n))]> { bit usesCustomInserter = 1; string Constraints = "$wd = $wd_in"; } @@ -2302,13 +2314,13 @@ MSA128DOpnd, GPR64Opnd>; class INSERT_B_VIDX_PSEUDO_DESC : - MSA_INSERT_VIDX_PSEUDO_BASE; + MSA_INSERT_VIDX_PSEUDO_BASE; class INSERT_H_VIDX_PSEUDO_DESC : - MSA_INSERT_VIDX_PSEUDO_BASE; + MSA_INSERT_VIDX_PSEUDO_BASE; class INSERT_W_VIDX_PSEUDO_DESC : - MSA_INSERT_VIDX_PSEUDO_BASE; + MSA_INSERT_VIDX_PSEUDO_BASE; class INSERT_D_VIDX_PSEUDO_DESC : - MSA_INSERT_VIDX_PSEUDO_BASE; + MSA_INSERT_VIDX_PSEUDO_BASE; class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE; @@ -2316,9 +2328,23 @@ MSA128DOpnd, FGR64Opnd>; class INSERT_FW_VIDX_PSEUDO_DESC : - MSA_INSERT_VIDX_PSEUDO_BASE; + MSA_INSERT_VIDX_PSEUDO_BASE; class INSERT_FD_VIDX_PSEUDO_DESC : - MSA_INSERT_VIDX_PSEUDO_BASE; + MSA_INSERT_VIDX_PSEUDO_BASE; + +class INSERT_B_VIDX64_PSEUDO_DESC : + MSA_INSERT_VIDX_PSEUDO_BASE; +class INSERT_H_VIDX64_PSEUDO_DESC : + MSA_INSERT_VIDX_PSEUDO_BASE; +class INSERT_W_VIDX64_PSEUDO_DESC : + MSA_INSERT_VIDX_PSEUDO_BASE; +class INSERT_D_VIDX64_PSEUDO_DESC : + MSA_INSERT_VIDX_PSEUDO_BASE; + +class INSERT_FW_VIDX64_PSEUDO_DESC : + MSA_INSERT_VIDX_PSEUDO_BASE; +class INSERT_FD_VIDX64_PSEUDO_DESC : + MSA_INSERT_VIDX_PSEUDO_BASE; class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, MSA128BOpnd>; @@ -3236,6 +3262,13 @@ def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; +def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; +def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; +def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; +def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; +def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; +def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; + def LD_B: LD_B_ENC, LD_B_DESC; def LD_H: LD_H_ENC, LD_H_DESC; def LD_W: LD_W_ENC, LD_W_DESC; @@ -3805,3 +3838,93 @@ (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, i32:$idx), sub_64))>; + +// Vector extraction with variable index (N64 ABI) +def : MSAPat< + (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), + (SRA (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG + (SPLAT_B v16i8:$ws, + (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_lo)), + GPR32), + (i32 24))>; +def : MSAPat< + (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), + (SRA (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG + (SPLAT_H v8i16:$ws, + (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_lo)), + GPR32), + (i32 16))>; +def : MSAPat< + (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), + (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG + (SPLAT_W v4i32:$ws, + (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_lo)), + GPR32)>; +def : MSAPat< + (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), + (COPY_TO_REGCLASS + (i64 (EXTRACT_SUBREG + (SPLAT_D v2i64:$ws, + (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_64)), + GPR64), [HasMSA, IsGP64bit]>; + +def : MSAPat< + (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), + (SRL (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG + (SPLAT_B v16i8:$ws, + (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_lo)), + GPR32), + (i32 24))>; +def : MSAPat< + (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), + (SRL (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG + (SPLAT_H v8i16:$ws, + (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_lo)), + GPR32), + (i32 16))>; +def : MSAPat< + (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), + (COPY_TO_REGCLASS + (i32 (EXTRACT_SUBREG + (SPLAT_W v4i32:$ws, + (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_lo)), + GPR32)>; +def : MSAPat< + (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), + (COPY_TO_REGCLASS + (i64 (EXTRACT_SUBREG + (SPLAT_D v2i64:$ws, + (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_64)), + GPR64), + [HasMSA, IsGP64bit]>; + +def : MSAPat< + (f32 (vector_extract v4f32:$ws, i64:$idx)), + (f32 (EXTRACT_SUBREG + (SPLAT_W v4f32:$ws, + (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_lo))>; +def : MSAPat< + (f64 (vector_extract v2f64:$ws, i64:$idx)), + (f64 (EXTRACT_SUBREG + (SPLAT_D v2f64:$ws, + (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), + sub_64))>; Index: lib/Target/Mips/MipsSEISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsSEISelLowering.cpp +++ lib/Target/Mips/MipsSEISelLowering.cpp @@ -1145,16 +1145,22 @@ case Mips::INSERT_FD_PSEUDO: return emitINSERT_FD(MI, BB); case Mips::INSERT_B_VIDX_PSEUDO: + case Mips::INSERT_B_VIDX64_PSEUDO: return emitINSERT_DF_VIDX(MI, BB, 1, false); case Mips::INSERT_H_VIDX_PSEUDO: + case Mips::INSERT_H_VIDX64_PSEUDO: return emitINSERT_DF_VIDX(MI, BB, 2, false); case Mips::INSERT_W_VIDX_PSEUDO: + case Mips::INSERT_W_VIDX64_PSEUDO: return emitINSERT_DF_VIDX(MI, BB, 4, false); case Mips::INSERT_D_VIDX_PSEUDO: + case Mips::INSERT_D_VIDX64_PSEUDO: return emitINSERT_DF_VIDX(MI, BB, 8, false); case Mips::INSERT_FW_VIDX_PSEUDO: + case Mips::INSERT_FW_VIDX64_PSEUDO: return emitINSERT_DF_VIDX(MI, BB, 4, true); case Mips::INSERT_FD_VIDX_PSEUDO: + case Mips::INSERT_FD_VIDX64_PSEUDO: return emitINSERT_DF_VIDX(MI, BB, 8, true); case Mips::FILL_FW_PSEUDO: return emitFILL_FW(MI, BB); Index: test/CodeGen/Mips/msa/basic_operations.ll =================================================================== --- test/CodeGen/Mips/msa/basic_operations.ll +++ test/CodeGen/Mips/msa/basic_operations.ll @@ -2,8 +2,8 @@ ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-LE %s ; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-BE %s ; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-LE %s -; R!N: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-BE %s -; R!N: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-LE %s +; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-BE %s +; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-LE %s @v4i8 = global <4 x i8> @v16i8 = global <16 x i8> @@ -798,7 +798,9 @@ ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] ; ALL-DAG: insert.w [[R1]][0], $4 - ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] + ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]] ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] store <4 x i32> %3, <4 x i32>* @v4i32 Index: test/CodeGen/Mips/msa/basic_operations_float.ll =================================================================== --- test/CodeGen/Mips/msa/basic_operations_float.ll +++ test/CodeGen/Mips/msa/basic_operations_float.ll @@ -1,5 +1,9 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s +; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s +; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s +; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s +; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s @v4f32 = global <4 x float> @v2f64 = global <2 x double> @@ -18,7 +22,9 @@ ; ALL: fill.w [[R2:\$w[0-9]+]], [[R1]] store volatile <4 x float> , <4 x float>*@v4f32 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x float> , <4 x float>*@v4f32 @@ -27,11 +33,15 @@ ; ALL: fill.w [[R3:\$w[0-9]+]], [[R2]] store volatile <4 x float> , <4 x float>*@v4f32 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x float> , <4 x float>*@v4f32 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void @@ -44,27 +54,39 @@ ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 store volatile <2 x double> , <2 x double>*@v2f64 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> , <2 x double>*@v2f64 - ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void @@ -153,14 +175,18 @@ ; ALL-LABEL: extract_v4f32_vidx: %1 = load <4 x float>, <4 x float>* @v4f32 - ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( + ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( + ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)( + ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)( ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = fadd <4 x float> %1, %1 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( + ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <4 x float> %2, i32 %3 @@ -215,14 +241,18 @@ ; ALL-LABEL: extract_v2f64_vidx: %1 = load <2 x double>, <2 x double>* @v2f64 - ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( + ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( + ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)( + ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)( ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = fadd <2 x double> %1, %1 ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] %3 = load i32, i32* @i32 - ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( + ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %4 = extractelement <2 x double> %2, i32 %3 @@ -267,11 +297,15 @@ ; ALL-LABEL: insert_v4f32_vidx: %1 = load <4 x float>, <4 x float>* @v4f32 - ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( + ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( + ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)( + ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)( ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = load i32, i32* @i32 - ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( + ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %3 = insertelement <4 x float> %1, float %a, i32 %2 @@ -292,11 +326,15 @@ ; ALL-LABEL: insert_v2f64_vidx: %1 = load <2 x double>, <2 x double>* @v2f64 - ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( + ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( + ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)( + ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)( ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) %2 = load i32, i32* @i32 - ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( + ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)( + ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)( ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) %3 = insertelement <2 x double> %1, double %a, i32 %2