diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -36,7 +36,6 @@
 def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
 
 multiclass VPatUSLoadStoreSDNode<LLVMType type,
-                                 LLVMType mask_type,
                                  int sew,
                                  LMULInfo vlmul,
                                  RegisterClass reg_rs1,
@@ -54,8 +53,10 @@
 
 multiclass VPatUSLoadStoreSDNodes<RegisterClass reg_rs1> {
   foreach vti = AllVectors in
-    defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.Mask, vti.SEW, vti.LMul,
+    defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.SEW, vti.LMul,
                                     reg_rs1, vti.RegClass>;
+  foreach vti = AllMasks in
+    defm "" : VPatUSLoadStoreSDNode<vti.Mask, 8, V_M1, reg_rs1, VR>;
 }
 
 class VPatBinarySDNode_VV<SDNode vop,
diff --git a/llvm/test/CodeGen/RISCV/rvv/load-mask.ll b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
@@ -0,0 +1,89 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
+; RUN:     -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
+; RUN:     -verify-machineinstrs | FileCheck %s
+
+define void @test_load_mask_64(<vscale x 64 x i1>* %pa, <vscale x 64 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vse8.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 64 x i1>, <vscale x 64 x i1>* %pa
+  store <vscale x 64 x i1> %a, <vscale x 64 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_32(<vscale x 32 x i1>* %pa, <vscale x 32 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vse8.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 32 x i1>, <vscale x 32 x i1>* %pa
+  store <vscale x 32 x i1> %a, <vscale x 32 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_16(<vscale x 16 x i1>* %pa, <vscale x 16 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vse8.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 16 x i1>, <vscale x 16 x i1>* %pa
+  store <vscale x 16 x i1> %a, <vscale x 16 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_8(<vscale x 8 x i1>* %pa, <vscale x 8 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vse8.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 8 x i1>, <vscale x 8 x i1>* %pa
+  store <vscale x 8 x i1> %a, <vscale x 8 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_4(<vscale x 4 x i1>* %pa, <vscale x 4 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vse8.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 4 x i1>, <vscale x 4 x i1>* %pa
+  store <vscale x 4 x i1> %a, <vscale x 4 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_2(<vscale x 2 x i1>* %pa, <vscale x 2 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vse8.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 2 x i1>, <vscale x 2 x i1>* %pa
+  store <vscale x 2 x i1> %a, <vscale x 2 x i1>* %pb
+  ret void
+}
+
+define void @test_load_mask_1(<vscale x 1 x i1>* %pa, <vscale x 1 x i1>* %pb) {
+; CHECK-LABEL: test_load_mask_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vse8.v v25, (a1)
+; CHECK-NEXT:    ret
+  %a = load <vscale x 1 x i1>, <vscale x 1 x i1>* %pa
+  store <vscale x 1 x i1> %a, <vscale x 1 x i1>* %pb
+  ret void
+}