diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -33,11 +33,12 @@
   bool HasB;
   bool HasV;
   bool HasZfh;
+  bool HasZfinx;
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false),
-        HasC(false), HasB(false), HasV(false), HasZfh(false) {
+        HasC(false), HasB(false), HasV(false), HasZfh(false), HasZfinx(false) {
     LongDoubleWidth = 128;
     LongDoubleAlign = 128;
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -141,6 +141,9 @@
 
   if (HasZfh)
     Builder.defineMacro("__riscv_zfh");
+
+  if (HasZfinx)
+    Builder.defineMacro("__riscv_zfinx");
 }
 
 /// Return true if has this feature, need to sync with handleTargetFeatures.
@@ -158,6 +161,7 @@
       .Case("experimental-b", HasB)
       .Case("experimental-v", HasV)
       .Case("experimental-zfh", HasZfh)
+      .Case("experimental-zfinx", HasZfinx)
       .Default(false);
 }
 
@@ -181,6 +185,8 @@
       HasV = true;
     else if (Feature == "+experimental-zfh")
       HasZfh = true;
+    else if (Feature == "+experimental-zfinx")
+      HasZfinx = true;
   }
 
   return true;
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -367,6 +367,18 @@
       return MCDisassembler::Fail;
     }
     Insn = support::endian::read32le(Bytes.data());
+
+    if (STI.getFeatureBits()[RISCV::FeatureExtZfinx]) {
+      LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
+      // Calling the auto-generated decoder function.
+      Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
+                                 STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
+
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
     Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
     Size = 4;
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -49,6 +49,13 @@
                              AssemblerPredicate<(all_of FeatureExtZfh),
                              "'Zfh' (Half-Precision Floating-Point)">;
 
+def FeatureExtZfinx
+    : SubtargetFeature<"experimental-zfinx", "HasStdExtZfinx", "true",
+                       "'Zfinx' (Float in Integer)">;
+def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
+                             AssemblerPredicate<(all_of FeatureExtZfinx),
+                             "'Zfinx' (Float in Integer)">;
+
 def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1224,3 +1224,4 @@
 include "RISCVInstrInfoB.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
+include "RISCVInstrInfoZfinx.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
new file mode 100644
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td
@@ -0,0 +1,322 @@
+//=== RISCVInstrInfoZfinx.td - RISC-V 'Zfinx' instructions -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zfinx'
+// float in integer.
+// This version is still experimental as the 'Zfinx' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+
+
+
+// Zfh Part
+let DecoderNamespace = "RVZfinx", Predicates = [HasStdExtZfinx] in {
+
+// Common
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
+                      string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPR:$rd),
+                 (ins GPR:$rs1, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $funct3">;
+
+
+// Zfh Part
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPFMAH_rrr_frm<RISCVOpcode opcode, string opcodestr>
+    : RVInstR4<0b10, opcode, (outs GPR:$rd),
+               (ins GPR:$rs1, GPR:$rs2, GPR:$rs3, frmarg:$funct3),
+                opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPALUH_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPR:$rd),
+                 (ins GPR:$rs1, GPR:$rs2, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $rs2, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPALUH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPCmpH_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[]>;
+
+
+// F Part
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr>
+    : RVInstR4<0b00, opcode, (outs GPR:$rd),
+               (ins GPR:$rs1, GPR:$rs2, GPR:$rs3, frmarg:$funct3),
+                opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPALUS_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPR:$rd),
+                 (ins GPR:$rs1, GPR:$rs2, frmarg:$funct3), opcodestr,
+                  "$rd, $rs1, $rs2, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPCmpS_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
+                RegisterClass rs1ty, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd), (ins GPR:$rs1),
+              opcodestr, "$rd, $rs1">;
+
+
+// D Part
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPFMAD_rrr_frm<RISCVOpcode opcode, string opcodestr>
+    : RVInstR4<0b01, opcode, (outs GPR:$rd),
+               (ins GPR:$rs1, GPR:$rs2, GPR:$rs3, frmarg:$funct3),
+                opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPALUD_rr_frm<bits<7> funct7, string opcodestr>
+    : RVInstRFrm<funct7, OPC_OP_FP, (outs GPR:$rd),
+                (ins GPR:$rs1, GPR:$rs2, frmarg:$funct3), opcodestr,
+                 "$rd, $rs1, $rs2, $funct3">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Zfinx_FPCmpD_rr<bits<3> funct3, string opcodestr>
+    : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">,
+      Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
+} // ! DecoderNamespace = "RVZfinx", Predicates = [HasStdExtZfinx]
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates alias
+//===----------------------------------------------------------------------===//
+
+
+// Zfh Part
+class Zfinx_FPFMAHDynFrmAlias<Zfinx_FPFMAH_rrr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, GPR:$rs3, 0b111)>;
+
+class Zfinx_FPALUHDynFrmAlias<Zfinx_FPALUH_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, 0b111)>;
+
+
+// F Part
+class Zfinx_FPFMASDynFrmAlias<Zfinx_FPFMAS_rrr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, GPR:$rs3, 0b111)>;
+
+class Zfinx_FPALUSDynFrmAlias<Zfinx_FPALUS_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, 0b111)>;
+class Zfinx_FPUnaryOpDynFrmAlias<Zfinx_FPUnaryOp_r_frm Inst, string OpcodeStr, RegisterClass rdty, RegisterClass rs1ty>
+    : InstAlias<OpcodeStr#" $rd, $rs1",
+                (Inst GPR:$rd, GPR:$rs1, 0b111)>;
+
+
+// D Part
+class Zfinx_FPFMADDynFrmAlias<Zfinx_FPFMAD_rrr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, GPR:$rs3, 0b111)>;
+
+class Zfinx_FPALUDDynFrmAlias<Zfinx_FPALUD_rr_frm Inst, string OpcodeStr>
+    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                (Inst GPR:$rd, GPR:$rs1, GPR:$rs2, 0b111)>;
+
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+
+// Zfh Part
+let Predicates = [HasStdExtZfinx] in {
+def Zfinx_FMADD_H  : Zfinx_FPFMAH_rrr_frm<OPC_MADD, "fmadd.h">,
+                     Sched<[]>;
+def                : Zfinx_FPFMAHDynFrmAlias<Zfinx_FMADD_H, "fmadd.h">;
+def Zfinx_FMSUB_H  : Zfinx_FPFMAH_rrr_frm<OPC_MSUB, "fmsub.h">,
+                     Sched<[]>;
+def                : Zfinx_FPFMAHDynFrmAlias<Zfinx_FMSUB_H, "fmsub.h">;
+def Zfinx_FNMSUB_H : Zfinx_FPFMAH_rrr_frm<OPC_NMSUB, "fnmsub.h">,
+                     Sched<[]>;
+def                : Zfinx_FPFMAHDynFrmAlias<Zfinx_FNMSUB_H, "fnmsub.h">;
+def Zfinx_FNMADD_H : Zfinx_FPFMAH_rrr_frm<OPC_NMADD, "fnmadd.h">,
+                     Sched<[]>;
+def                : Zfinx_FPFMAHDynFrmAlias<Zfinx_FNMADD_H, "fnmadd.h">;
+
+def Zfinx_FADD_H : Zfinx_FPALUH_rr_frm<0b0000010, "fadd.h">,
+                   Sched<[]>;
+def              : Zfinx_FPALUHDynFrmAlias<Zfinx_FADD_H, "fadd.h">;
+def Zfinx_FSUB_H : Zfinx_FPALUH_rr_frm<0b0000110, "fsub.h">,
+                   Sched<[]>;
+def              : Zfinx_FPALUHDynFrmAlias<Zfinx_FSUB_H, "fsub.h">;
+def Zfinx_FMUL_H : Zfinx_FPALUH_rr_frm<0b0001010, "fmul.h">,
+                   Sched<[]>;
+def              : Zfinx_FPALUHDynFrmAlias<Zfinx_FMUL_H, "fmul.h">;
+def Zfinx_FDIV_H : Zfinx_FPALUH_rr_frm<0b0001110, "fdiv.h">,
+                   Sched<[]>;
+def              : Zfinx_FPALUHDynFrmAlias<Zfinx_FDIV_H, "fdiv.h">;
+
+def Zfinx_FSQRT_H : Zfinx_FPUnaryOp_r_frm<0b0101110, FPR16, FPR16, "fsqrt.h">,
+                    Sched<[]> {
+  let rs2 = 0b00000;
+}
+def               : Zfinx_FPUnaryOpDynFrmAlias<Zfinx_FSQRT_H, "fsqrt.h", FPR16, FPR16>;
+
+
+def Zfinx_FSGNJ_H  : Zfinx_FPALUH_rr<0b0010010, 0b000, "fsgnj.h">,
+                     Sched<[]>;
+def Zfinx_FSGNJN_H : Zfinx_FPALUH_rr<0b0010010, 0b001, "fsgnjn.h">,
+                     Sched<[]>;
+def Zfinx_FSGNJX_H : Zfinx_FPALUH_rr<0b0010010, 0b010, "fsgnjx.h">,
+                     Sched<[]>;
+def Zfinx_FMIN_H   : Zfinx_FPALUH_rr<0b0010110, 0b000, "fmin.h">,
+                     Sched<[]>;
+def Zfinx_FMAX_H   : Zfinx_FPALUH_rr<0b0010110, 0b001, "fmax.h">,
+                     Sched<[]>;
+
+def Zfinx_FEQ_H : Zfinx_FPCmpH_rr<0b010, "feq.h">;
+def Zfinx_FLT_H : Zfinx_FPCmpH_rr<0b001, "flt.h">;
+def Zfinx_FLE_H : Zfinx_FPCmpH_rr<0b000, "fle.h">;
+
+def Zfinx_FCLASS_H : Zfinx_FPUnaryOp_r<0b1110010, 0b001, GPR, FPR16, "fclass.h">,
+               Sched<[]> {
+  let rs2 = 0b00000;
+}
+
+
+// F Part
+def Zfinx_FMADD_S  : Zfinx_FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">,
+                     Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
+def                : Zfinx_FPFMASDynFrmAlias<Zfinx_FMADD_S, "fmadd.s">;
+def Zfinx_FMSUB_S  : Zfinx_FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">,
+                     Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
+def                : Zfinx_FPFMASDynFrmAlias<Zfinx_FMSUB_S, "fmsub.s">;
+def Zfinx_FNMSUB_S : Zfinx_FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">,
+                     Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
+def                : Zfinx_FPFMASDynFrmAlias<Zfinx_FNMSUB_S, "fnmsub.s">;
+def Zfinx_FNMADD_S : Zfinx_FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">,
+                     Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
+def                : Zfinx_FPFMASDynFrmAlias<Zfinx_FNMADD_S, "fnmadd.s">;
+
+def Zfinx_FADD_S : Zfinx_FPALUS_rr_frm<0b0000000, "fadd.s">,
+                   Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
+def              : Zfinx_FPALUSDynFrmAlias<Zfinx_FADD_S, "fadd.s">;
+def Zfinx_FSUB_S : Zfinx_FPALUS_rr_frm<0b0000100, "fsub.s">,
+                   Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
+def              : Zfinx_FPALUSDynFrmAlias<Zfinx_FSUB_S, "fsub.s">;
+def Zfinx_FMUL_S : Zfinx_FPALUS_rr_frm<0b0001000, "fmul.s">,
+                   Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
+def              : Zfinx_FPALUSDynFrmAlias<Zfinx_FMUL_S, "fmul.s">;
+def Zfinx_FDIV_S : Zfinx_FPALUS_rr_frm<0b0001100, "fdiv.s">,
+                   Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
+def              : Zfinx_FPALUSDynFrmAlias<Zfinx_FDIV_S, "fdiv.s">;
+
+def Zfinx_FSQRT_S : Zfinx_FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">,
+                    Sched<[WriteFSqrt32, ReadFSqrt32]> {
+  let rs2 = 0b00000;
+}
+def               : Zfinx_FPUnaryOpDynFrmAlias<Zfinx_FSQRT_S, "fsqrt.s", FPR32, FPR32>;
+
+def Zfinx_FSGNJ_S  : Zfinx_FPALUS_rr<0b0010000, 0b000, "fsgnj.s">,
+                     Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
+def Zfinx_FSGNJN_S : Zfinx_FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">,
+                     Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
+def Zfinx_FSGNJX_S : Zfinx_FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">,
+                     Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
+def Zfinx_FMIN_S   : Zfinx_FPALUS_rr<0b0010100, 0b000, "fmin.s">,
+                     Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>;
+def Zfinx_FMAX_S   : Zfinx_FPALUS_rr<0b0010100, 0b001, "fmax.s">,
+                     Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>;
+
+def Zfinx_FEQ_S : Zfinx_FPCmpS_rr<0b010, "feq.s">;
+def Zfinx_FLT_S : Zfinx_FPCmpS_rr<0b001, "flt.s">;
+def Zfinx_FLE_S : Zfinx_FPCmpS_rr<0b000, "fle.s">;
+
+def Zfinx_FCLASS_S : Zfinx_FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
+                     Sched<[WriteFClass32, ReadFClass32]> {
+  let rs2 = 0b00000;
+}
+
+
+// D Part
+def Zfinx_FMADD_D  : Zfinx_FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">,
+                     Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
+def                : Zfinx_FPFMADDynFrmAlias<Zfinx_FMADD_D, "fmadd.d">;
+def Zfinx_FMSUB_D  : Zfinx_FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">,
+                     Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
+def                : Zfinx_FPFMADDynFrmAlias<Zfinx_FMSUB_D, "fmsub.d">;
+def Zfinx_FNMSUB_D : Zfinx_FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">,
+                     Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
+def                : Zfinx_FPFMADDynFrmAlias<Zfinx_FNMSUB_D, "fnmsub.d">;
+def Zfinx_FNMADD_D : Zfinx_FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">,
+                     Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
+def                : Zfinx_FPFMADDynFrmAlias<Zfinx_FNMADD_D, "fnmadd.d">;
+
+def Zfinx_FADD_D : Zfinx_FPALUD_rr_frm<0b0000001, "fadd.d">,
+                   Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+def              : Zfinx_FPALUDDynFrmAlias<Zfinx_FADD_D, "fadd.d">;
+def Zfinx_FSUB_D : Zfinx_FPALUD_rr_frm<0b0000101, "fsub.d">,
+                   Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+def              : Zfinx_FPALUDDynFrmAlias<Zfinx_FSUB_D, "fsub.d">;
+def Zfinx_FMUL_D : Zfinx_FPALUD_rr_frm<0b0001001, "fmul.d">,
+                   Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
+def              : Zfinx_FPALUDDynFrmAlias<Zfinx_FMUL_D, "fmul.d">;
+def Zfinx_FDIV_D : Zfinx_FPALUD_rr_frm<0b0001101, "fdiv.d">,
+                   Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
+def              : Zfinx_FPALUDDynFrmAlias<Zfinx_FDIV_D, "fdiv.d">;
+
+def Zfinx_FSQRT_D : Zfinx_FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">,
+                    Sched<[WriteFSqrt64, ReadFSqrt64]> {
+  let rs2 = 0b00000;
+}
+def               : Zfinx_FPUnaryOpDynFrmAlias<Zfinx_FSQRT_D, "fsqrt.d", FPR64, FPR64>;
+
+
+def Zfinx_FSGNJ_D  : Zfinx_FPALUD_rr<0b0010001, 0b000, "fsgnj.d">,
+                     Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def Zfinx_FSGNJN_D : Zfinx_FPALUD_rr<0b0010001, 0b001, "fsgnjn.d">,
+                     Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def Zfinx_FSGNJX_D : Zfinx_FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">,
+                     Sched<[WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64]>;
+def Zfinx_FMIN_D   : Zfinx_FPALUD_rr<0b0010101, 0b000, "fmin.d">,
+                     Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
+def Zfinx_FMAX_D   : Zfinx_FPALUD_rr<0b0010101, 0b001, "fmax.d">,
+                     Sched<[WriteFMinMax64, ReadFMinMax64, ReadFMinMax64]>;
+
+def Zfinx_FEQ_D : Zfinx_FPCmpD_rr<0b010, "feq.d">;
+def Zfinx_FLT_D : Zfinx_FPCmpD_rr<0b001, "flt.d">;
+def Zfinx_FLE_D : Zfinx_FPCmpD_rr<0b000, "fle.d">;
+
+def Zfinx_FCLASS_D : Zfinx_FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
+                     Sched<[WriteFClass64, ReadFClass64]> {
+  let rs2 = 0b00000;
+}
+} // Predicates = [HasStdExtZfinx]
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -54,6 +54,7 @@
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
   bool HasStdExtZfh = false;
+  bool HasStdExtZfinx = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
@@ -120,6 +121,7 @@
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
+  bool hasStdExtZfinx() const { return HasStdExtZfinx; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
diff --git a/llvm/test/MC/RISCV/rv32d-invalid.s b/llvm/test/MC/RISCV/rv32d-invalid.s
--- a/llvm/test/MC/RISCV/rv32d-invalid.s
+++ b/llvm/test/MC/RISCV/rv32d-invalid.s
@@ -14,8 +14,5 @@
 fld ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
 fsgnjn.d fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 
-# Integer registers where FP regs are expected
-fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-
 # FP registers where integer regs are expected
 fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32zfh-invalid.s b/llvm/test/MC/RISCV/rv32zfh-invalid.s
--- a/llvm/test/MC/RISCV/rv32zfh-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zfh-invalid.s
@@ -29,8 +29,5 @@
 fmsub.h f14, f15, f16, f17, 0 # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
 fnmsub.h f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic
 
-# Integer registers where FP regs are expected
-fadd.h a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-
 # FP registers where integer regs are expected
 fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rvzfinx-valid.s b/llvm/test/MC/RISCV/rvzfinx-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvzfinx-valid.s
@@ -0,0 +1,333 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zfinx %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zfinx - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zfinx %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmadd.h a0, a1, a2, a3
+# CHECK-INST: fmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 6c <unknown>
+
+fmsub.h a0, a1, a2, a3
+# CHECK-INST: fmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 6c <unknown>
+
+fnmsub.h a0, a1, a2, a3
+# CHECK-INST: fnmsub.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 6c <unknown>
+
+fnmadd.h a0, a1, a2, a3
+# CHECK-INST: fnmadd.h a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x6c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 6c <unknown>
+
+fadd.h a0, a1, a2
+# CHECK-INST: fadd.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x04]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 04 <unknown>
+
+fsub.h a0, a1, a2
+# CHECK-INST: fsub.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x0c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 0c <unknown>
+
+fmul.h a0, a1, a2
+# CHECK-INST: fmul.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x14]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 14 <unknown>
+
+fdiv.h a0, a1, a2
+# CHECK-INST: fdiv.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x1c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 1c <unknown>
+
+fsqrt.h a0, a1
+# CHECK-INST: fsqrt.h a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x5c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 5c <unknown>
+
+fsgnj.h a0, a1, a2
+# CHECK-INST: fsgnj.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 24 <unknown>
+
+fsgnjn.h a0, a1, a2
+# CHECK-INST: fsgnjn.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 24 <unknown>
+
+fsgnjx.h a0, a1, a2
+# CHECK-INST: fsgnjx.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x24]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 24 <unknown>
+
+fmin.h a0, a1, a2
+# CHECK-INST: fmin.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 2c <unknown>
+
+fmax.h a0, a1, a2
+# CHECK-INST: fmax.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x2c]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 2c <unknown>
+
+feq.h a0, a1, a2
+# CHECK-INST: feq.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a4 <unknown>
+
+flt.h a0, a1, a2
+# CHECK-INST: flt.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a4 <unknown>
+
+fle.h a0, a1, a2
+# CHECK-INST: fle.h a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a4 <unknown>
+
+fclass.h a0, a1
+# CHECK-INST: fclass.h a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe4]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e4 <unknown>
+
+fmadd.s a0, a1, a2, a3
+# CHECK-INST: fmadd.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 68 <unknown>
+
+fmsub.s a0, a1, a2, a3
+# CHECK-INST: fmsub.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 68 <unknown>
+
+fnmsub.s a0, a1, a2, a3
+# CHECK-INST: fnmsub.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 68 <unknown>
+
+fnmadd.s a0, a1, a2, a3
+# CHECK-INST: fnmadd.s a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x68]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 68 <unknown>
+
+fadd.s a0, a1, a2
+# CHECK-INST: fadd.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x00]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 00 <unknown>
+
+fsub.s a0, a1, a2
+# CHECK-INST: fsub.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x08]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 08 <unknown>
+
+fmul.s a0, a1, a2
+# CHECK-INST: fmul.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x10]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 10 <unknown>
+
+fdiv.s a0, a1, a2
+# CHECK-INST: fdiv.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x18]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 18 <unknown>
+
+fsqrt.s a0, a1
+# CHECK-INST: fsqrt.s a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x58]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 58 <unknown>
+
+fsgnj.s a0, a1, a2
+# CHECK-INST: fsgnj.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x20]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 20 <unknown>
+
+fsgnjn.s a0, a1, a2
+# CHECK-INST: fsgnjn.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x20]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 20 <unknown>
+
+fsgnjx.s a0, a1, a2
+# CHECK-INST: fsgnjx.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x20]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 20 <unknown>
+
+fmin.s a0, a1, a2
+# CHECK-INST: fmin.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x28]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 28 <unknown>
+
+fmax.s a0, a1, a2
+# CHECK-INST: fmax.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x28]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 28 <unknown>
+
+feq.s a0, a1, a2
+# CHECK-INST: feq.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa0]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a0 <unknown>
+
+flt.s a0, a1, a2
+# CHECK-INST: flt.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa0]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a0 <unknown>
+
+fle.s a0, a1, a2
+# CHECK-INST: fle.s a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa0]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a0 <unknown>
+
+fclass.s a0, a1
+# CHECK-INST: fclass.s a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe0]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e0 <unknown>
+
+fmadd.d a0, a1, a2, a3
+# CHECK-INST: fmadd.d a0, a1, a2, a3
+# CHECK-ENCODING: [0x43,0xf5,0xc5,0x6a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 43 f5 c5 6a <unknown>
+
+fmsub.d a0, a1, a2, a3
+# CHECK-INST: fmsub.d a0, a1, a2, a3
+# CHECK-ENCODING: [0x47,0xf5,0xc5,0x6a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 47 f5 c5 6a <unknown>
+
+fnmsub.d a0, a1, a2, a3
+# CHECK-INST: fnmsub.d a0, a1, a2, a3
+# CHECK-ENCODING: [0x4b,0xf5,0xc5,0x6a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4b f5 c5 6a <unknown>
+
+fnmadd.d a0, a1, a2, a3
+# CHECK-INST: fnmadd.d a0, a1, a2, a3
+# CHECK-ENCODING: [0x4f,0xf5,0xc5,0x6a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 4f f5 c5 6a <unknown>
+
+fadd.d a0, a1, a2
+# CHECK-INST: fadd.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x02]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 02 <unknown>
+
+fsub.d a0, a1, a2
+# CHECK-INST: fsub.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x0a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 0a <unknown>
+
+fmul.d a0, a1, a2
+# CHECK-INST: fmul.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x12]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 12 <unknown>
+
+fdiv.d a0, a1, a2
+# CHECK-INST: fdiv.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xf5,0xc5,0x1a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 c5 1a <unknown>
+
+fsqrt.d a0, a1
+# CHECK-INST: fsqrt.d a0, a1
+# CHECK-ENCODING: [0x53,0xf5,0x05,0x5a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 f5 05 5a <unknown>
+
+fsgnj.d a0, a1, a2
+# CHECK-INST: fsgnj.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x22]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 22 <unknown>
+
+fsgnjn.d a0, a1, a2
+# CHECK-INST: fsgnjn.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x22]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 22 <unknown>
+
+fsgnjx.d a0, a1, a2
+# CHECK-INST: fsgnjx.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0x22]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 22 <unknown>
+
+fmin.d a0, a1, a2
+# CHECK-INST: fmin.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0x2a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 2a <unknown>
+
+fmax.d a0, a1, a2
+# CHECK-INST: fmax.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0x2a]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 2a <unknown>
+
+feq.d a0, a1, a2
+# CHECK-INST: feq.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0xa5,0xc5,0xa2]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 a5 c5 a2 <unknown>
+
+flt.d a0, a1, a2
+# CHECK-INST: flt.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x95,0xc5,0xa2]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 c5 a2 <unknown>
+
+fle.d a0, a1, a2
+# CHECK-INST: fle.d a0, a1, a2
+# CHECK-ENCODING: [0x53,0x85,0xc5,0xa2]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 85 c5 a2 <unknown>
+
+fclass.d a0, a1
+# CHECK-INST: fclass.d a0, a1
+# CHECK-ENCODING: [0x53,0x95,0x05,0xe2]
+# CHECK-ERROR: 'Zfinx' (Float in Integer)
+# CHECK-UNKNOWN: 53 95 05 e2 <unknown>