Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -280,10 +280,7 @@
   };
 
   struct VTypeOp {
-    RISCVVSEW Sew;
-    RISCVVLMUL Lmul;
-    bool TailAgnostic;
-    bool MaskAgnostic;
+    unsigned Val;
   };
 
   SMLoc StartLoc, EndLoc;
@@ -720,7 +717,7 @@
   }
 
   StringRef getSysReg() const {
-    assert(Kind == KindTy::SystemRegister && "Invalid access!");
+    assert(Kind == KindTy::SystemRegister && "Invalid type access!");
     return StringRef(SysReg.Data, SysReg.Length);
   }
 
@@ -734,55 +731,9 @@
     return Tok;
   }
 
-  static StringRef getSEWStr(RISCVVSEW Sew) {
-    switch (Sew) {
-    case RISCVVSEW::SEW_8:
-      return "e8";
-    case RISCVVSEW::SEW_16:
-      return "e16";
-    case RISCVVSEW::SEW_32:
-      return "e32";
-    case RISCVVSEW::SEW_64:
-      return "e64";
-    case RISCVVSEW::SEW_128:
-      return "e128";
-    case RISCVVSEW::SEW_256:
-      return "e256";
-    case RISCVVSEW::SEW_512:
-      return "e512";
-    case RISCVVSEW::SEW_1024:
-      return "e1024";
-    }
-    llvm_unreachable("Unknown SEW.");
-  }
-
-  static StringRef getLMULStr(RISCVVLMUL Lmul) {
-    switch (Lmul) {
-    case RISCVVLMUL::LMUL_1:
-      return "m1";
-    case RISCVVLMUL::LMUL_2:
-      return "m2";
-    case RISCVVLMUL::LMUL_4:
-      return "m4";
-    case RISCVVLMUL::LMUL_8:
-      return "m8";
-    case RISCVVLMUL::LMUL_F2:
-      return "mf2";
-    case RISCVVLMUL::LMUL_F4:
-      return "mf4";
-    case RISCVVLMUL::LMUL_F8:
-      return "mf8";
-    }
-    llvm_unreachable("Unknown LMUL.");
-  }
-
-  StringRef getVType(SmallString<32> &Buf) const {
-    assert(Kind == KindTy::VType && "Invalid access!");
-    Buf.append(getSEWStr(VType.Sew));
-    Buf.append(",");
-    Buf.append(getLMULStr(VType.Lmul));
-
-    return Buf.str();
+  unsigned getVType() const {
+    assert(Kind == KindTy::VType && "Invalid type access!");
+    return VType.Val;
   }
 
   void print(raw_ostream &OS) const override {
@@ -800,11 +751,13 @@
     case KindTy::SystemRegister:
       OS << "<sysreg: " << getSysReg() << '>';
       break;
-    case KindTy::VType:
-      SmallString<32> VTypeBuf;
-      OS << "<vtype: " << getVType(VTypeBuf) << '>';
+    case KindTy::VType: {
+      OS << "<vtype: ";
+      RISCVVType::printVType(getVType(), OS);
+      OS << '>';
       break;
     }
+    }
   }
 
   static std::unique_ptr<RISCVOperand> createToken(StringRef Str, SMLoc S,
@@ -848,21 +801,10 @@
     return Op;
   }
 
-  static std::unique_ptr<RISCVOperand>
-  createVType(unsigned Sew, unsigned Lmul, bool Fractional, bool TailAgnostic,
-              bool MaskAgnostic, SMLoc S, bool IsRV64) {
+  static std::unique_ptr<RISCVOperand> createVType(unsigned VTypeI, SMLoc S,
+                                                   bool IsRV64) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::VType);
-    unsigned SewLog2 = Log2_32(Sew / 8);
-    unsigned LmulLog2 = Log2_32(Lmul);
-    Op->VType.Sew = static_cast<RISCVVSEW>(SewLog2);
-    if (Fractional) {
-      unsigned Flmul = 8 - LmulLog2;
-      Op->VType.Lmul = static_cast<RISCVVLMUL>(Flmul);
-    } else {
-      Op->VType.Lmul = static_cast<RISCVVLMUL>(LmulLog2);
-    }
-    Op->VType.TailAgnostic = TailAgnostic;
-    Op->VType.MaskAgnostic = MaskAgnostic;
+    Op->VType.Val = VTypeI;
     Op->StartLoc = S;
     Op->IsRV64 = IsRV64;
     return Op;
@@ -927,9 +869,7 @@
 
   void addVTypeIOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
-    unsigned VTypeI = RISCVVType::encodeVTYPE(
-        VType.Lmul, VType.Sew, VType.TailAgnostic, VType.MaskAgnostic);
-    Inst.addOperand(MCOperand::createImm(VTypeI));
+    Inst.addOperand(MCOperand::createImm(getVType()));
   }
 
   // Returns the rounding mode represented by this RISCVOperand. Should only
@@ -1628,8 +1568,20 @@
   if (getLexer().getKind() != AsmToken::EndOfStatement)
     return MatchOperand_NoMatch;
 
-  Operands.push_back(RISCVOperand::createVType(
-      Sew, Lmul, Fractional, TailAgnostic, MaskAgnostic, S, isRV64()));
+  unsigned SewLog2 = Log2_32(Sew / 8);
+  unsigned LmulLog2 = Log2_32(Lmul);
+  RISCVVSEW VSEW = static_cast<RISCVVSEW>(SewLog2);
+  RISCVVLMUL VLMUL;
+  if (Fractional) {
+    unsigned Flmul = 8 - LmulLog2;
+    VLMUL = static_cast<RISCVVLMUL>(Flmul);
+  } else {
+    VLMUL = static_cast<RISCVVLMUL>(LmulLog2);
+  }
+
+  unsigned VTypeI =
+      RISCVVType::encodeVTYPE(VLMUL, VSEW, TailAgnostic, MaskAgnostic);
+  Operands.push_back(RISCVOperand::createVType(VTypeI, S, isRV64()));
 
   return MatchOperand_Success;
 }
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -171,30 +171,7 @@
 void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
-  unsigned Sew = (Imm >> 2) & 0x7;
-  unsigned Lmul = Imm & 0x3;
-  bool Fractional = (Imm >> 5) & 0x1;
-
-  Sew = 0x1 << (Sew + 3);
-  O << "e" << Sew;
-  if (Fractional) {
-    Lmul = 4 - Lmul;
-    Lmul = 0x1 << Lmul;
-    O << ",mf" << Lmul;
-  } else {
-    Lmul = 0x1 << Lmul;
-    O << ",m" << Lmul;
-  }
-  bool TailAgnostic = Imm & 0x40;
-  bool MaskedoffAgnostic = Imm & 0x80;
-  if (TailAgnostic)
-    O << ",ta";
-  else
-    O << ",tu";
-  if (MaskedoffAgnostic)
-    O << ",ma";
-  else
-    O << ",mu";
+  RISCVVType::printVType(Imm, O);
 }
 
 void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
Index: llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
===================================================================
--- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -387,6 +387,24 @@
 
   return VTypeI;
 }
+
+// TODO: This format will change for the V extensions spec v1.0.
+inline static RISCVVLMUL getVLMUL(unsigned VType) {
+  unsigned VLMUL = (VType & 0x3) | ((VType & 0x20) >> 3);
+  return static_cast<RISCVVLMUL>(VLMUL);
+}
+
+inline static RISCVVSEW getVSEW(unsigned VType) {
+  unsigned VSEW = (VType >> 2) & 0x7;
+  return static_cast<RISCVVSEW>(VSEW);
+}
+
+inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
+
+inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
+
+void printVType(unsigned VType, raw_ostream &OS);
+
 } // namespace RISCVVType
 
 namespace RISCVVPseudosTable {
Index: llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
+++ llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
@@ -101,4 +101,40 @@
 
 } // namespace RISCVVPseudosTable
 
+void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
+  RISCVVSEW VSEW = getVSEW(VType);
+  RISCVVLMUL VLMUL = getVLMUL(VType);
+
+  unsigned Sew = 1 << (static_cast<unsigned>(VSEW) + 3);
+  OS << "e" << Sew;
+
+  switch (VLMUL) {
+  case RISCVVLMUL::LMUL_1:
+  case RISCVVLMUL::LMUL_2:
+  case RISCVVLMUL::LMUL_4:
+  case RISCVVLMUL::LMUL_8: {
+    unsigned LMul = 1 << static_cast<unsigned>(VLMUL);
+    OS << ",m" << LMul;
+    break;
+  }
+  case RISCVVLMUL::LMUL_F2:
+  case RISCVVLMUL::LMUL_F4:
+  case RISCVVLMUL::LMUL_F8: {
+    unsigned LMul = 1 << (8 - static_cast<unsigned>(VLMUL));
+    OS << ",mf" << LMul;
+    break;
+  }
+  }
+
+  if (isTailAgnostic(VType))
+    OS << ",ta";
+  else
+    OS << ",tu";
+
+  if (isMaskAgnostic(VType))
+    OS << ",ma";
+  else
+    OS << ",mu";
+}
+
 } // namespace llvm