Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -195,7 +195,8 @@ SmallVectorImpl &Instructions); void expandLoadAddressSym(const MCOperand *DstRegOp, const MCOperand *SymOp, - SMLoc IDLoc, SmallVectorImpl &Instructions); + bool Is32BitSym, SMLoc IDLoc, + SmallVectorImpl &Instructions); void expandMemInst(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions, bool isLoad, @@ -1891,7 +1892,7 @@ assert((ImmOp->isImm() || ImmOp->isExpr()) && "expected immediate operand kind"); if (!ImmOp->isImm()) { - expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions); + expandLoadAddressSym(DstRegOp, ImmOp, Is32BitImm, IDLoc, Instructions); return false; } const MCOperand *SrcRegOp = &Inst.getOperand(1); @@ -1913,7 +1914,7 @@ assert((ImmOp->isImm() || ImmOp->isExpr()) && "expected immediate operand kind"); if (!ImmOp->isImm()) { - expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions); + expandLoadAddressSym(DstRegOp, ImmOp, Is32BitImm, IDLoc, Instructions); return false; } @@ -1923,10 +1924,13 @@ return false; } -void -MipsAsmParser::expandLoadAddressSym(const MCOperand *DstRegOp, - const MCOperand *SymOp, SMLoc IDLoc, - SmallVectorImpl &Instructions) { +void MipsAsmParser::expandLoadAddressSym( + const MCOperand *DstRegOp, const MCOperand *SymOp, bool Is32BitSym, + SMLoc IDLoc, SmallVectorImpl &Instructions) { + if (Is32BitSym && isGP64bit()) + Warning(IDLoc, + "instruction loads a 32-bit address on a 64-bit architecture"); + MCInst tmpInst; unsigned RegNo = DstRegOp->getReg(); const MCSymbolRefExpr *Symbol = cast(SymOp->getExpr()); @@ -1936,7 +1940,7 @@ const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(Symbol->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO, getContext()); - if (isGP64bit()) { + if (!Is32BitSym) { // If it's a 64-bit architecture, expand to: // la d,sym => lui d,highest(sym) // ori d,d,higher(sym) Index: test/MC/Mips/mips-expansions-bad.s =================================================================== --- test/MC/Mips/mips-expansions-bad.s +++ test/MC/Mips/mips-expansions-bad.s @@ -13,5 +13,9 @@ la $5, 0x100000000($6) # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate + la $5, symbol + # 64-BIT: :[[@LINE-1]]:3: warning: instruction loads a 32-bit address on a 64-bit architecture + # 64-BIT: lui $5, %hi(symbol) + # 64-BIT: ori $5, $5, %lo(symbol) dli $5, 1 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture Index: test/MC/Mips/mips-expansions.s =================================================================== --- test/MC/Mips/mips-expansions.s +++ test/MC/Mips/mips-expansions.s @@ -23,18 +23,6 @@ # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 # CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 -# CHECK: .set mips64 -# CHECK: lui $8, %highest(symbol) # encoding: [A,A,0x08,0x3c] - # fixup A - offset: 0, value: symbol@HIGHEST, kind: fixup_Mips_HIGHEST -# CHECK: ori $8, $8, %higher(symbol) # encoding: [A,A,0x08,0x35] - # fixup A - offset: 0, value: symbol@HIGHER, kind: fixup_Mips_HIGHER -# CHECK: dsll $8, $8, 16 # encoding: [0x38,0x44,0x08,0x00] -# CHECK: ori $8, $8, %hi(symbol) # encoding: [A,A,0x08,0x35] - # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 -# CHECK: dsll $8, $8, 16 # encoding: [0x38,0x44,0x08,0x00] -# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] - # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 -# CHECK: .set mips32r2 # CHECK: lui $10, %hi(symbol) # encoding: [A,A,0x0a,0x3c] # CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 # CHECK: addu $10, $10, $4 # encoding: [0x21,0x50,0x44,0x01] @@ -79,9 +67,6 @@ la $a0, 20($a1) la $7,65538($8) la $t0, symbol - .set mips64 - la $t0, symbol - .set mips32r2 .set noat lw $t2, symbol($a0)