Index: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -179,7 +179,7 @@
   bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
                          SmallVectorImpl<MCInst> &Instructions);
 
-  bool expandLoadImm(MCInst &Inst, SMLoc IDLoc,
+  bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions);
 
   bool expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
@@ -1609,13 +1609,9 @@
   switch (Inst.getOpcode()) {
   default: llvm_unreachable("unimplemented expansion");
   case Mips::LoadImm32:
-    return expandLoadImm(Inst, IDLoc, Instructions);
+    return expandLoadImm(Inst, true, IDLoc, Instructions);
   case Mips::LoadImm64:
-    if (!isGP64bit()) {
-      Error(IDLoc, "instruction requires a 64-bit architecture");
-      return true;
-    }
-    return expandLoadImm(Inst, IDLoc, Instructions);
+    return expandLoadImm(Inst, false, IDLoc, Instructions);
   case Mips::LoadAddrImm32:
     return expandLoadAddressImm(Inst, IDLoc, Instructions);
   case Mips::LoadAddrReg32:
@@ -1715,8 +1711,13 @@
   return false;
 }
 
-bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
+bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                                   SmallVectorImpl<MCInst> &Instructions) {
+  if (!Is32BitImm && !isGP64bit()) {
+    Error(IDLoc, "instruction requires a 64-bit architecture");
+    return true;
+  }
+
   MCInst tmpInst;
   const MCOperand &ImmOp = Inst.getOperand(1);
   assert(ImmOp.isImm() && "expected immediate operand kind");
@@ -1757,8 +1758,8 @@
     Instructions.push_back(tmpInst);
     createLShiftOri<0>(Bits15To0, Reg, IDLoc, Instructions);
   } else if ((ImmValue & (0xffffLL << 48)) == 0) {
-    if (!isGP64bit()) {
-      Error(IDLoc, "instruction requires a 64-bit architecture");
+    if (Is32BitImm) {
+      Error(IDLoc, "instruction requires a 32-bit immediate");
       return true;
     }
 
@@ -1786,8 +1787,8 @@
     createLShiftOri<0>(Bits31To16, Reg, IDLoc, Instructions);
     createLShiftOri<16>(Bits15To0, Reg, IDLoc, Instructions);
   } else {
-    if (!isGP64bit()) {
-      Error(IDLoc, "instruction requires a 64-bit architecture");
+    if (Is32BitImm) {
+      Error(IDLoc, "instruction requires a 32-bit immediate");
       return true;
     }
 
Index: llvm/trunk/test/MC/Mips/mips-expansions-bad.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips-expansions-bad.s
+++ llvm/trunk/test/MC/Mips/mips-expansions-bad.s
@@ -1,8 +1,11 @@
 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
-# RUN: FileCheck %s < %t1
+# RUN: FileCheck %s < %t1 --check-prefix=32-BIT
+# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 2>&1 | \
+# RUN:   FileCheck %s --check-prefix=64-BIT
 
   .text
   li $5, 0x100000000
-  # CHECK: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
   dli $5, 1
-  # CHECK: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture